diff --git a/stm32cube/stm32f4xx/README b/stm32cube/stm32f4xx/README
index 55f264bebbc0c871b298821159610670c2b245d7..831f2af90d15e6f52d9adeb9164ef24a4baf33ed 100644
--- a/stm32cube/stm32f4xx/README
+++ b/stm32cube/stm32f4xx/README
@@ -6,7 +6,7 @@ Origin:
http://www.st.com/en/embedded-software/stm32cubef4.html
Status:
- version 1.21.0
+ version 1.24.1
Purpose:
ST Microelectronics official MCU package for STM32F4 series.
@@ -23,7 +23,7 @@ URL:
http://www.st.com/en/embedded-software/stm32cubef4.html
commit:
- version 1.21.0
+ version 1.24.1
Maintained-by:
External
@@ -54,14 +54,6 @@ Patch List:
drivers/include/stm32f4xx_hal_conf.h
drivers/src/Legacy/stm32f4_hal_can.c
- *Use of (__packed uint32_t *) produces warning
- Using GNU 8.2.0, (__packed uint32_t *) generates warning.
- Replace with CMSIS macros __UNALIGNED_UINT32_READ and
- __UNALIGNED_UINT32_WRITE.
- Impacted files:
- drivers/include/stm32f4xx_ll_usb.c
- ST Bug tracker ID: 61325
-
*Fix warnings for extraneous parentheses
Using clang 7.0.1, if ((htim->State == HAL_TIM_STATE_BUSY))
generates warnings. Remove the extra parentheses
diff --git a/stm32cube/stm32f4xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32f4xx/drivers/include/Legacy/stm32_hal_legacy.h
index 0ae9d0b24873bae3a6afa2fe2c4d3d7c0231cd35..889db8f18f339bdb159c058cd58a96ff96134c02 100644
--- a/stm32cube/stm32f4xx/drivers/include/Legacy/stm32_hal_legacy.h
+++ b/stm32cube/stm32f4xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -7,36 +7,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
#ifdef __cplusplus
extern "C" {
@@ -110,6 +94,10 @@
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
/**
* @}
*/
@@ -274,7 +262,100 @@
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+#if defined(STM32L4)
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#endif /* STM32L4 */
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#endif /* STM32H7 */
/**
* @}
@@ -355,6 +436,38 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
/**
* @}
@@ -381,12 +494,12 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#else
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
@@ -427,16 +540,25 @@
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+#endif
+
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -456,78 +578,6 @@
* @}
*/
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
- #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
- #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
- #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
- #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
- #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
- #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-
- #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
- #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
- #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
- #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
- #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
- #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
- #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
- #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
- #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
- #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
- #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
- #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
- #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
- #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-
-#endif /* STM32H7 */
-
-
-/**
- * @}
- */
-
-
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@@ -696,6 +746,16 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+ #define I2S_IT_TXE I2S_IT_TXP
+ #define I2S_IT_RXNE I2S_IT_RXP
+
+ #define I2S_FLAG_TXE I2S_FLAG_TXP
+ #define I2S_FLAG_RXNE I2S_FLAG_RXP
+ #define I2S_FLAG_FRE I2S_FLAG_TIFRE
+#endif
+
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
@@ -820,6 +880,21 @@
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+ #define SPI_IT_TXE SPI_IT_TXP
+ #define SPI_IT_RXNE SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
/**
* @}
*/
@@ -887,6 +962,15 @@
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
/**
* @}
*/
@@ -1047,8 +1131,9 @@
* @}
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
@@ -1072,7 +1157,7 @@
/**
* @}
*/
-#endif /* STM32L4 || STM32F7*/
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@@ -1164,6 +1249,28 @@
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
/**
* @}
*/
@@ -1243,6 +1350,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
/**
* @}
*/
@@ -1456,10 +1571,17 @@
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#if defined(STM32H7)
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
@@ -1725,6 +1847,10 @@
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+#if defined(STM32H7)
+ #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
/**
* @}
*/
@@ -2932,7 +3058,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0)
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3064,6 +3190,7 @@
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
#endif
/**
* @}
@@ -3291,6 +3418,21 @@
* @}
*/
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
@@ -3303,7 +3445,7 @@
}
#endif
-#endif /* ___STM32_HAL_LEGACY */
+#endif /* STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/Legacy/stm32f4xx_hal_can_legacy.h b/stm32cube/stm32f4xx/drivers/include/Legacy/stm32f4xx_hal_can_legacy.h
index fd809622a65ede4e570fda86790fe8c7ec9b8de5..e74a814fed331161447c582e75476712e4b83a8b 100644
--- a/stm32cube/stm32f4xx/drivers/include/Legacy/stm32f4xx_hal_can_legacy.h
+++ b/stm32cube/stm32f4xx/drivers/include/Legacy/stm32f4xx_hal_can_legacy.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32_assert_template.h b/stm32cube/stm32f4xx/drivers/include/stm32_assert_template.h
index d14016f7f015b4caf8757236fe5e7dde5353b192..4711b65d8f92aad7451e91ba385a3a1625ca737a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32_assert_template.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32_assert_template.h
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal.h
index 93bc167bda96b1bc9eedad6a193e080a9d06d227..678f7bf1e93ec94f6cd5076d142ccb180b4ea5af 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal.h
@@ -7,29 +7,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -253,7 +237,9 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
-void HAL_GetUID(uint32_t *UID);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
defined(STM32F469xx) || defined(STM32F479xx)
void HAL_EnableMemorySwappingBank(void);
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc.h
index dc93c771724e25426b266d244645c4eb8ad82388..0dfff39b1dc72818039a39b14ef30bab8be2c950 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -72,53 +56,53 @@
*/
typedef struct
{
- uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
- all the ADCs.
- This parameter can be a value of @ref ADC_ClockPrescaler */
- uint32_t Resolution; /*!< Configures the ADC resolution.
- This parameter can be a value of @ref ADC_Resolution */
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
- This parameter can be a value of @ref ADC_Data_align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
- This parameter can be a value of @ref ADC_EOCSelection.
- Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
- Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
- or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
- Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
- If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge by default.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
- uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
- If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
- This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
- or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
- This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
+ all the ADCs.
+ This parameter can be a value of @ref ADC_ClockPrescaler */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADC_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADC_EOCSelection.
+ Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
+ Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
+ or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
+ Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
+ If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
+ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge by default.
+ This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
+ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
+ This parameter can be set to ENABLE or DISABLE. */
}ADC_InitTypeDef;
@@ -160,7 +144,7 @@ typedef struct
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
This parameter can be a value of @ref ADC_channels */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
+ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
@@ -203,7 +187,11 @@ typedef struct
/**
* @brief ADC handle Structure definition
*/
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
typedef struct
+#endif
{
ADC_TypeDef *Instance; /*!< Register base address */
@@ -218,7 +206,39 @@ typedef struct
__IO uint32_t State; /*!< ADC communication state */
__IO uint32_t ErrorCode; /*!< ADC Error code */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -236,6 +256,9 @@ typedef struct
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -456,7 +479,17 @@ typedef struct
* @param __HANDLE__ ADC handle
* @retval None
*/
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
/**
* @brief Enable the ADC peripheral.
@@ -531,6 +564,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc_ex.h
index c61eaff095c795c99c97bc6c26d897af89b2b5c8..6587acc802b804cee2ba7a6f687eb02218744f95 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_adc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -71,58 +55,58 @@
*/
typedef struct
{
- uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t InjectedRank; /*!< Rank in the injected group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
- Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
- This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
- If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADC_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
/**
@@ -235,15 +219,11 @@ typedef struct
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
STM32F412Vx || STM32F412Rx || STM32F412Cx */
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18)
-#endif /* STM32F413xx || STM32F423xx */
-
-#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
-#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_can.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_can.h
index 379090a386d63a6799e3cdbede99c1bcf8d40450..0611a6521a342766bdc80a2ba1d9a7c7834af073 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_can.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_can.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2016 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -151,7 +135,7 @@ typedef struct
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set to ENABLE or DISABLE. */
+ This parameter can be a value of @ref CAN_filter_activation */
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
For single CAN instances, this parameter is meaningless.
@@ -233,8 +217,58 @@ typedef struct __CAN_HandleTypeDef
__IO uint32_t ErrorCode; /*!< CAN Error code.
This parameter can be a value of @ref CAN_Error_Code */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
+ void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
+ void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
+ void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
+ void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
+ void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
+ void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
+ void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
+ void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
+ void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
+ void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
+ void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
+ void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
+
+ void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
+ void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
} CAN_HandleTypeDef;
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL CAN common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
+ HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
+ HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
+ HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
+ HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
+ HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
+ HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
+ HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
+ HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
+ HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
+ HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
+
+ HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
+ HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
+
+} HAL_CAN_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CAN Callback pointer definition
+ */
+typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
+
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -272,6 +306,11 @@ typedef struct __CAN_HandleTypeDef
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
+
/**
* @}
*/
@@ -364,6 +403,15 @@ typedef struct __CAN_HandleTypeDef
* @}
*/
+/** @defgroup CAN_filter_activation CAN Filter Activation
+ * @{
+ */
+#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
+#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
+/**
+ * @}
+ */
+
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
@@ -496,7 +544,15 @@ typedef struct __CAN_HandleTypeDef
* @param __HANDLE__ CAN handle.
* @retval None
*/
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_CAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @brief Enable the specified CAN interrupts.
@@ -587,6 +643,12 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/**
* @}
*/
@@ -738,6 +800,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+ ((ACTIVATION) == CAN_FILTER_ENABLE))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cec.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cec.h
index aef0a35c514aa1162f15749310b48a0fcc450481..3519cbd8638f6daa36845dd827b345a887642b81 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cec.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cec.h
@@ -6,45 +6,30 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CEC_H
-#define __STM32F4xx_HAL_CEC_H
+#ifndef STM32F4xx_HAL_CEC_H
+#define STM32F4xx_HAL_CEC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F446xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined (CEC)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -123,11 +108,11 @@ typedef struct
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
-}CEC_InitTypeDef;
+} CEC_InitTypeDef;
/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * @brief HAL CEC State definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -164,25 +149,16 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
+typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+typedef struct __CEC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
@@ -205,7 +181,40 @@ typedef struct
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
-}CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __CEC_HandleTypeDef
+ *hcec); /*!< CEC Tx Transfer completed callback */
+ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
+
+ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
+
+#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
+} CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL CEC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
+ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
+ HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
+ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
+ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
+} HAL_CEC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CEC Callback pointer definition
+ */
+typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
+typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -214,11 +223,29 @@ typedef struct
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+/** @defgroup CEC_State_Definition CEC State Code Definition
+ * @{
+ */
+#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
+/**
+ * @}
+ */
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
-#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@@ -228,6 +255,9 @@ typedef struct
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -235,14 +265,14 @@ typedef struct
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
-#define CEC_DEFAULT_SFT 0x00000000U
-#define CEC_0_5_BITPERIOD_SFT 0x00000001U
-#define CEC_1_5_BITPERIOD_SFT 0x00000002U
-#define CEC_2_5_BITPERIOD_SFT 0x00000003U
-#define CEC_3_5_BITPERIOD_SFT 0x00000004U
-#define CEC_4_5_BITPERIOD_SFT 0x00000005U
-#define CEC_5_5_BITPERIOD_SFT 0x00000006U
-#define CEC_6_5_BITPERIOD_SFT 0x00000007U
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
@@ -250,7 +280,7 @@ typedef struct
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
-#define CEC_STANDARD_TOLERANCE 0x00000000U
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
@@ -259,7 +289,7 @@ typedef struct
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
-#define CEC_NO_RX_STOP_ON_BRE 0x00000000U
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
@@ -268,7 +298,7 @@ typedef struct
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
-#define CEC_BRE_ERRORBIT_NO_GENERATION 0x00000000U
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
@@ -277,7 +307,7 @@ typedef struct
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
-#define CEC_LBPE_ERRORBIT_NO_GENERATION 0x00000000U
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
@@ -286,7 +316,7 @@ typedef struct
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION 0x00000000U
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
@@ -295,7 +325,7 @@ typedef struct
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
-#define CEC_SFT_START_ON_TXSOM 0x00000000U
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
@@ -304,7 +334,7 @@ typedef struct
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
-#define CEC_REDUCED_LISTENING_MODE 0x00000000U
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
@@ -313,7 +343,7 @@ typedef struct
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
-#define CEC_CFGR_OAR_LSB_POS 16U
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
@@ -321,7 +351,7 @@ typedef struct
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
-#define CEC_INITIATOR_LSB_POS 4U
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
/**
* @}
*/
@@ -329,22 +359,22 @@ typedef struct
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
-#define CEC_OWN_ADDRESS_NONE ((uint16_t)0x0000) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0001) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0002) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0004) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0008) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0010) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0020) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0040) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0080) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0100) /* Logical Address 9 */
-#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0200) /* Logical Address 10 */
-#define CEC_OWN_ADDRESS_10 ((uint16_t)0x0400) /* Logical Address 11 */
-#define CEC_OWN_ADDRESS_11 ((uint16_t)0x0800) /* Logical Address 12 */
-#define CEC_OWN_ADDRESS_12 ((uint16_t)0x1000) /* Logical Address 13 */
-#define CEC_OWN_ADDRESS_13 ((uint16_t)0x2000) /* Logical Address 14 */
-#define CEC_OWN_ADDRESS_14 ((uint16_t)0x4000) /* Logical Address 15 */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
/**
* @}
*/
@@ -393,7 +423,7 @@ typedef struct
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -427,11 +457,19 @@ typedef struct
* @param __HANDLE__ CEC handle.
* @retval None
*/
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
-
+#else
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0)
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
@@ -605,6 +643,15 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -613,9 +660,10 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
@@ -714,7 +762,7 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
/**
* @}
*/
@@ -734,12 +782,13 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
* @}
*/
-#endif /* STM32F446xx */
+
+#endif /* CEC */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_CEC_H */
+#endif /* STM32F4xxHAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_conf.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_conf.h
index 9588cb4984ce0885b971447a372eb45744dd9574..edb84ad08a5c3b0a3779ebce02bcca3c0e825796 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_conf.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_conf.h
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -76,6 +60,9 @@
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+/* #define HAL_I2C_MODULE_ENABLED */
+#define HAL_SMBUS_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
@@ -168,6 +155,45 @@
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
@@ -263,6 +289,10 @@
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
@@ -339,6 +369,10 @@
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cortex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cortex.h
index ff70ca1f7fb7545ec701a461d764a7aa3166ffcd..028ea5e6a0c51ca8eaba3058a0342229c5bfd957 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cortex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cortex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_crc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_crc.h
index 164f72d96abebb7203c43d0a4e8e330a8b005575..bbd58a581ae0b7d9741afd9f6a8ae5d953a44fa4 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_crc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_crc.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CRC_H
-#define __STM32F4xx_HAL_CRC_H
+#ifndef STM32F4xx_HAL_CRC_H
+#define STM32F4xx_HAL_CRC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,8 +32,7 @@
* @{
*/
-/** @defgroup CRC CRC
- * @brief CRC HAL module driver
+/** @addtogroup CRC
* @{
*/
@@ -58,8 +41,8 @@
* @{
*/
-/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
- * @{
+/**
+ * @brief CRC HAL State Structure definition
*/
typedef enum
{
@@ -68,85 +51,100 @@ typedef enum
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
+} HAL_CRC_StateTypeDef;
-}HAL_CRC_StateTypeDef;
-/**
- * @}
- */
-/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition
- * @{
+/**
+ * @brief CRC Handle Structure definition
*/
typedef struct
{
- CRC_TypeDef *Instance; /*!< Register base address */
+ CRC_TypeDef *Instance; /*!< Register base address */
- HAL_LockTypeDef Lock; /*!< CRC locking object */
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
- __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-}CRC_HandleTypeDef;
+} CRC_HandleTypeDef;
/**
* @}
*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
-/** @brief Resets CRC handle state
- * @param __HANDLE__ CRC handle
+/** @brief Reset CRC handle state.
+ * @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
- * @brief Resets CRC Data Register.
+ * @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @param __VALUE__ 8-bit value to be stored in the ID register
+ * @param __VALUE__ Value to be stored in the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @retval 8-bit value of the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
+/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
+/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
@@ -156,6 +154,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
* @}
*/
+/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
@@ -164,68 +163,6 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
* @}
*/
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRC_Private_Types CRC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRC_Private_Defines CRC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Variables CRC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Constants CRC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRC_Private_Macros CRC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
-
/**
* @}
*/
@@ -242,6 +179,6 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
}
#endif
-#endif /* __STM32F4xx_HAL_CRC_H */
+#endif /* STM32F4xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp.h
index 2e6502280c26a84fef1b4979f3539a3316e2a1ee..835a8aec6ff0757c82a12735920ca0e48ecedc9e 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -41,16 +25,14 @@
extern "C" {
#endif
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-
-#if defined(CRYP)
-
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
+#if defined (AES) || defined (CRYP)
/** @addtogroup CRYP
* @{
*/
@@ -61,753 +43,276 @@
* @{
*/
-/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
- * @{
+/**
+ * @brief CRYP Init Structure definition
*/
typedef struct
{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+ This parameter can be a value of @ref CRYP_Data_Type */
+ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+ 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
+ uint32_t* pKey; /*!< The key used for encryption/decryption */
+ uint32_t* pInitVect; /*!< The initialization vector used also as initialization
+ counter in CTR mode */
+ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
+ AES Algorithm ECB/CBC/CTR/GCM or CCM
+ This parameter can be a value of @ref CRYP_Algorithm_Mode */
+ uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
+ GCM : also known as Additional Authentication Data
+ CCM : named B1 composed of the associated data length and Associated Data. */
+ uint32_t HeaderSize; /*!< The size of header buffer in word */
+ uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
+ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
- uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
+}CRYP_ConfigTypeDef;
- uint8_t* pKey; /*!< The key used for encryption/decryption */
-
- uint8_t* pInitVect; /*!< The initialization vector used also as initialization
- counter in CTR mode */
-
- uint8_t IVSize; /*!< The size of initialization vector.
- This parameter (called nonce size in CCM) is used only
- in AES-128/192/256 encryption/decryption CCM mode */
-
- uint8_t TagSize; /*!< The size of returned authentication TAG.
- This parameter is used only in AES-128/192/256
- encryption/decryption CCM mode */
-
- uint8_t* Header; /*!< The header used in GCM and CCM modes */
-
- uint32_t HeaderSize; /*!< The size of header buffer in bytes */
-
- uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
- This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
-}CRYP_InitTypeDef;
/**
- * @}
+ * @brief CRYP State Structure definition
*/
-/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
- * @{
- */
-
-
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
- HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
+ HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
}HAL_CRYP_STATETypeDef;
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
- * @{
- */
-
-
-typedef enum
-{
- HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
- HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
- HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase
- This is relevant only with CCM and GCM modes */
-}HAL_PhaseTypeDef;
/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
- * @{
+ * @brief CRYP handle Structure definition
*/
-typedef struct
+typedef struct __CRYP_HandleTypeDef
{
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
-
- CRYP_InitTypeDef Init; /*!< CRYP required parameters */
-
- uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- __IO uint16_t CrypInCount; /*!< Counter of inputed data */
+#if defined (CRYP)
+ CRYP_TypeDef *Instance; /*!< CRYP registers base address */
+#else /* AES*/
+ AES_TypeDef *Instance; /*!< AES Register base address */
+#endif /* End AES or CRYP */
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
+ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
- HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
+ FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
+ This parameter can be a value of ENABLE/DISABLE */
- HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
+ uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
+ uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
+ __IO uint16_t CrypHeaderCount; /*!< Counter of header data */
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-}CRYP_HandleTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Key_Size CRYP Key Size
- * @{
- */
-#define CRYP_KEYSIZE_128B 0x00000000U
-#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
-#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-/**
- * @}
- */
+ __IO uint16_t CrypInCount; /*!< Counter of input data */
-/** @defgroup CRYP_Data_Type CRYP Data Type
- * @{
- */
-#define CRYP_DATATYPE_32B 0x00000000U
-#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-/**
- * @}
- */
+ __IO uint16_t CrypOutCount; /*!< Counter of output data */
-/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
- * @{
- */
-#define CRYP_CR_ALGOMODE_DIRECTION 0x0008003CU
-#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT 0x00000000U
-#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT 0x00000004U
-#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT 0x00000008U
-#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT 0x0000000CU
-#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT 0x00000010U
-#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT 0x00000014U
-#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT 0x00000018U
-#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT 0x0000001CU
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT 0x00000020U
-#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT 0x00000024U
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT 0x00000028U
-#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT 0x0000002CU
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT 0x00000030U
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT 0x00000034U
-/**
- * @}
- */
+ uint16_t Size; /*!< length of input data in word */
-/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
- * @{
- */
-#define CRYP_IT_INI ((uint32_t)CRYP_IMSCR_INIM) /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI ((uint32_t)CRYP_IMSCR_OUTIM) /*!< Output FIFO Interrupt */
-/**
- * @}
- */
+ uint32_t Phase; /*!< CRYP peripheral phase */
-/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
- * @{
- */
-#define CRYP_FLAG_BUSY 0x00000010U /*!< The CRYP core is currently
- processing a block of data
- or a key preparation (for
- AES decryption). */
-#define CRYP_FLAG_IFEM 0x00000001U /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF 0x00000002U /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE 0x00000004U /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU 0x00000008U /*!< Output FIFO is Full */
-#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw
- interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw
- interrupt status */
-/**
- * @}
- */
+ DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-/**
- * @}
- */
+ DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
- * @{
- */
+ HAL_LockTypeDef Lock; /*!< CRYP locking object */
-/** @brief Reset CRYP handle state
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+ __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-/**
- * @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
+ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-/**
- * @brief Flush the data FIFO.
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
+ void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-/**
- * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param MODE The algorithm mode.
- * @retval None
- */
-#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
+ void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
-/** @brief Check whether the specified CRYP flag is set or not.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
- * @arg CRYP_FLAG_IFEM: Input FIFO is empty
- * @arg CRYP_FLAG_IFNF: Input FIFO is not full
- * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
- * @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24U)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
-
-/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ specifies the interrupt to check.
- * This parameter can be one of the following values:
- * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Enable the CRYP interrupt.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ CRYP Interrupt.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+}CRYP_HandleTypeDef;
-/**
- * @brief Disable the CRYP interrupt.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __INTERRUPT__ CRYP interrupt.
- * @retval None
- */
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
/**
* @}
*/
-/* Include CRYP HAL Extension module */
-#include "stm32f4xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
+ * @brief HAL CRYP Callback ID enumeration definition
* @{
*/
+typedef enum
+{
+ HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */
+ HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */
+ HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */
-/** @addtogroup CRYP_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
+ HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
+ HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-/** @addtogroup CRYP_Exported_Functions_Group2
- * @{
- */
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
+}HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group3
+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
+ * @brief HAL CRYP Callback pointer definition
* @{
*/
-/* DES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* DES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* DES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
- * @}
- */
-/** @addtogroup CRYP_Exported_Functions_Group4
- * @{
- */
-/* TDES encryption/decryption using polling **********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* TDES encryption/decryption using interrupt ********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* TDES encryption/decryption using DMA **************************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
- * @}
- */
+typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
-/** @addtogroup CRYP_Exported_Functions_Group5
- * @{
- */
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group6
- * @{
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/** @addtogroup CRYP_Exported_Functions_Group7
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Types CRYP Private Types
+/** @defgroup CRYP_Error_Definition CRYP Error Definition
* @{
*/
-
+#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
+#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
+#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
+#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
-/**
- * @}
- */
+#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
- * @{
- */
-#define CRYP_FLAG_MASK 0x0000001FU
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
+#if defined(CRYP)
-#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_192B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
-
-
-#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_1B))
-
-
- /**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-#endif /* CRYP */
-
-#if defined (AES)
-
-/** @addtogroup STM32F4xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRYP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
- * @{
- */
-
-/**
- * @brief CRYP Configuration Structure definition
- */
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
-
- uint32_t KeySize; /*!< 128 or 256-bit key length.
- This parameter can be a value of @ref CRYP_Key_Size */
-
- uint32_t OperatingMode; /*!< AES operating mode.
- This parameter can be a value of @ref CRYP_AES_OperatingMode */
-
- uint32_t ChainingMode; /*!< AES chaining mode.
- This parameter can be a value of @ref CRYP_AES_ChainingMode */
-
- uint32_t KeyWriteFlag; /*!< Allows to bypass or not key write-up before decryption.
- This parameter can be a value of @ref CRYP_Key_Write */
-
- uint32_t GCMCMACPhase; /*!< Indicates the processing phase of the Galois Counter Mode (GCM),
- Galois Message Authentication Code (GMAC) or Cipher Message
- Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when
- the latter is applicable.
- This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */
-
- uint8_t* pKey; /*!< Encryption/Decryption Key */
-
- uint8_t* pInitVect; /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC,
- (and CCM when applicable) modes */
-
- uint8_t* Header; /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */
-
- uint64_t HeaderSize; /*!< Header size in bytes */
-
-}CRYP_InitTypeDef;
-
-/**
- * @brief HAL CRYP State structures definition
- */
-typedef enum
-{
- HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
- HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
- HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04U, /*!< CRYP error state */
- HAL_CRYP_STATE_SUSPENDED = 0x05U /*!< CRYP suspended */
-}HAL_CRYP_STATETypeDef;
-
-/**
- * @brief HAL CRYP phase structures definition
- */
-typedef enum
-{
- HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
- HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
- HAL_CRYP_PHASE_START = 0x03U, /*!< CRYP peripheral has been initialized but
- GCM/GMAC/CMAC(/CCM) initialization phase has not started */
- HAL_CRYP_PHASE_INIT_OVER = 0x04U, /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out */
- HAL_CRYP_PHASE_HEADER_OVER = 0x05U, /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out */
- HAL_CRYP_PHASE_PAYLOAD_OVER = 0x06U, /*!< GCM(/CCM) payload phase has been carried out */
- HAL_CRYP_PHASE_FINAL_OVER = 0x07U, /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out */
- HAL_CRYP_PHASE_HEADER_SUSPENDED = 0x08U, /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended */
- HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09U, /*!< GCM(/CCM) payload phase has been suspended */
- HAL_CRYP_PHASE_NOT_USED = 0x0AU /*!< Phase is irrelevant to the current chaining mode */
-}HAL_PhaseTypeDef;
-
-/**
- * @brief HAL CRYP mode suspend definitions
- */
-typedef enum
-{
- HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP peripheral suspension not requested */
- HAL_CRYP_SUSPEND = 0x01U /*!< CRYP peripheral suspension requested */
-}HAL_SuspendTypeDef;
-
-
-/**
- * @brief HAL CRYP Error Codes definition
- */
-#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CRYP_WRITE_ERROR 0x00000001U /*!< Write error */
-#define HAL_CRYP_READ_ERROR 0x00000002U /*!< Read error */
-#define HAL_CRYP_DMA_ERROR 0x00000004U /*!< DMA error */
-#define HAL_CRYP_BUSY_ERROR 0x00000008U /*!< Busy flag error */
-
-/**
- * @brief CRYP handle Structure definition
- */
-typedef struct
-{
- AES_TypeDef *Instance; /*!< Register base address */
-
- CRYP_InitTypeDef Init; /*!< CRYP initialization parameters */
-
- uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */
-
- uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */
-
- uint32_t CrypInCount; /*!< Input data size in bytes or, after suspension, the remaining
- number of bytes to process */
-
- uint32_t CrypOutCount; /*!< Output data size in bytes */
-
- HAL_PhaseTypeDef Phase; /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC
- (or CCM when applicable) modes.
- Indicates the last phase carried out to ease
- phase transitions */
-
- DMA_HandleTypeDef *hdmain; /*!< CRYP peripheral Input DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaout; /*!< CRYP peripheral Output DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
- HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
-}CRYP_HandleTypeDef;
+#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
+#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
+#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
+#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
+#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
+#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
+#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
+#endif /* GCM CCM defined*/
+#else /* AES*/
+#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
+#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
+#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
+#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
+#endif /* End AES or CRYP */
/**
* @}
*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Key_Size Key size selection
+/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
-#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#if defined(CRYP)
+#define CRYP_KEYSIZE_128B 0x00000000U
+#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
+#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
+#else /* AES*/
+#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
+#endif /* End AES or CRYP */
/**
* @}
*/
-/** @defgroup CRYP_Data_Type AES Data Type selection
+/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
-#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
+#if defined(CRYP)
+#define CRYP_DATATYPE_32B 0x00000000U
+#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
+#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
+#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
+#else /* AES*/
+#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
-/**
- * @}
- */
-
- /** @defgroup CRYP_AES_State AES Enable state
- * @{
- */
-#define CRYP_AES_DISABLE 0x00000000U /*!< Disable AES */
-#define CRYP_AES_ENABLE AES_CR_EN /*!< Enable AES */
-/**
- * @}
- */
+#endif /* End AES or CRYP */
-/** @defgroup CRYP_AES_OperatingMode AES operating mode
- * @{
- */
-#define CRYP_ALGOMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
-#define CRYP_ALGOMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode */
-#define CRYP_ALGOMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
-#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption */
-#define CRYP_ALGOMODE_TAG_GENERATION 0x00000000U /*!< GMAC or CMAC authentication tag generation */
-/**
- * @}
- */
-
-/** @defgroup CRYP_AES_ChainingMode AES chaining mode
- * @{
- */
-#define CRYP_CHAINMODE_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
-#define CRYP_CHAINMODE_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
-#define CRYP_CHAINMODE_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
-#define CRYP_CHAINMODE_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
-#define CRYP_CHAINMODE_AES_CMAC AES_CR_CHMOD_2 /*!< Cipher message authentication code */
-#if defined(AES_CR_NPBLB)
-#define CRYP_CHAINMODE_AES_CCM_CMAC AES_CR_CHMOD_2 /*!< Counter with Cipher Mode - Cipher message authentication code */
-#endif
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Write AES decryption key write-up flag
- * @{
- */
-#define CRYP_KEY_WRITE_ENABLE 0x00000000U /*!< Enable decryption key writing */
-#define CRYP_KEY_WRITE_DISABLE 0x00000001U /*!< Disable decryption key writing */
-/**
- * @}
- */
-
-/** @defgroup CRYP_DMAIN DMA Input phase management enable state
- * @{
- */
-#define CRYP_DMAIN_DISABLE 0x00000000U /*!< Disable DMA Input phase management */
-#define CRYP_DMAIN_ENABLE AES_CR_DMAINEN /*!< Enable DMA Input phase management */
/**
* @}
*/
-/** @defgroup CRYP_DMAOUT DMA Output phase management enable state
+/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
-#define CRYP_DMAOUT_DISABLE 0x00000000U /*!< Disable DMA Output phase management */
-#define CRYP_DMAOUT_ENABLE AES_CR_DMAOUTEN /*!< Enable DMA Output phase management */
-/**
- * @}
- */
+#if defined (CRYP)
+#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
+#else /* AES*/
+#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
+#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
+#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
+#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
+#endif /* End AES or CRYP */
-
-/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection
- * @{
- */
-#define CRYP_GCM_INIT_PHASE 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
-#define CRYP_GCMCMAC_HEADER_PHASE AES_CR_GCMPH_0 /*!< GCM/GMAC or (CCM/)CMAC header phase */
-#define CRYP_GCM_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
-#define CRYP_GCMCMAC_FINAL_PHASE AES_CR_GCMPH /*!< GCM/GMAC or (CCM/)CMAC final phase */
-/* Definitions duplication for code readibility's sake:
- supported or not supported chain modes are not specified for each phase */
-#define CRYP_INIT_PHASE 0x00000000U /*!< Init phase */
-#define CRYP_HEADER_PHASE AES_CR_GCMPH_0 /*!< Header phase */
-#define CRYP_PAYLOAD_PHASE AES_CR_GCMPH_1 /*!< Payload phase */
-#define CRYP_FINAL_PHASE AES_CR_GCMPH /*!< Final phase */
/**
* @}
*/
-/** @defgroup CRYP_Flags AES status flags
+/** @defgroup CRYP_Flags CRYP Flags
* @{
*/
-
+#if defined (CRYP)
+/* Flags in the SR register */
+#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
+#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
+ or a key preparation (for AES decryption). */
+/* Flags in the RISR register */
+#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
+#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
+#else /* AES*/
+/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
-/**
- * @}
- */
-
-/** @defgroup CRYP_Clear_Flags AES clearing flags
- * @{
- */
-
+/* clearing flags */
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
-#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
-/**
- * @}
- */
+#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
+#endif /* End AES or CRYP */
-/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits
- * @{
- */
-#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
-#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
-/** @defgroup CRYP_Interrupts_Flags AES Interrupts flags
- * @{
- */
-#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
-#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
-#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
-/**
- * @}
- */
/**
* @}
@@ -818,334 +323,314 @@ typedef struct
* @{
*/
-/** @brief Reset CRYP handle state.
+/** @brief Reset CRYP handle state
* @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
- * @brief Enable the CRYP AES peripheral.
- * @retval None
- */
-#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN)
-
-/**
- * @brief Disable the CRYP AES peripheral.
- * @retval None
- */
-#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN)
-
-/**
- * @brief Set the algorithm operating mode.
- * @param __OPERATING_MODE__ specifies the operating mode
- * This parameter can be one of the following values:
- * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
- * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
- * @arg @ref CRYP_ALGOMODE_DECRYPT decryption
- * @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption
- * @retval None
- */
-#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))
-
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
- * @brief Set the algorithm chaining mode.
- * @param __CHAINING_MODE__ specifies the chaining mode
- * This parameter can be one of the following values:
- * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
- * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
- * @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode
- * @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code
- * @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)
+ * @brief Enable/Disable the CRYP peripheral.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))
-
-
+#if defined(CRYP)
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
+#else /* AES*/
+#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
+#endif /* End AES or CRYP */
/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * This parameter can be one of the following values for CRYP:
+ * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+ * or a key preparation (for AES decryption).
+ * @arg CRYP_FLAG_IFEM: Input FIFO is empty
+ * @arg CRYP_FLAG_IFNF: Input FIFO is not full
+ * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+ * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+ * @arg CRYP_FLAG_OFFU: Output FIFO is full
+ * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))
-
+#define CRYP_FLAG_MASK 0x0000001FU
+#if defined(CRYP)
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+#else /* AES*/
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#endif /* End AES or CRYP */
/** @brief Clear the CRYP pending status flag.
- * @param __FLAG__ specifies the flag to clear.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))
+#if defined(AES)
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
- * @param __INTERRUPT__ CRYP interrupt source to check
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP interrupt source to check
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval State of interruption (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#endif /* AES */
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __INTERRUPT__ specifies the interrupt to check.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: specifies the interrupt to check.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
+ * This parameter can be one of the following values for CRYP:
+ * @arg CRYP_IT_INI: Input FIFO service masked interrupt status
+ * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-
-
-/** @brief Clear the CRYP pending interrupt.
- * @param __INTERRUPT__ specifies the IT to clear.
- * This parameter can be one of the following values:
- * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
- * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
- * @retval None
- */
-#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))
-
+#if defined(CRYP)
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @brief Enable the CRYP interrupt.
- * @param __INTERRUPT__ CRYP Interrupt.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * This parameter can be one of the following values for CRYP:
+ * @ CRYP_IT_INI : Input FIFO service interrupt mask.
+ * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))
-
+#if defined(CRYP)
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @brief Disable the CRYP interrupt.
- * @param __INTERRUPT__ CRYP Interrupt.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: CRYP Interrupt.
+ * This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+ * This parameter can be one of the following values for CRYP:
+ * @ CRYP_IT_INI : Input FIFO service interrupt mask.
+ * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+ * @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))
+#if defined(CRYP)
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
+#else /* AES*/
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+#endif /* End AES or CRYP */
/**
* @}
*/
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup CRYP_Private_Macros CRYP Private Macros
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
+/* Include CRYP HAL Extended module */
+#include "stm32f4xx_hal_cryp_ex.h"
+#endif /* AES or GCM CCM defined*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
+/** @addtogroup CRYP_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
- * @brief Verify the key size length.
- * @param __KEYSIZE__ Ciphering/deciphering algorithm key size.
- * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
+ * @}
*/
-#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
- ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
-/**
- * @brief Verify the input data type.
- * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.
- * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+/** @addtogroup CRYP_Exported_Functions_Group2
+ * @{
*/
-#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_8B) || \
- ((__DATATYPE__) == CRYP_DATATYPE_1B))
+
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
/**
- * @brief Verify the CRYP AES IP running mode.
- * @param __MODE__ CRYP AES IP running mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ * @}
*/
-#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
- ((__MODE__) == CRYP_AES_ENABLE))
-/**
- * @brief Verify the selected CRYP algorithm.
- * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
- * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+ * @{
*/
-#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \
- ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))
+/* Interrupt Handler functions **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
- * @brief Verify the selected CRYP chaining algorithm.
- * @param __CHAINMODE__ Selected CRYP chaining algorithm.
- * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
+ * @}
*/
-#if defined(AES_CR_NPBLB)
-#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
-#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \
- ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))
-#endif
/**
- * @brief Verify the deciphering key write option.
- * @param __WRITE__ deciphering key write option.
- * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
+ * @}
*/
-#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
- ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))
-/**
- * @brief Verify the CRYP input data DMA mode.
- * @param __MODE__ CRYP input data DMA mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+ * @{
*/
-#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
- ((__MODE__) == CRYP_DMAIN_ENABLE))
-/**
- * @brief Verify the CRYP output data DMA mode.
- * @param __MODE__ CRYP output data DMA mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
+ * @{
*/
-#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
- ((__MODE__) == CRYP_DMAOUT_ENABLE))
+#if defined(CRYP)
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM) || \
+ ((ALGORITHM) == CRYP_AES_CCM))
+#else /*NO GCM CCM */
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
+ ((ALGORITHM) == CRYP_DES_CBC) || \
+ ((ALGORITHM) == CRYP_TDES_ECB) || \
+ ((ALGORITHM) == CRYP_TDES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR))
+#endif /* GCM CCM defined*/
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+#else /* AES*/
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
+ ((ALGORITHM) == CRYP_AES_CBC) || \
+ ((ALGORITHM) == CRYP_AES_CTR) || \
+ ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
+ ((ALGORITHM) == CRYP_AES_CCM))
+
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
+ ((KEYSIZE) == CRYP_KEYSIZE_256B))
+#endif /* End AES or CRYP */
+
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
+ ((DATATYPE) == CRYP_DATATYPE_16B) || \
+ ((DATATYPE) == CRYP_DATATYPE_8B) || \
+ ((DATATYPE) == CRYP_DATATYPE_1B))
/**
- * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
+ * @}
*/
-#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
- ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \
- ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE) || \
- ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))
/**
* @}
*/
-/* Include CRYP HAL Extended module */
-#include "stm32f4xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
-/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
* @{
*/
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-
-/* MSP initialization/de-initialization functions ****************************/
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
-
-/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
*/
-/* AES encryption/decryption processing functions ****************************/
-
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
*/
-/* CallBack functions ********************************************************/
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
-/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
*/
-/* AES interrupt handling function *******************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
-/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
* @{
*/
-/* Peripheral State functions ************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
+
/**
* @}
*/
-#endif /* AES */
-
/**
* @}
*/
+#endif /* TinyAES or CRYP*/
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp_ex.h
index 5d55e19f0b103f2597ea48e78af15bc57dac947e..8f9fc9ddaea48fc9ed522b4b05fd5dcfa6727e95 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_cryp_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -44,9 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-
-#if defined(CRYP)
-
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -54,111 +35,24 @@
/** @addtogroup CRYPEx
* @{
*/
-
/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants
- * @{
- */
-
-/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
- * @{
- */
-#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT 0x00080000U
-#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT 0x00080004U
-#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT 0x00080008U
-#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT 0x0008000CU
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
- * @brief The phases are relevant only to AES-GCM and AES-CCM
+/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
* @{
*/
-#define CRYP_PHASE_INIT 0x00000000U
-#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
-#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
-#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
-/**
- * @}
- */
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
- * @{
- */
-
-/**
- * @brief Set the phase: Init, header, payload, final.
- * This is relevant only for GCM and CCM modes.
- * @param __HANDLE__ specifies the CRYP handle.
- * @param __PHASE__ The phase.
- * @retval None
- */
-#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
- * @{
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
- * @{
- */
-
-/* AES encryption/decryption using polling ***********************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt *********************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA ***************************************/
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group2
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
* @{
*/
-void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
/**
* @}
*/
- /**
- * @}
- */
-
-
- /* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
*/
@@ -203,79 +97,36 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
* @}
*/
-#endif /* CRYP */
-
-#if defined (AES)
-
-/** @addtogroup CRYPEx_Exported_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
*/
-
+#if defined (CRYP) || defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
*/
-
-/* CallBack functions ********************************************************/
-void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
-
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
* @}
*/
+#endif /* CRYP||AES */
+#if defined (AES)
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
*/
-
-/* AES encryption/decryption processing functions ****************************/
-HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
-HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
-
-/* AES encryption/decryption/authentication processing functions *************/
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group3
- * @{
- */
-
-/* AES suspension/resumption functions ***************************************/
-void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
-void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
-void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
-void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
-void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
-
+void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
-
-
-/**
- * @}
- */
-
-/* Private functions -----------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
- * @{
- */
-HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
+#endif /* AES */
/**
* @}
*/
-#endif /* AES */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac.h
index b12a6ef7feb9aaccd2dc0d8b004bda5f27ab8ffc..d13fe2e8ef55515909bb61f01c5a8dc60e432981 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -77,7 +61,11 @@ typedef enum
/**
* @brief DAC handle Structure definition
*/
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
typedef struct
+#endif
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -91,6 +79,20 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+
+ void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
}DAC_HandleTypeDef;
/**
@@ -104,6 +106,31 @@ typedef struct
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DAC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
+ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
+ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
+ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
+ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
+ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
+ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+ HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
+}HAL_DAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DAC Callback pointer definition
+ */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -120,6 +147,9 @@ typedef struct
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -202,7 +232,15 @@ typedef struct
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel
* @param __HANDLE__ specifies the DAC handle.
@@ -320,6 +358,12 @@ void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac_ex.h
index 1667a5d6be12ae44d79bb860b76dccb9e70237b4..7a827077505161096c0317dcbb3e73302da2b0ea 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dac_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi.h
index 4d867dba04d139e8e68b0081b9114d156d8ae357..28cc7e4d882ffc904df05add79062034e7ba3596 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -80,7 +64,7 @@ typedef enum
/**
* @brief DCMI handle Structure definition
*/
-typedef struct
+typedef struct __DCMI_HandleTypeDef
{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
@@ -101,8 +85,32 @@ typedef struct
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
__IO uint32_t ErrorCode; /*!< DCMI Error code */
-
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
+ void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
+ void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
+ void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
+ void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
+ void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}DCMI_HandleTypeDef;
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+typedef enum
+{
+ HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
+ HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
+ HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
+ HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
+ HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
+ HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
+
+}HAL_DCMI_CallbackIDTypeDef;
+
+typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
@@ -120,6 +128,9 @@ typedef struct
#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -293,7 +304,11 @@ typedef struct
* @param __HANDLE__ specifies the DCMI handle.
* @retval None
*/
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
/**
* @brief Enable the DCMI.
@@ -407,6 +422,12 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi_ex.h
index 11d166343822036c24e6ced010c6f5b816907cf0..c241c7b59035fb52eb1f252dd25584cfd9ea47cd 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dcmi_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_def.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_def.h
index ba24bdbd7fecd71b9d3cb235f978c82203d2e1e4..6d6e85d938325dcd70a209dbdba81e4b3f18a4bc 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_def.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_def.h
@@ -7,29 +7,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -45,7 +29,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
#include "Legacy/stm32_hal_legacy.h"
-#include
+#include
/* Exported types ------------------------------------------------------------*/
@@ -75,8 +59,8 @@ typedef enum
#define HAL_MAX_DELAY 0xFFFFFFFFU
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dfsdm.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dfsdm.h
index 9ec5a3343222a2333750bbb9e5ac1f895404ed6d..f1e857fa165a365c441b3b963715249d247f45f3 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dfsdm.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dfsdm.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -133,13 +117,40 @@ typedef struct
/**
* @brief DFSDM channel handle structure definition
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Channel_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
+ void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
+ void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
+ void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
+#endif
}DFSDM_Channel_HandleTypeDef;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief DFSDM channel callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
+ HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
+ HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */
+ HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */
+}HAL_DFSDM_Channel_CallbackIDTypeDef;
+
+/**
+ * @brief DFSDM channel callback pointer definition
+ */
+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+#endif
/**
* @brief HAL DFSDM Filter states definition
*/
@@ -205,7 +216,11 @@ typedef struct
/**
* @brief DFSDM filter handle structure definition
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Filter_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
@@ -220,6 +235,17 @@ typedef struct
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
+ void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
+ void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
+ void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
+ void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */
+ void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */
+ void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */
+ void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */
+#endif
}DFSDM_Filter_HandleTypeDef;
/**
@@ -241,6 +267,28 @@ typedef struct
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief DFSDM filter callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
+ HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
+ HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
+ HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
+ HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */
+ HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */
+ HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */
+}HAL_DFSDM_Filter_CallbackIDTypeDef;
+
+/**
+ * @brief DFSDM filter callback pointer definition
+ */
+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+#endif
+
/**
* @}
*/
@@ -435,6 +483,9 @@ typedef struct
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
+#endif
/**
* @}
*/
@@ -693,13 +744,29 @@ typedef struct
* @param __HANDLE__ DFSDM channel handle.
* @retval None
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+#endif
/** @brief Reset DFSDM filter handle state.
* @param __HANDLE__ DFSDM filter handle.
* @retval None
*/
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+#endif
/**
* @}
@@ -719,6 +786,14 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Channel callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
+ pDFSDM_Channel_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
+#endif
/**
* @}
*/
@@ -766,6 +841,17 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Filter callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
+ pDFSDM_Filter_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ pDFSDM_Filter_AwdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma.h
index 4e26cb46344397c412fb5f1246733e0591b76faf..9423ab5df6a980481449b4ac9ff216fa5c1e46fd 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma2d.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma2d.h
index 623d8517f944c8fc130a18a064bae340ab82b7b1..5bb7b6dfbae7fdbbef7f3988a7e97f43ddc7e54a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma2d.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma2d.h
@@ -6,43 +6,27 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DMA2D_H
-#define __STM32F4xx_HAL_DMA2D_H
+#ifndef STM32F4xx_HAL_DMA2D_H
+#define STM32F4xx_HAL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DMA2D)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -59,35 +43,20 @@
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{
*/
-#define MAX_DMA2D_LAYER 2U
-
-/**
- * @brief DMA2D color Structure definition
- */
-typedef struct
-{
- uint32_t Blue; /*!< Configures the blue value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Green; /*!< Configures the green value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Red; /*!< Configures the red value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-} DMA2D_ColorTypeDef;
+#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @brief DMA2D CLUT Structure definition
*/
typedef struct
{
- uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
- uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
- This parameter can be one value of @ref DMA2D_CLUT_CM. */
+ uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
+ This parameter can be one value of @ref DMA2D_CLUT_CM. */
- uint32_t Size; /*!< Configures the DMA2D CLUT size.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
+ uint32_t Size; /*!< Configures the DMA2D CLUT size.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
@@ -104,30 +73,35 @@ typedef struct
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+
+
+
} DMA2D_InitTypeDef;
+
/**
* @brief DMA2D Layer structure definition
*/
typedef struct
{
- uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
+ uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
- uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
- This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
+ uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
+ This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
- uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
- This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+ uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
+ This parameter can be one value of @ref DMA2D_Alpha_Mode. */
+
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
+ @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
+ Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
+ - InputAlpha[24:31] is the alpha value ALPHA[0:7]
+ - InputAlpha[16:23] is the red value RED[0:7]
+ - InputAlpha[8:15] is the green value GREEN[0:7]
+ - InputAlpha[0:7] is the blue value BLUE[0:7]. */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
- @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
- Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- - InputAlpha[24:31] is the alpha value ALPHA[0:7]
- - InputAlpha[16:23] is the red value RED[0:7]
- - InputAlpha[8:15] is the green value GREEN[0:7]
- - InputAlpha[0:7] is the blue value BLUE[0:7]. */
} DMA2D_LayerCfgTypeDef;
@@ -157,7 +131,18 @@ typedef struct __DMA2D_HandleTypeDef
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
- DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
+
+ void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
+
+ void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
+
+ void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
+
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
+
+ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
@@ -165,6 +150,13 @@ typedef struct __DMA2D_HandleTypeDef
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D Callback pointer definition
+ */
+typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -177,11 +169,15 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
-#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
-#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
-#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
-#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
+#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
+#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -189,10 +185,10 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
-#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
-#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
-#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
+#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
@@ -212,17 +208,17 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
-#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
-#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
-#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
-#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
-#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
-#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
-#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
-#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
-#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
-#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
-#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
+#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
+#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
+#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
+#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
+#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
+#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
+#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
+#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
+#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
+#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
+#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
/**
* @}
*/
@@ -230,19 +226,24 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
-#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
-#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
-#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
- with original alpha channel value */
+#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
+#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
+#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
+ with original alpha channel value */
/**
* @}
*/
+
+
+
+
+
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
-#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
-#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
+#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
+#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
@@ -250,12 +251,12 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
-#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
+#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
-#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
-#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
-#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
-#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
+#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
+#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
+#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
+#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
@@ -263,12 +264,12 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Flags DMA2D Flags
* @{
*/
-#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
+#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
-#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
-#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
-#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
+#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
@@ -281,6 +282,22 @@ typedef struct __DMA2D_HandleTypeDef
* @}
*/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DMA2D common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
+ HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
+ HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
+ HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
+ HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
+ HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
+}HAL_DMA2D_CallbackIDTypeDef;
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
@@ -293,14 +310,24 @@ typedef struct __DMA2D_HandleTypeDef
* @param __HANDLE__ specifies the DMA2D handle.
* @retval None
*/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
/**
* @brief Enable the DMA2D.
* @param __HANDLE__ DMA2D handle
* @retval None.
*/
-#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
+
/* Interrupt & Flag management */
/**
@@ -396,11 +423,17 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
+
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
* @{
*/
@@ -469,7 +502,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
* @{
*/
-#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
+#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
/**
* @}
*/
@@ -477,7 +510,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
-#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
+#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
/**
* @}
*/
@@ -485,7 +518,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{
*/
-#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
+#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
+/**
+ * @}
+ */
+
+/** @defgroup DMA2D_Layers DMA2D Layers
+ * @{
+ */
+#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
+#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
/**
* @}
*/
@@ -493,7 +535,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
-#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
+#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
/**
* @}
*/
@@ -501,8 +543,8 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
-#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
-#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
+#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
+#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
/**
* @}
*/
@@ -510,7 +552,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
-#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */
+#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
/**
* @}
*/
@@ -519,30 +561,40 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
+#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
+
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
+
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
+
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
+
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
+
+
+
+
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
@@ -564,12 +616,13 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#endif /* defined (DMA2D) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_DMA2D_H */
+#endif /* STM32F4xx_HAL_DMA2D_H */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma_ex.h
index fb2cd044c8ff7107add9c03d869caca5391c4368..7691536f47170024b5745decad8e86fe42f17439 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dma_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dsi.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dsi.h
index 9b6b78ded294d4134606ceae190ca43ab1326002..df61c5e30db6aeeeb4a9c02cd258d933e98bde4f 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dsi.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_dsi.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DSI_H
-#define __STM32F4xx_HAL_DSI_H
+#ifndef STM32F4xx_HAL_DSI_H
+#define STM32F4xx_HAL_DSI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if defined(DSI)
@@ -69,7 +53,7 @@ typedef struct
uint32_t NumberOfLanes; /*!< Number of lanes
This parameter can be any value of @ref DSI_Number_Of_Lanes */
-}DSI_InitTypeDef;
+} DSI_InitTypeDef;
/**
* @brief DSI PLL Clock structure definition
@@ -85,7 +69,7 @@ typedef struct
uint32_t PLLODF; /*!< PLL Output Division Factor
This parameter can be any value of @ref DSI_PLL_ODF */
-}DSI_PLLInitTypeDef;
+} DSI_PLLInitTypeDef;
/**
* @brief DSI Video mode configuration
@@ -163,7 +147,7 @@ typedef struct
uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
This parameter can be any value of @ref DSI_FBTA_acknowledge */
-}DSI_VidCfgTypeDef;
+} DSI_VidCfgTypeDef;
/**
* @brief DSI Adapted command mode configuration
@@ -202,7 +186,7 @@ typedef struct
uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
-}DSI_CmdCfgTypeDef;
+} DSI_CmdCfgTypeDef;
/**
* @brief DSI command transmission mode configuration
@@ -248,7 +232,7 @@ typedef struct
uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
This parameter can be any value of @ref DSI_AcknowledgeRequest */
-}DSI_LPCmdTypeDef;
+} DSI_LPCmdTypeDef;
/**
* @brief DSI PHY Timings definition
@@ -272,7 +256,7 @@ typedef struct
uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
Stop state */
-}DSI_PHY_TimerTypeDef;
+} DSI_PHY_TimerTypeDef;
/**
* @brief DSI HOST Timeouts definition
@@ -298,7 +282,7 @@ typedef struct
uint32_t BTATimeout; /*!< BTA time-out */
-}DSI_HOST_TimeoutTypeDef;
+} DSI_HOST_TimeoutTypeDef;
/**
* @brief DSI States Structure definition
@@ -310,12 +294,16 @@ typedef enum
HAL_DSI_STATE_ERROR = 0x02U,
HAL_DSI_STATE_BUSY = 0x03U,
HAL_DSI_STATE_TIMEOUT = 0x04U
-}HAL_DSI_StateTypeDef;
+} HAL_DSI_StateTypeDef;
/**
* @brief DSI Handle Structure definition
*/
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+typedef struct __DSI_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
{
DSI_TypeDef *Instance; /*!< Register base address */
DSI_InitTypeDef Init; /*!< DSI required parameters */
@@ -323,7 +311,40 @@ typedef struct
__IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
__IO uint32_t ErrorCode; /*!< DSI Error code */
uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
-}DSI_HandleTypeDef;
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */
+ void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */
+ void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */
+
+ void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */
+ void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
+} DSI_HandleTypeDef;
+
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DSI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */
+ HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */
+
+ HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */
+ HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */
+ HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */
+
+} HAL_DSI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DSI Callback pointer definition
+ */
+typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
+
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_DCS_Command DSI DCS Command
@@ -815,17 +836,20 @@ typedef struct
/** @defgroup DSI_Error_Data_Type DSI Error Data Type
* @{
*/
-#define HAL_DSI_ERROR_NONE 0U
-#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
-#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
-#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
-#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
-#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
-#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
-#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
-#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
-#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
-#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_NONE 0U
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -885,6 +909,21 @@ typedef struct
*/
/* Exported macros -----------------------------------------------------------*/
+/**
+ * @brief Reset DSI handle state.
+ * @param __HANDLE__: DSI handle
+ * @retval None
+ */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
+#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
+
/**
* @brief Enables the DSI host.
* @param __HANDLE__ DSI handle
@@ -896,7 +935,7 @@ typedef struct
/* Delay after an DSI Host enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Disables the DSI host.
@@ -909,7 +948,7 @@ typedef struct
/* Delay after an DSI Host disabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Enables the DSI wrapper.
@@ -922,7 +961,7 @@ typedef struct
/* Delay after an DSI warpper enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Disable the DSI wrapper.
@@ -935,7 +974,7 @@ typedef struct
/* Delay after an DSI warpper disabling*/ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Enables the DSI PLL.
@@ -948,7 +987,7 @@ typedef struct
/* Delay after an DSI PLL enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Disables the DSI PLL.
@@ -961,7 +1000,7 @@ typedef struct
/* Delay after an DSI PLL disabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Enables the DSI regulator.
@@ -974,7 +1013,7 @@ typedef struct
/* Delay after an DSI regulator enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Disables the DSI regulator.
@@ -987,7 +1026,7 @@ typedef struct
/* Delay after an DSI regulator disabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
UNUSED(tmpreg); \
- }while(0U)
+ } while(0U)
/**
* @brief Get the DSI pending flags.
@@ -1076,6 +1115,13 @@ void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+ pDSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1098,14 +1144,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t* ParametersTable);
+ uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
- uint8_t* Array,
+ uint8_t *Array,
uint32_t Size,
uint32_t Mode,
uint32_t DCSCmd,
- uint8_t* ParametersTable);
+ uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
@@ -1114,11 +1160,14 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+ uint32_t Value);
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
-HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
-HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+ FunctionalState State);
+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
+ uint32_t Value);
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
@@ -1283,6 +1332,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
}
#endif
-#endif /* __STM32F4xx_HAL_DSI_H */
+#endif /* STM32F4xx_HAL_DSI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_eth.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_eth.h
index 5dc952752f41ca30132439b57399a3a73cdb0d01..057d70216e88d45766c8a883bb08597336f04c77 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_eth.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_eth.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -624,7 +608,11 @@ typedef struct
* @brief ETH Handle Structure definition
*/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
{
ETH_TypeDef *Instance; /*!< Register base address */
@@ -642,8 +630,39 @@ typedef struct
HAL_LockTypeDef Lock; /*!< ETH Lock */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
+ void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */
+ void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
} ETH_HandleTypeDef;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ETH Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
+ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
+ HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
+ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
+ HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
+
+}HAL_ETH_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ETH Callback pointer definition
+ */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1590,7 +1609,15 @@ typedef struct
* @param __HANDLE__ specifies the ETH handle.
* @retval None
*/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
@@ -2107,6 +2134,11 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_exti.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_exti.h
new file mode 100644
index 0000000000000000000000000000000000000000..0862c0e275647b1fe274a7859ceb3a8c6d238949
--- /dev/null
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_exti.h
@@ -0,0 +1,264 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32f4xx_HAL_EXTI_H
+#define STM32f4xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+typedef enum
+{
+ HAL_EXTI_COMMON_CB_ID = 0x00U,
+ HAL_EXTI_RISING_CB_ID = 0x01U,
+ HAL_EXTI_FALLING_CB_ID = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< Exti line number */
+ void (* RisingCallback)(void); /*!< Exti rising callback */
+ void (* FallingCallback)(void); /*!< Exti falling callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */
+#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */
+#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */
+#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */
+#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */
+#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */
+#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */
+#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */
+#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */
+#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */
+#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */
+#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */
+#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */
+#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */
+#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */
+#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */
+#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_INTERRUPT 0x00000000U
+#define EXTI_MODE_EVENT 0x00000004U
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+
+#define EXTI_TRIGGER_RISING 0x00000008U
+#define EXTI_TRIGGER_FALLING 0x0000000CU
+#define EXTI_TRIGGER_RISING_FALLING 0x00000010U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 23UL
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__LINE__) (((__LINE__) == EXTI_LINE_0) || \
+ ((__LINE__) == EXTI_LINE_1) || \
+ ((__LINE__) == EXTI_LINE_2) || \
+ ((__LINE__) == EXTI_LINE_3) || \
+ ((__LINE__) == EXTI_LINE_4) || \
+ ((__LINE__) == EXTI_LINE_5) || \
+ ((__LINE__) == EXTI_LINE_6) || \
+ ((__LINE__) == EXTI_LINE_7) || \
+ ((__LINE__) == EXTI_LINE_8) || \
+ ((__LINE__) == EXTI_LINE_9) || \
+ ((__LINE__) == EXTI_LINE_10) || \
+ ((__LINE__) == EXTI_LINE_11) || \
+ ((__LINE__) == EXTI_LINE_12) || \
+ ((__LINE__) == EXTI_LINE_13) || \
+ ((__LINE__) == EXTI_LINE_14) || \
+ ((__LINE__) == EXTI_LINE_15) || \
+ ((__LINE__) == EXTI_LINE_16) || \
+ ((__LINE__) == EXTI_LINE_17) || \
+ ((__LINE__) == EXTI_LINE_18) || \
+ ((__LINE__) == EXTI_LINE_19) || \
+ ((__LINE__) == EXTI_LINE_20) || \
+ ((__LINE__) == EXTI_LINE_21) || \
+ ((__LINE__) == EXTI_LINE_22))
+
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \
+ ((__LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32f4xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash.h
index 29c6f7ed28b7da8986b5a47eab2d328d7e374156..d40fb9880d573b5471372078493c229d30becaf1 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ex.h
index c830210d5033ae0af69d9eb8737c1f29417c49ab..4df2675746d9a39f884f805f4e2c980e2d398d1a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ramfunc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ramfunc.h
index bd4ebb95ab5e5ed8b67f7916355d670102753b80..ecb522c70776577ec4e54d1b3fb26bc06c56af04 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ramfunc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_flash_ramfunc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c.h
index 9390d5bd687ec95f8e6ee5539a2c0b171ddfdf9c..f0fd230e80be51fbad4e5be8c9e9bc58d6e6dcd5 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c.h
@@ -6,44 +6,26 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FMPI2C_H
-#define __STM32F4xx_HAL_FMPI2C_H
+#ifndef STM32F4xx_HAL_FMPI2C_H
+#define STM32F4xx_HAL_FMPI2C_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
+#if defined(FMPI2C_CR1_PE)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -105,17 +87,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
- * b5 IP initilisation status\n
- * 0 : Reset (IP not initialized)\n
- * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)\n
+ * b5 Peripheral initialization status\n
+ * 0 : Reset (peripheral not initialized)\n
+ * 1 : Init done (peripheral initialized and ready to use. HAL FMPI2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
- * 1 : Listen (IP in Address Listen Mode)\n
+ * 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
- * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
@@ -189,6 +171,11 @@ typedef enum
#define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+#define HAL_FMPI2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+#define HAL_FMPI2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
+#define HAL_FMPI2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
@@ -229,7 +216,54 @@ typedef struct __FMPI2C_HandleTypeDef
__IO uint32_t ErrorCode; /*!< FMPI2C Error code */
__IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
+
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Error callback */
+ void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Abort callback */
+
+ void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPI2C Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp DeInit callback */
+
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
} FMPI2C_HandleTypeDef;
+
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL FMPI2C Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPI2C Master Tx Transfer completed callback ID */
+ HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPI2C Master Rx Transfer completed callback ID */
+ HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPI2C Slave Tx Transfer completed callback ID */
+ HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPI2C Slave Rx Transfer completed callback ID */
+ HAL_FMPI2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPI2C Listen Complete callback ID */
+ HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< FMPI2C Memory Tx Transfer callback ID */
+ HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< FMPI2C Memory Rx Transfer completed callback ID */
+ HAL_FMPI2C_ERROR_CB_ID = 0x07U, /*!< FMPI2C Error callback ID */
+ HAL_FMPI2C_ABORT_CB_ID = 0x08U, /*!< FMPI2C Abort callback ID */
+
+ HAL_FMPI2C_MSPINIT_CB_ID = 0x09U, /*!< FMPI2C Msp Init callback ID */
+ HAL_FMPI2C_MSPDEINIT_CB_ID = 0x0AU /*!< FMPI2C Msp DeInit callback ID */
+
+} HAL_FMPI2C_CallbackIDTypeDef;
+
+/**
+ * @brief HAL FMPI2C Callback pointer definition
+ */
+typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */
+typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */
+
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -252,6 +286,12 @@ typedef struct __FMPI2C_HandleTypeDef
#define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define FMPI2C_OTHER_FRAME (0x000000AAU)
+#define FMPI2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
@@ -277,14 +317,14 @@ typedef struct __FMPI2C_HandleTypeDef
/** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
* @{
*/
-#define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
-#define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
-#define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
-#define FMPI2C_OA2_MASK03 ((uint8_t)0x03)
-#define FMPI2C_OA2_MASK04 ((uint8_t)0x04)
-#define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
-#define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
-#define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
+#define FMPI2C_OA2_NOMASK ((uint8_t)0x00U)
+#define FMPI2C_OA2_MASK01 ((uint8_t)0x01U)
+#define FMPI2C_OA2_MASK02 ((uint8_t)0x02U)
+#define FMPI2C_OA2_MASK03 ((uint8_t)0x03U)
+#define FMPI2C_OA2_MASK04 ((uint8_t)0x04U)
+#define FMPI2C_OA2_MASK05 ((uint8_t)0x05U)
+#define FMPI2C_OA2_MASK06 ((uint8_t)0x06U)
+#define FMPI2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
@@ -400,7 +440,15 @@ typedef struct __FMPI2C_HandleTypeDef
* @param __HANDLE__ specifies the FMPI2C Handle.
* @retval None
*/
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
+#endif
/** @brief Enable the specified FMPI2C interrupt.
* @param __HANDLE__ specifies the FMPI2C Handle.
@@ -473,6 +521,7 @@ typedef struct __FMPI2C_HandleTypeDef
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
+#define FMPI2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
@@ -532,6 +581,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -557,10 +615,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
@@ -572,6 +630,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/**
* @}
*/
@@ -660,28 +723,35 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
((REQUEST) == FMPI2C_NO_STARTSTOP))
#define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \
- ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
- ((REQUEST) == FMPI2C_NEXT_FRAME) || \
- ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == FMPI2C_LAST_FRAME) || \
- ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP))
+ ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
+ ((REQUEST) == FMPI2C_NEXT_FRAME) || \
+ ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == FMPI2C_LAST_FRAME) || \
+ ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \
+ IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \
+ ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME))
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
-#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16)
-#define FMPI2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16)
+#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U))
+#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U))
#define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
-#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
-#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
+#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1))
+#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2))
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
-#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8U)))
-#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
+
+#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET)
+#define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
@@ -702,12 +772,13 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
/**
* @}
*/
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* FMPI2C_CR1_PE */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_FMPI2C_H */
+#endif /* STM32F4xx_HAL_FMPI2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c_ex.h
index 52e2e765f2a3428408b3d2793c926406ea5b7fd7..2be2c288e2ce1c8352179d4388d227b02831ba89 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_fmpi2c_ex.h
@@ -6,44 +6,26 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FMPI2C_EX_H
-#define __STM32F4xx_HAL_FMPI2C_EX_H
+#ifndef STM32F4xx_HAL_FMPI2C_EX_H
+#define STM32F4xx_HAL_FMPI2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
+#if defined(FMPI2C_CR1_PE)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -116,12 +98,17 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @{
*/
#define IS_FMPI2C_ANALOG_FILTER(FILTER) (((FILTER) == FMPI2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == FMPI2C_ANALOGFILTER_DISABLE))
#define IS_FMPI2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_FMPI2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SCL)) == FMPI2C_FASTMODEPLUS_SCL) || \
(((__CONFIG__) & (FMPI2C_FASTMODEPLUS_SDA)) == FMPI2C_FASTMODEPLUS_SDA))
+
+
+
+
+
/**
* @}
*/
@@ -130,7 +117,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions
* @{
*/
-/* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */
+/* Private functions are defined in stm32f4xx_hal_fmpfmpi2c_ex.c file */
/**
* @}
*/
@@ -150,11 +137,12 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* FMPI2C_CR1_PE */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
+#endif /* STM32F4xx_HAL_FMPI2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio.h
index ed002f004c149fb4cd82e12fbb5066198f348c13..11c29dc23b16cdc9d58251025c3d1311999430aa 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio_ex.h
index 5aa0ddf671834565318079b7fdf07a2ef50b1e0a..b109c8d979f46a9273977b3f7aa27979d58c4a37 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_gpio_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -542,8 +526,9 @@
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
-#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
+#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
/**
* @brief AF 6 selection
@@ -566,7 +551,6 @@
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
@@ -1319,7 +1303,7 @@
((__GPIOx__) == (GPIOE))? 4U : 7U)
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F446xx) || defined(STM32F412Zx) ||defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
@@ -1327,7 +1311,25 @@
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :\
((__GPIOx__) == (GPIOG))? 6U : 7U)
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F412Vx */
+#if defined(STM32F412Rx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U : 7U)
+#endif /* STM32F412Rx */
+#if defined(STM32F412Cx)
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F412Cx */
/**
* @}
@@ -1441,7 +1443,7 @@
/*---------------------------------------- STM32F401xx------------------------*/
#if defined(STM32F401xC) || defined(STM32F401xE)
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
@@ -1453,7 +1455,7 @@
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT))
+ ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F401xC || STM32F401xE */
/*----------------------------------------------------------------------------*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash.h
index 47b44c7cbe00aa3bae5922e331e1b99959d2a75c..da6d5d92b4a27fee819262df93dfa67b7dd5ebc8 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash.h
@@ -6,53 +6,34 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_HASH_H
-#define __STM32F4xx_HAL_HASH_H
+#ifndef STM32F4xx_HAL_HASH_H
+#define STM32F4xx_HAL_HASH_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
+#if defined (HASH)
/** @addtogroup HASH
- * @brief HASH HAL module driver
- * @{
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
@@ -60,156 +41,227 @@
* @{
*/
-/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
- * @{
+/**
+ * @brief HASH Configuration Structure definition
*/
-
typedef struct
{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref HASH_Data_Type */
+ uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+ This parameter can be a value of @ref HASH_Data_Type. */
- uint32_t KeySize; /*!< The key size is used only in HMAC operation */
+ uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
- uint8_t* pKey; /*!< The key is used only in HMAC operation */
-}HASH_InitTypeDef;
+ uint8_t* pKey; /*!< The key is used only in HMAC operation. */
-/**
- * @}
- */
+} HASH_InitTypeDef;
-/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
- * @{
+/**
+ * @brief HAL State structures definition
*/
-
typedef enum
{
- HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
- HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
- HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
- HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
+ HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
+ HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
+ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
+ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
}HAL_HASH_StateTypeDef;
/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
- * @{
+ * @brief HAL phase structures definition
*/
-
typedef enum
{
- HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
- HAL_HASH_PHASE_PROCESS = 0x02U /*!< HASH peripheral is in processing phase */
+ HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
+ HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
+ HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
+ (step 1 consists in entering the inner hash function key) */
+ HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
+ (step 2 consists in entering the message text) */
+ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
+ (step 3 consists in entering the outer hash function key) */
}HAL_HASH_PhaseTypeDef;
/**
- * @}
+ * @brief HAL HASH mode suspend definitions
*/
+typedef enum
+{
+ HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
+ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
+}HAL_HASH_SuspendTypeDef;
-/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
- * @{
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL HASH common Callback ID enumeration definition
*/
+typedef enum
+{
+ HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
+ HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
+ HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
+ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
+ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
+}HAL_HASH_CallbackIDTypeDef;
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+/**
+ * @brief HASH Handle Structure definition
+ */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+typedef struct __HASH_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
{
- HASH_InitTypeDef Init; /*!< HASH required parameters */
+ HASH_InitTypeDef Init; /*!< HASH required parameters */
+
+ uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+
+ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+
+ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+ uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+
+ uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+
+ __IO uint32_t HashInCount; /*!< Counter of inputted data */
+
+ __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
- uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
+ __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
- uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
+ HAL_StatusTypeDef Status; /*!< HASH peripheral status */
- __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
+ HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
- __IO uint32_t HashInCount; /*!< Counter of inputed data */
+ DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
- __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_StatusTypeDef Status; /*!< HASH peripheral status */
+ __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
- HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
+ HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
- DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
+ FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
- HAL_LockTypeDef Lock; /*!< HASH locking object */
+ __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
- __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
+ __IO uint32_t ErrorCode; /*!< HASH Error code */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
+
+ void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
+
+ void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
+
+ void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
+
+ void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
/**
- * @}
+ * @brief HAL HASH Callback pointer definition
*/
-
+typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup HASH_Exported_Constants HASH Exported Constants
+
+/** @defgroup HASH_Exported_Constants HASH Exported Constants
+ * @{
+ */
+
+/** @defgroup HASH_Algo_Selection HASH algorithm selection
* @{
*/
+#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
+#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
+#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
+/**
+ * @}
+ */
-/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
+/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
* @{
*/
-#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
-#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
-#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
-#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
+#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
+/** @defgroup HASH_Data_Type HASH input data type
* @{
*/
-#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
-#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
+#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
+#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
+#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
+#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
/**
* @}
*/
-/** @defgroup HASH_Data_Type HASH Data Type
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
* @{
*/
-#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
-#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
-#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
-#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
+#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
- * @brief HASH HMAC Long key used only for HMAC mode
+/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
-#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
+#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
+#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
+#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
+
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
+/** @defgroup HASH_interrupts_definition HASH interrupts definitions
+ * @{
+ */
+#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
+#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
+
+/**
+ * @}
+ */
+/** @defgroup HASH_alias HASH API alias
* @{
*/
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
+#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
/**
* @}
*/
-/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
+/** @defgroup HASH_Error_Definition HASH Error Definition
* @{
*/
-#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
+#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */
+#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -218,232 +270,356 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup HASH_Exported_Macros HASH Exported Macros
* @{
*/
-/** @brief Reset HASH handle state
- * @param __HANDLE__ specifies the HASH handle.
+/** @brief Check whether or not the specified HASH flag is set.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+ * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+ * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+ * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
+ ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+ ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief Clear the specified HASH flag.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+ * @arg @ref HASH_FLAG_DCIS Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief Enable the specified HASH interrupt.
+ * @param __INTERRUPT__: specifies the HASH interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Disable the specified HASH interrupt.
+ * @param __INTERRUPT__: specifies the HASH interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
+ * @arg @ref HASH_IT_DCI Digest calculation complete
+ * @retval None
+ */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+ * @param __HANDLE__: HASH handle.
* @retval None
*/
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ }while(0)
+#else
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-/** @brief Check whether the specified HASH flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
- * @arg HASH_FLAG_DCIS: Digest calculation complete
- * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
- * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
- * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+
+/** @brief Reset HASH handle status.
+ * @param __HANDLE__: HASH handle.
+ * @retval None
*/
-#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)))
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
/**
- * @brief Enable the multiple DMA mode.
- * This feature is available only in STM32F429x and STM32F439x devices.
+ * @brief Enable the multi-buffer DMA transfer mode.
+ * @note This bit is set when hashing large files when multiple DMA transfers are needed.
* @retval None
*/
-#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
+#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
/**
- * @brief Disable the multiple DMA mode.
+ * @brief Disable the multi-buffer DMA transfer mode.
* @retval None
*/
-#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
+#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
+
/**
- * @brief Start the digest computation
+ * @brief Start the digest computation.
* @retval None
*/
-#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
+#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
/**
- * @brief Set the number of valid bits in last word written in Data register
- * @param SIZE size in byte of last data written in Data register.
+ * @brief Set the number of valid bits in the last word written in data register DIN.
+ * @param __SIZE__: size in bytes of last data written in Data register.
* @retval None
*/
-#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
- HASH->STR |= 8U * ((SIZE) % 4U);\
- }while(0)
+#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
+
+/**
+ * @brief Reset the HASH core.
+ * @retval None
+ */
+#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
/**
* @}
*/
-/* Include HASH HAL Extension module */
-#include "stm32f4xx_hal_hash_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HASH_Exported_Functions HASH Exported Functions
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros HASH Private Macros
* @{
*/
-
-/** @addtogroup HASH_Exported_Functions_Group1
- * @{
+/**
+ * @brief Return digest length in bytes.
+ * @retval Digest length
*/
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+#if defined(HASH_CR_MDMAT)
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \
+ ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) )
+#else
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16)
+#endif
/**
- * @}
+ * @brief Return number of words already pushed in the FIFO.
+ * @retval Number of words already pushed in the FIFO
*/
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
-/** @addtogroup HASH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
- * @}
+ * @brief Ensure that HASH input data type is valid.
+ * @param __DATATYPE__: HASH input data type.
+ * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+ ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+ ((__DATATYPE__) == HASH_DATATYPE_1B))
-/** @addtogroup HASH_Exported_Functions_Group3
- * @{
+
+
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+ * processing in polling mode.
+ * @note This check is valid only for multi-buffer HASH processing in polling mode.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U)
/**
- * @}
+ * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HASH processing in DMA mode.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
-/** @addtogroup HASH_Exported_Functions_Group4
- * @{
+/**
+ * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
+ * processing in DMA mode.
+ * @note This check is valid only for multi-buffer HMAC processing in DMA mode.
+ * @param __HANDLE__: HASH handle.
+ * @param __SIZE__: input data buffer size.
+ * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
/**
- * @}
+ * @brief Ensure that handle phase is set to HASH processing.
+ * @param __HANDLE__: HASH handle.
+ * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
+#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
-/** @addtogroup HASH_Exported_Functions_Group5
- * @{
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
- * @}
+ * @brief Ensure that handle phase is set to HMAC processing.
+ * @param __HANDLE__: HASH handle.
+ * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
+#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+ ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-/** @addtogroup HASH_Exported_Functions_Group6
- * @{
- */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/** @addtogroup HASH_Exported_Functions_Group7
+/* Include HASH HAL Extended module */
+#include "stm32f4xx_hal_hash_ex.h"
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
-/**
- * @}
- */
-/** @addtogroup HASH_Exported_Functions_Group8
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+
+/* Initialization/de-initialization methods **********************************/
+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
- /**
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @{
+ */
+
+
+/* HASH processing using polling *********************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
* @}
*/
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HASH_Private_Types HASH Private Types
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
* @{
*/
+/* HASH processing using IT **************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Variables HASH Private Variables
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
* @{
*/
+/* HASH processing using DMA *************************************************/
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Constants HASH Private Constants
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
* @{
*/
+/* HASH-MAC processing using polling *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros HASH Private Macros
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
* @{
*/
-#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
- ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
- ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
+/**
+ * @}
+ */
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @{
+ */
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_8B) || \
- ((__DATATYPE__) == HASH_DATATYPE_1B))
+/* HASH-HMAC processing using DMA ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
+/**
+ * @}
+ */
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @{
+ */
-#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
- ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
-#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4U) != 0U)? 0U: 1U)
+/* Peripheral State methods **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+
+/** @addtogroup HASH_Private_Functions HASH Private Functions
* @{
*/
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
/**
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
*/
-
+#endif /* HASH*/
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_HASH_H */
+#endif /* STM32F4xx_HAL_HASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash_ex.h
index a1edda239f9d6547b0a5a4745dbdbb0bdbd2e6c8..e594b63b2b47b725cfbbb6a65ebef6c6da9ad214 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hash_ex.h
@@ -2,92 +2,65 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.h
* @author MCD Application Team
- * @brief Header file of HASH HAL Extension module.
+ * @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_HASH_EX_H
-#define __STM32F4xx_HAL_HASH_EX_H
+#ifndef STM32F4xx_HAL_HASH_EX_H
+#define STM32F4xx_HAL_HASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
+#if defined (HASH)
/** @addtogroup HASHEx
- * @brief HASHEx HAL Extension module driver
- * @{
+ * @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+
+
/* Exported functions --------------------------------------------------------*/
-/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
-/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions
+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @{
*/
@@ -98,10 +71,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @{
*/
-
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
@@ -111,88 +83,77 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
-
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
-/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @{
*/
-void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
-/**
- * @}
- */
-
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Types HASHEx Private Types
+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @{
*/
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Variables HASHEx Private Variables
- * @{
- */
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Constants HASHEx Private Constants
+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @{
*/
-/**
- * @}
- */
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Macros HASHEx Private Macros
- * @{
- */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HASHEx_Private_Functions HASHEx Private Functions
- * @{
- */
-
/**
* @}
*/
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
/**
* @}
*/
-
+#endif /* HASH*/
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_HASH_EX_H */
+
+#endif /* STM32F4xx_HAL_HASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hcd.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hcd.h
index 8a9b22b23277a39c7f0cc9815f28b217bcb8c1cb..5f4cccdc5bfab43757b605a34b6c13758827976d 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hcd.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_hcd.h
@@ -6,48 +6,29 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_HCD_H
-#define __STM32F4xx_HAL_HCD_H
+#ifndef STM32F4xx_HAL_HCD_H
+#define STM32F4xx_HAL_HCD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_usb.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -66,18 +47,18 @@
*/
typedef enum
{
- HAL_HCD_STATE_RESET = 0x00U,
- HAL_HCD_STATE_READY = 0x01U,
- HAL_HCD_STATE_ERROR = 0x02U,
- HAL_HCD_STATE_BUSY = 0x03U,
- HAL_HCD_STATE_TIMEOUT = 0x04U
+ HAL_HCD_STATE_RESET = 0x00,
+ HAL_HCD_STATE_READY = 0x01,
+ HAL_HCD_STATE_ERROR = 0x02,
+ HAL_HCD_STATE_BUSY = 0x03,
+ HAL_HCD_STATE_TIMEOUT = 0x04
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
-typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
/**
* @}
*/
@@ -85,14 +66,31 @@ typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{
*/
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
- HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
+ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
+ __IO uint32_t ErrorCode; /*!< HCD Error code */
void *pData; /*!< Pointer Stack Handler */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
+ void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
+ void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
+ void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
+ void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
+ void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+ HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
+
+ void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
} HCD_HandleTypeDef;
/**
* @}
@@ -110,9 +108,10 @@ typedef struct
/** @defgroup HCD_Speed HCD Speed
* @{
*/
-#define HCD_SPEED_HIGH 0U
-#define HCD_SPEED_LOW 2U
-#define HCD_SPEED_FULL 3U
+#define HCD_SPEED_HIGH USBH_HS_SPEED
+#define HCD_SPEED_FULL USBH_FS_SPEED
+#define HCD_SPEED_LOW USBH_LS_SPEED
+
/**
* @}
*/
@@ -122,6 +121,18 @@ typedef struct
*/
#define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
+/**
+ * @}
+ */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+ * @brief HCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -135,8 +146,8 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
-#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
@@ -156,24 +167,63 @@ typedef struct
* @{
*/
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
+
+HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+ * @brief HAL USB OTG HCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
+ HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
+ HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
+ HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
+ HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
+
+ HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
+ HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+ * @brief HAL USB OTG HCD Callback pointer definition
* @{
*/
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+ uint8_t epnum,
+ HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
+/**
+ * @}
+ */
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -182,23 +232,25 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+ uint8_t ch_num,
+ uint8_t direction,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t *pbuff,
+ uint16_t length,
+ uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
+ HCD_URBStateTypeDef urb_state);
/**
* @}
*/
@@ -207,9 +259,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -218,12 +270,12 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
@@ -241,6 +293,20 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
* @}
*/
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+ * @{
+ */
+
/**
* @}
*/
@@ -248,13 +314,16 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || defined(STM32F413xx) || defined(STM32F423xx) */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_HCD_H */
+#endif /* STM32F4xx_HAL_HCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c.h
index e44474a145da6ae03ae14442dc21fac2a1989578..2f3f947c4df996cf022c5994c2c6c2277f55bb08 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,7 +22,7 @@
#define __STM32F4xx_HAL_I2C_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -57,8 +41,9 @@
* @{
*/
-/**
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
+ * @{
*/
typedef struct
{
@@ -86,9 +71,13 @@ typedef struct
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
-}I2C_InitTypeDef;
+} I2C_InitTypeDef;
/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :
* b7-b6 Error information
@@ -96,23 +85,24 @@ typedef struct
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
+ * b5 Peripheral initilisation status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
* x : Should be set to 0
* b3
* 0 : Ready or Busy (No Listen mode ongoing)
- * 1 : Listen (IP in Address Listen Mode)
+ * 1 : Listen (Peripheral in Address Listen Mode)
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
+ * @{
*/
typedef enum
{
@@ -130,24 +120,29 @@ typedef enum
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-}HAL_I2C_StateTypeDef;
+} HAL_I2C_StateTypeDef;
/**
+ * @}
+ */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
- * @note HAL I2C Mode value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6
- * 0 : None
- * 1 : Memory (HAL I2C communication is in Memory Mode)
- * b5
- * 0 : None
- * 1 : Slave (HAL I2C communication is in Slave Mode)
- * b4
- * 0 : None
- * 1 : Master (HAL I2C communication is in Master Mode)
- * b3-b2-b1-b0 (not used)
+ * @note HAL I2C Mode value coding follow below described bitmap :\n
+ * b7 (not used)\n
+ * x : Should be set to 0\n
+ * b6\n
+ * 0 : None\n
+ * 1 : Memory (HAL I2C communication is in Memory Mode)\n
+ * b5\n
+ * 0 : None\n
+ * 1 : Slave (HAL I2C communication is in Slave Mode)\n
+ * b4\n
+ * 0 : None\n
+ * 1 : Master (HAL I2C communication is in Master Mode)\n
+ * b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
+ * @{
*/
typedef enum
{
@@ -156,12 +151,37 @@ typedef enum
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-}HAL_I2C_ModeTypeDef;
+} HAL_I2C_ModeTypeDef;
/**
+ * @}
+ */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
+#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
+ * @{
*/
-typedef struct
+typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
@@ -197,32 +217,67 @@ typedef struct
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
__IO uint32_t EventCount; /*!< I2C Event counter */
-
-}I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
- * @}
+ * @brief HAL I2C Callback ID enumeration definition
*/
+typedef enum
+{
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2C Callback pointer definition
*/
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
-/** @defgroup I2C_Error_Code I2C Error Code
- * @brief I2C Error Code
- * @{
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+ * @}
*/
-#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
-#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
-#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
-#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
+
/**
* @}
*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
@@ -291,14 +346,25 @@ typedef struct
* @{
*/
#define I2C_FIRST_FRAME 0x00000001U
-#define I2C_NEXT_FRAME 0x00000002U
-#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
-#define I2C_LAST_FRAME 0x00000008U
+#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
+#define I2C_NEXT_FRAME 0x00000004U
+#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
+#define I2C_LAST_FRAME_NO_STOP 0x00000010U
+#define I2C_LAST_FRAME 0x00000020U
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define I2C_OTHER_FRAME (0x00AA0000U)
+#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_BUF I2C_CR2_ITBUFEN
@@ -311,9 +377,7 @@ typedef struct
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
-#define I2C_FLAG_SMBALERT 0x00018000U
-#define I2C_FLAG_TIMEOUT 0x00014000U
-#define I2C_FLAG_PECERR 0x00011000U
+
#define I2C_FLAG_OVR 0x00010800U
#define I2C_FLAG_AF 0x00010400U
#define I2C_FLAG_ARLO 0x00010200U
@@ -326,8 +390,6 @@ typedef struct
#define I2C_FLAG_ADDR 0x00010002U
#define I2C_FLAG_SB 0x00010001U
#define I2C_FLAG_DUALF 0x00100080U
-#define I2C_FLAG_SMBHOST 0x00100040U
-#define I2C_FLAG_SMBDEFAULT 0x00100020U
#define I2C_FLAG_GENCALL 0x00100010U
#define I2C_FLAG_TRA 0x00100004U
#define I2C_FLAG_BUSY 0x00100002U
@@ -340,21 +402,28 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
-/** @brief Reset I2C handle state
+/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
/** @brief Enable or disable the specified I2C interrupts.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
@@ -362,12 +431,11 @@ typedef struct
* @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
@@ -379,12 +447,8 @@ typedef struct
/** @brief Checks whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
* @arg I2C_FLAG_AF: Acknowledge failure flag
* @arg I2C_FLAG_ARLO: Arbitration lost flag
@@ -398,25 +462,20 @@ typedef struct
* Address matched flag
* @arg I2C_FLAG_SB: Start bit flag
* @arg I2C_FLAG_DUALF: Dual flag
- * @arg I2C_FLAG_SMBHOST: SMBus host header
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
* @arg I2C_FLAG_GENCALL: General call header flag
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
* @arg I2C_FLAG_BUSY: Bus busy flag
* @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
+ (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
+ (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
* @arg I2C_FLAG_AF: Acknowledge failure flag
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
@@ -440,30 +499,27 @@ typedef struct
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
- UNUSED(tmpreg); \
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
+ UNUSED(tmpreg); \
} while(0)
-/** @brief Enable the I2C peripheral.
+/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-/** @brief Disable the I2C peripheral.
+/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
/**
* @}
@@ -477,22 +533,31 @@ typedef struct
* @{
*/
-/** @addtogroup I2C_Exported_Functions_Group1
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup I2C_Exported_Functions_Group2
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-/* I/O operation functions *****************************************************/
+/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -510,13 +575,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@@ -526,6 +591,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -543,10 +619,10 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
* @}
*/
-/** @addtogroup I2C_Exported_Functions_Group3
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
-/* Peripheral State, Mode and Errors functions *********************************/
+/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
@@ -564,7 +640,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
-#define I2C_FLAG_MASK 0x0000FFFFU
+#define I2C_FLAG_MASK 0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
+#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
/**
* @}
*/
@@ -574,15 +652,17 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
* @{
*/
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
@@ -611,9 +691,18 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
+ ((REQUEST) == I2C_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c_ex.h
index ff686a3e2a7077b3c5859d9fa2ed3bcb55c7dbf2..6864d83519f57451630a72eb533a36c721fb3d7a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2c_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,12 +22,10 @@
#define __STM32F4xx_HAL_I2C_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -123,9 +105,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
- STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx ||\
- STM32F413xx || STM32F423xx */
+#endif
#ifdef __cplusplus
}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s.h
index 67a7ec0b254bc9a0c8d94fb775cd9bfaf28b6afc..6530a5c2eeab57acbd98685c89663ffc87c54514 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2S_H
-#define __STM32F4xx_HAL_I2S_H
+#ifndef STM32F4xx_HAL_I2S_H
+#define STM32F4xx_HAL_I2S_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,7 +32,7 @@
* @{
*/
-/** @addtogroup I2S I2S
+/** @addtogroup I2S
* @{
*/
@@ -62,31 +46,29 @@
*/
typedef struct
{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
This parameter can be a value of @ref I2S_Clock_Source */
-
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
This parameter can be a value of @ref I2S_FullDuplex_Mode */
-
-}I2S_InitTypeDef;
+} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
@@ -101,27 +83,26 @@ typedef enum
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-
-}HAL_I2S_StateTypeDef;
+} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
typedef struct __I2S_HandleTypeDef
{
- SPI_TypeDef *Instance; /*!< I2S registers base address */
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
- I2S_InitTypeDef Init; /*!< I2S communication parameters */
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
@@ -129,21 +110,57 @@ typedef struct __I2S_HandleTypeDef
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
+ void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
- void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
- DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
- DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
- __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
- This parameter can be a value of @ref I2S_ErrorCode */
+ This parameter can be a value of @ref I2S_Error */
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
+ void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
+ void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL I2S Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
+ HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
+ HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */
+ HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
+ HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
+ HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */
+ HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
+ HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
+ HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
+
+} HAL_I2S_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2S Callback pointer definition
+ */
+typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
-}I2S_HandleTypeDef;
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -152,8 +169,7 @@ typedef struct __I2S_HandleTypeDef
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
-/**
- * @defgroup I2S_ErrorCode I2S Error Code
+/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
@@ -162,6 +178,9 @@ typedef struct __I2S_HandleTypeDef
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -170,9 +189,9 @@ typedef struct __I2S_HandleTypeDef
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
-#define I2S_MODE_SLAVE_RX (0x00000100U)
-#define I2S_MODE_MASTER_TX (0x00000200U)
-#define I2S_MODE_MASTER_RX (0x00000300U)
+#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
@@ -181,10 +200,10 @@ typedef struct __I2S_HandleTypeDef
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
-#define I2S_STANDARD_MSB (0x00000010U)
-#define I2S_STANDARD_LSB (0x00000020U)
-#define I2S_STANDARD_PCM_SHORT (0x00000030U)
-#define I2S_STANDARD_PCM_LONG (0x000000B0U)
+#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
@@ -193,18 +212,18 @@ typedef struct __I2S_HandleTypeDef
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
-#define I2S_DATAFORMAT_24B (0x00000003U)
-#define I2S_DATAFORMAT_32B (0x00000005U)
+#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
-#define I2S_MCLKOUTPUT_ENABLE SPI_I2SPR_MCKOE
-#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
+#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
@@ -229,17 +248,17 @@ typedef struct __I2S_HandleTypeDef
/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
* @{
*/
-#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
-#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
+#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
+#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
/**
* @}
*/
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW (0x00000000U)
-#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
@@ -247,9 +266,9 @@ typedef struct __I2S_HandleTypeDef
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
@@ -257,42 +276,41 @@ typedef struct __I2S_HandleTypeDef
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+
+#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
+
/** @defgroup I2S_Clock_Source I2S Clock Source Definition
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
- defined(STM32F479xx)
-#define I2S_CLOCK_PLL (0x00000000U)
-#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
+#define I2S_CLOCK_PLL (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
- defined(STM32F413xx) || defined(STM32F423xx)
-#define I2S_CLOCK_PLL (0x00000000U)
-#define I2S_CLOCK_EXTERNAL (0x00000001U)
-#define I2S_CLOCK_PLLR (0x00000002U)
-#define I2S_CLOCK_PLLSRC (0x00000003U)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define I2S_CLOCK_PLL (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_PLLR (0x00000002U)
+#define I2S_CLOCK_PLLSRC (0x00000003U)
#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define I2S_CLOCK_PLLSRC (0x00000000U)
-#define I2S_CLOCK_EXTERNAL (0x00000001U)
-#define I2S_CLOCK_PLLR (0x00000002U)
+#define I2S_CLOCK_PLLSRC (0x00000000U)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_PLLR (0x00000002U)
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
/**
* @}
@@ -302,25 +320,49 @@ typedef struct __I2S_HandleTypeDef
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
-/** @brief Reset I2S handle state
+/** @brief Reset I2S handle state
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif
+
+/** @brief Enable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &=(uint16_t)(~SPI_I2SCFGR_I2SE))
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Enable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-/** @brief Enable or disable the specified I2S interrupts.
+/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
@@ -329,8 +371,7 @@ typedef struct __I2S_HandleTypeDef
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &=(uint16_t)(~(__INTERRUPT__)))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
@@ -363,24 +404,21 @@ typedef struct __I2S_HandleTypeDef
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
-
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ }while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
/**
* @}
*/
@@ -389,31 +427,37 @@ typedef struct __I2S_HandleTypeDef
#include "stm32f4xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
+/** @addtogroup I2S_Exported_Functions
* @{
*/
-/** @defgroup I2S_Exported_Functions_Group1 I2S Initialization and de-initialization functions
+/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group2 I2S IO operation functions
+/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
-/* I/O operation functions *****************************************************/
+/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
@@ -436,7 +480,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group3 I2S Peripheral Control and State functions
+/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
@@ -465,47 +509,78 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX))
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of I2S SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun error flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_CHSIDE: Channel side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
+/** @brief Checks if I2S Mode parameter is in allowed range.
+ * @param __MODE__ specifies the I2S Mode.
+ * This parameter can be a value of @ref I2S_Mode
+ * @retval None
+ */
+#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
+ ((__MODE__) == I2S_MODE_SLAVE_RX) || \
+ ((__MODE__) == I2S_MODE_MASTER_TX) || \
+ ((__MODE__) == I2S_MODE_MASTER_RX))
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
+ ((__STANDARD__) == I2S_STANDARD_MSB) || \
+ ((__STANDARD__) == I2S_STANDARD_LSB) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
+ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
+/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the I2S serial clock steady state.
+ * This parameter can be a value of @ref I2S_Clock_Polarity
+ * @retval None
+ */
+#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
+ ((__CPOL__) == I2S_CPOL_HIGH))
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
- defined(STM32F479xx)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
((CLOCK) == I2S_CLOCK_PLL))
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) ||\
- defined(STM32F423xx)
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
((CLOCK) == I2S_CLOCK_PLL) ||\
((CLOCK) == I2S_CLOCK_PLLSRC) ||\
@@ -517,12 +592,10 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
((CLOCK) == I2S_CLOCK_PLLSRC) ||\
((CLOCK) == I2S_CLOCK_PLLR))
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
@@ -535,7 +608,6 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
}
#endif
-
-#endif /* __STM32F4xx_HAL_I2S_H */
+#endif /* STM32F4xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s_ex.h
index 8b92e2bd0b96017095c9bbeec4c547ae73cf38d8..19cd806181c280e547e33261505840b924068500 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_i2s_ex.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_I2S_EX_H
-#define __STM32F4xx_HAL_I2S_EX_H
+#ifndef STM32F4xx_HAL_I2S_EX_H
+#define STM32F4xx_HAL_I2S_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -185,6 +169,6 @@ void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
#endif
-#endif /* __STM32F4xx_HAL_I2S_EX_H */
+#endif /* STM32F4xx_HAL_I2S_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_irda.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_irda.h
index 4b870f893b2d31ffda58debef49a6d486cbab299..b30945e78ff0c37077c3d73943d9813ef26bc3f4 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_irda.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_irda.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,7 +22,7 @@
#define __STM32F4xx_HAL_IRDA_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -69,21 +53,24 @@ typedef struct
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDA_Word_Length */
- uint32_t Parity; /*!< Specifies the parity mode.
+ uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Mode */
- uint8_t Prescaler; /*!< Specifies the Prescaler */
+ uint8_t Prescaler; /*!< Specifies the Prescaler value to be programmed
+ in the IrDA low-power Baud Register, for defining pulse width on which
+ burst acceptance/rejection will be decided. This value is used as divisor
+ of system clock to achieve required pulse width. */
uint32_t IrDAMode; /*!< Specifies the IrDA mode
This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
+} IRDA_InitTypeDef;
/**
* @brief HAL IRDA State structures definition
@@ -143,45 +130,100 @@ typedef enum
Value is allowed for gState only */
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
+} HAL_IRDA_StateTypeDef;
/**
* @brief IRDA handle Structure definition
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- IRDA_InitTypeDef Init; /* IRDA communication parameters */
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
- uint16_t TxXferSize; /* IRDA Tx Transfer size */
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
- __IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
- uint16_t RxXferSize; /* IRDA Rx Transfer size */
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
- __IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
- __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
+ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
- __IO uint32_t ErrorCode; /* IRDA Error code */
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
+
+ void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
+
+ void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
+
+ void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
+
+ void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
+
+
+ void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL IRDA Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
+ HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
+ HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
+ HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
+ HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
+ HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
+ HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
+ HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
+
+ HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
+ HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+ * @brief HAL IRDA Callback pointer definition
+ */
+typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-}IRDA_HandleTypeDef;
/**
* @}
*/
@@ -191,15 +233,17 @@ typedef struct
* @{
*/
/** @defgroup IRDA_Error_Code IRDA Error Code
- * @brief IRDA Error Code
* @{
*/
-#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -207,8 +251,8 @@ typedef struct
/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
-#define IRDA_WORDLENGTH_8B 0x00000000U
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define IRDA_WORDLENGTH_8B 0x00000000U
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
@@ -216,9 +260,9 @@ typedef struct
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
-#define IRDA_PARITY_NONE 0x00000000U
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define IRDA_PARITY_NONE 0x00000000U
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
@@ -226,9 +270,9 @@ typedef struct
/** @defgroup IRDA_Mode IRDA Transfer Mode
* @{
*/
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
* @}
*/
@@ -236,8 +280,8 @@ typedef struct
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL 0x00000000U
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL 0x00000000U
/**
* @}
*/
@@ -247,14 +291,14 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define IRDA_FLAG_TXE 0x00000080U
-#define IRDA_FLAG_TC 0x00000040U
-#define IRDA_FLAG_RXNE 0x00000020U
-#define IRDA_FLAG_IDLE 0x00000010U
-#define IRDA_FLAG_ORE 0x00000008U
-#define IRDA_FLAG_NE 0x00000004U
-#define IRDA_FLAG_FE 0x00000002U
-#define IRDA_FLAG_PE 0x00000001U
+#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
+#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
+#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
+#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
@@ -268,16 +312,16 @@ typedef struct
* - 11: CR3 register
* @{
*/
-#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -292,27 +336,37 @@ typedef struct
*/
/** @brief Reset IRDA handle gstate & RxState
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
-/** @brief Flushs the IRDA DR register
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+/** @brief Flush the IRDA DR register
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-/** @brief Checks whether the specified IRDA flag is set or not.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+/** @brief Check whether the specified IRDA flag is set or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
@@ -327,10 +381,10 @@ typedef struct
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-/** @brief Clears the specified IRDA pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg IRDA_FLAG_TC: Transmission Complete flag.
@@ -344,61 +398,78 @@ typedef struct
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
- *
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enables or disables the specified IRDA interrupt.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
- * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
+/** @brief Enable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+/** @brief Disable the specified IRDA interrupt.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -408,35 +479,32 @@ typedef struct
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-/** @brief Checks whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * IRDA Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __IT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
* @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ERR: Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
/** @brief Macro to enable the IRDA's one bit sample method
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
/** @brief Macro to disable the IRDA's one bit sample method
* @param __HANDLE__ specifies the IRDA Handle.
@@ -450,7 +518,7 @@ typedef struct
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
-#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
/** @brief Disable UART/USART associated to IRDA Handle
* @param __HANDLE__ specifies the IRDA Handle.
@@ -458,7 +526,7 @@ typedef struct
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
-#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
/**
* @}
@@ -477,6 +545,13 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -542,9 +617,9 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-#define IRDA_CR1_REG_INDEX 1U
-#define IRDA_CR2_REG_INDEX 2U
-#define IRDA_CR3_REG_INDEX 3U
+#define IRDA_CR1_REG_INDEX 1U
+#define IRDA_CR2_REG_INDEX 2U
+#define IRDA_CR3_REG_INDEX 3U
/**
* @}
*/
@@ -553,24 +628,31 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/** @defgroup IRDA_Private_Macros IRDA Private Macros
* @{
*/
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
-#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+
+#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
+
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
+
+#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+
+#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
+
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_iwdg.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_iwdg.h
index 8f4ddfa50afc63fefcd9da529b196c676fa2542c..ced1099f31899d0ced156d259cadd9cfeb3fa635 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_iwdg.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_iwdg.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_IWDG_H
-#define __STM32F4xx_HAL_IWDG_H
+#ifndef STM32F4xx_HAL_IWDG_H
+#define STM32F4xx_HAL_IWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,7 +32,7 @@
* @{
*/
-/** @addtogroup IWDG
+/** @defgroup IWDG IWDG
* @{
*/
@@ -78,8 +62,8 @@ typedef struct
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
-}IWDG_HandleTypeDef;
/**
* @}
@@ -93,17 +77,20 @@ typedef struct
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
-#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+
/**
* @}
*/
+
+
/**
* @}
*/
@@ -122,7 +109,7 @@ typedef struct
/**
* @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR & IWDG_RLR registers disabled).
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@@ -167,10 +154,10 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @brief IWDG Key Register BitMask
*/
-#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
@@ -215,6 +202,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+
+
/**
* @}
*/
@@ -232,6 +221,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
}
#endif
-#endif /* __STM32F4xx_HAL_IWDG_H */
+#endif /* STM32F4xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_lptim.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_lptim.h
index 845006ac8a26628e11478bd548d7706cd6333b1b..39a8164553cd55de3591d201452649390c375862 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_lptim.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_lptim.h
@@ -4,44 +4,26 @@
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
- * @attention
+ * @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ * ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_LPTIM_H
-#define __STM32F4xx_HAL_LPTIM_H
+#ifndef STM32F4xx_HAL_LPTIM_H
+#define STM32F4xx_HAL_LPTIM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -49,8 +31,9 @@
* @{
*/
-/** @defgroup LPTIM LPTIM
- * @brief LPTIM HAL module driver
+#if defined (LPTIM1)
+
+/** @addtogroup LPTIM
* @{
*/
@@ -58,14 +41,7 @@
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
-
-/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
- * @{
- */
-#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
-/**
- * @}
- */
+#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
* @brief LPTIM Clock configuration definition
@@ -78,7 +54,7 @@ typedef struct
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-}LPTIM_ClockConfigTypeDef;
+} LPTIM_ClockConfigTypeDef;
/**
* @brief LPTIM Clock configuration definition
@@ -96,7 +72,7 @@ typedef struct
Note: This parameter is used only when Ultra low power clock source is used.
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-}LPTIM_ULPClockConfigTypeDef;
+} LPTIM_ULPClockConfigTypeDef;
/**
* @brief LPTIM Trigger configuration definition
@@ -113,7 +89,7 @@ typedef struct
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
-}LPTIM_TriggerConfigTypeDef;
+} LPTIM_TriggerConfigTypeDef;
/**
* @brief LPTIM Initialization Structure definition
@@ -129,45 +105,82 @@ typedef struct
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */
- uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
+ uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event.
This parameter can be a value of @ref LPTIM_Counter_Source */
-
-}LPTIM_InitTypeDef;
+} LPTIM_InitTypeDef;
/**
* @brief HAL LPTIM State structure definition
*/
-typedef enum __HAL_LPTIM_StateTypeDef
+typedef enum
{
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
-}HAL_LPTIM_StateTypeDef;
+} HAL_LPTIM_StateTypeDef;
/**
* @brief LPTIM handle Structure definition
*/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+typedef struct __LPTIM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
{
- LPTIM_TypeDef *Instance; /*!< Register base address */
+ LPTIM_TypeDef *Instance; /*!< Register base address */
- LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
- HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
- HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
- __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
-}LPTIM_HandleTypeDef;
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
+ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
+ void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
+ void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
+ void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
+ void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
+ void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
+ void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
+ void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+} LPTIM_HandleTypeDef;
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL LPTIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
+ HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
+ HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
+ HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
+ HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
+ HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
+ HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
+ HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
+ HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
+} HAL_LPTIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
+
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -180,7 +193,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00U
+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
@@ -192,11 +205,11 @@ typedef struct
#define LPTIM_PRESCALER_DIV1 0x00000000U
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
-#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
+#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
-#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
-#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
+#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
+#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
/**
* @}
*/
@@ -206,7 +219,7 @@ typedef struct
*/
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
-#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
+#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
/**
* @}
*/
@@ -214,10 +227,10 @@ typedef struct
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
-#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
-#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
-#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
/**
* @}
*/
@@ -225,10 +238,9 @@ typedef struct
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
* @{
*/
-
-#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
-#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
-#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
+#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
+#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
+#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
* @}
*/
@@ -238,11 +250,11 @@ typedef struct
*/
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define LPTIM_TRIGSOURCE_0 0x00000000U
-#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
+#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
-#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
+#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
-#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
+#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
/**
* @}
*/
@@ -288,7 +300,7 @@ typedef struct
* @}
*/
-/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
* @{
*/
@@ -306,7 +318,6 @@ typedef struct
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
-
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
@@ -325,7 +336,6 @@ typedef struct
#define LPTIM_OP_PAD_PA4 LPTIM_OR_LPT_IN1_RMP_0
#define LPTIM_OP_PAD_PB9 LPTIM_OR_LPT_IN1_RMP_1
#define LPTIM_OP_TIM_DAC LPTIM_OR_LPT_IN1_RMP
-
/**
* @}
*/
@@ -334,54 +344,75 @@ typedef struct
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
-/** @brief Reset LPTIM handle state
+/** @brief Reset LPTIM handle state.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
- * @brief Enable/Disable the LPTIM peripheral.
+ * @brief Enable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
-#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
-#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
+#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
/**
- * @brief Starts the LPTIM peripheral in Continuous or in single mode.
- * @param __HANDLE__ DMA handle
+ * @brief Disable the LPTIM peripheral.
+ * @param __HANDLE__ LPTIM handle
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @retval None
+ */
+#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
+
+/**
+ * @brief Start the LPTIM peripheral in Continuous mode.
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
+/**
+ * @brief Start the LPTIM peripheral in single mode.
+ * @param __HANDLE__ LPTIM handle
+ * @retval None
+ */
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
-
/**
- * @brief Writes the passed parameter in the Autoreload register.
+ * @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
- * @param __VALUE__ Autoreload value
+ * @param __VALUE__ Autoreload value
* @retval None
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
- * @brief Writes the passed parameter in the Compare register.
+ * @brief Write the passed parameter in the Compare register.
* @param __HANDLE__ LPTIM handle
- * @param __VALUE__ Compare value
+ * @param __VALUE__ Compare value
* @retval None
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
- * @brief Checks whether the specified LPTIM flag is set or not.
+ * @brief Check whether the specified LPTIM flag is set or not.
* @param __HANDLE__ LPTIM handle
- * @param __FLAG__ LPTIM flag to check
+ * @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -395,9 +426,9 @@ typedef struct
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the specified LPTIM flag.
+ * @brief Clear the specified LPTIM flag.
* @param __HANDLE__ LPTIM handle.
- * @param __FLAG__ LPTIM flag to clear.
+ * @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -408,12 +439,12 @@ typedef struct
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval None.
*/
-#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified LPTIM interrupt.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -424,12 +455,12 @@ typedef struct
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
*/
-#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
- /**
+/**
* @brief Disable the specified LPTIM interrupt.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -440,12 +471,12 @@ typedef struct
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
*/
-#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
- /**
- * @brief Checks whether the specified LPTIM interrupt is set or not.
- * @param __HANDLE__ LPTIM handle.
- * @param __INTERRUPT__ LPTIM interrupt to check.
+/**
+ * @brief Check whether the specified LPTIM interrupt source is enabled or not.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -470,6 +501,7 @@ typedef struct
*/
#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__))
+
/**
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
@@ -524,16 +556,15 @@ typedef struct
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
- }while(0U)
+ }while(0)
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
- * This parameter can be:
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
- }while(0U)
+ }while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
@@ -556,6 +587,7 @@ typedef struct
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
@@ -635,6 +667,12 @@ void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
@@ -674,30 +712,32 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
* @{
*/
-#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
- ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
+ ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
+
+
+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
+ ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
-#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
- ((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
-#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
- ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
+ ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
- ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
+ ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
-#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
@@ -707,28 +747,28 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5))
-#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
- ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
- ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
+ ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
-#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
- ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
+ ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
-#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
- ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
+#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
+ ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
-#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
- ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
+ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
-#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
+#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
-#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
+#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
-#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
+#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
/**
* @}
@@ -738,7 +778,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
-
+void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
/**
* @}
*/
@@ -747,15 +787,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
* @}
*/
+#endif /* LPTIM1 */
/**
* @}
*/
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_LPTIM_H */
+#endif /* STM32F4xx_HAL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc.h
index a51ef88726fb8cc92d7f161ed96793fe8e79246a..a862f2cc8ed7679abb551a1819cafc2ef268ffc9 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc.h
@@ -6,45 +6,31 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_LTDC_H
-#define __STM32F4xx_HAL_LTDC_H
+#ifndef STM32F4xx_HAL_LTDC_H
+#define STM32F4xx_HAL_LTDC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (LTDC)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -174,12 +160,16 @@ typedef enum
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
-}HAL_LTDC_StateTypeDef;
+} HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+typedef struct __LTDC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
@@ -193,7 +183,41 @@ typedef struct
__IO uint32_t ErrorCode; /*!< LTDC Error code */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
+ void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
+ void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
+
+ void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
+ void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
+
} LTDC_HandleTypeDef;
+
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL LTDC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
+ HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
+
+ HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
+ HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
+ HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
+
+} HAL_LTDC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL LTDC Callback pointer definition
+ */
+typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
+
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -210,6 +234,9 @@ typedef struct
#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -373,7 +400,15 @@ typedef struct
* @param __HANDLE__ LTDC handle
* @retval None
*/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @brief Enable the LTDC.
@@ -503,11 +538,18 @@ typedef struct
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
-void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
-void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -614,7 +656,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_SRCR_VBR))
+#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
@@ -636,12 +678,12 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
* @}
*/
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#endif /* LTDC */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_LTDC_H */
+#endif /* STM32F4xx_HAL_LTDC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc_ex.h
index 01d182c89e28e446a9a83ae9b2c9e8c22ea624d0..b46457fea485656262f971ff3ad9f07ce29237b9 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_ltdc_ex.h
@@ -6,42 +6,27 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_LTDC_EX_H
-#define __STM32F4xx_HAL_LTDC_EX_H
+#ifndef STM32F4xx_HAL_LTDC_EX_H
+#define STM32F4xx_HAL_LTDC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (LTDC) && defined (DSI)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_dsi.h"
@@ -65,8 +50,8 @@
/** @addtogroup LTDCEx_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
@@ -89,12 +74,12 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
* @}
*/
-#endif /* STM32F469xx || STM32F479xx */
+#endif /* LTDC && DSI */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_LTDC_EX_H */
+#endif /* STM32F4xx_HAL_LTDC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_mmc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_mmc.h
index 14d45f91e1170aefde6aff1ad1242798eca7db4b..c53e706b295d0aa03725e3a3747a809fa339c650 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_mmc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_mmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -131,7 +115,11 @@ typedef struct
/**
* @brief MMC handle Structure definition
*/
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+typedef struct __MMC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
@@ -162,7 +150,15 @@ typedef struct
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4U]; /*!< MMC card identification number table */
-
+ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
+
+ void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
+ void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
+#endif
}MMC_HandleTypeDef;
/**
@@ -255,10 +251,35 @@ typedef struct
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
}HAL_MMC_CardStatusTypeDef;
+/**
+ * @}
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
+ HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
+ HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
+ HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
+
+ HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
+ HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
+}HAL_MMC_CallbackIDTypeDef;
/**
* @}
*/
+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
+ * @{
+ */
+typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+#endif
/**
* @}
*/
@@ -311,7 +332,9 @@ typedef struct
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -364,6 +387,19 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+/** @brief Reset MMC handle state.
+ * @param __HANDLE__ : MMC handle.
+ * @retval None
+ */
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
+#endif
/**
* @brief Enable the MMC device.
@@ -594,6 +630,12 @@ void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+
+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
+/* MMC callback registering/unregistering */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nand.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nand.h
index fd6552e20f30f0040b56ef115b4daf6ba6ca83cc..7395751c703a6d351d9552befe12b27268ac76ed 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nand.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nand.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -140,7 +124,11 @@ typedef struct
/**
* @brief NAND handle Structure definition
*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+typedef struct __NAND_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
@@ -152,7 +140,30 @@ typedef struct
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
-}NAND_HandleTypeDef;
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
+#endif
+} NAND_HandleTypeDef;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL NAND Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
+ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
+ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
+}HAL_NAND_CallbackIDTypeDef;
+
+/**
+ * @brief HAL NAND Callback pointer definition
+ */
+typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
+#endif
+
/**
* @}
*/
@@ -167,7 +178,15 @@ typedef struct
* @param __HANDLE__ specifies the NAND handle.
* @retval None
*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+#endif
/**
* @}
@@ -222,6 +241,12 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressT
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/* NAND callback registering/unregistering */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nor.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nor.h
index 3e8ad8c56624377667ca598f450cb61ab0e50fbb..f668085b3624e2a4e134c9761818d9c05d536e0c 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nor.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_nor.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -131,7 +115,12 @@ typedef struct
/**
* @brief NOR handle Structure definition
*/
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+typedef struct __NOR_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
+
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -143,7 +132,27 @@ typedef struct
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-}NOR_HandleTypeDef;
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
+#endif
+} NOR_HandleTypeDef;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL NOR Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
+ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
+}HAL_NOR_CallbackIDTypeDef;
+
+/**
+ * @brief HAL NOR Callback pointer definition
+ */
+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
+#endif
/**
* @}
*/
@@ -157,7 +166,15 @@ typedef struct
* @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_NOR_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+#endif
/**
* @}
*/
@@ -195,6 +212,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/* NOR callback registering/unregistering */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pccard.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pccard.h
index 311d73b9c51c1a07a193ffb86099867b981f0e87..fa47bc25f92f945e0ae130a410d27944c6e7cc86 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pccard.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pccard.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -88,7 +72,11 @@ typedef enum
/**
* @brief FMC_PCCARD handle Structure definition
*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+typedef struct __PCCARD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
@@ -98,7 +86,29 @@ typedef struct
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
-}PCCARD_HandleTypeDef;
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */
+ void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */
+ void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */
+#endif
+} PCCARD_HandleTypeDef;
+
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL PCCARD Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
+ HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
+ HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
+}HAL_PCCARD_CallbackIDTypeDef;
+
+/**
+ * @brief HAL PCCARD Callback pointer definition
+ */
+typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
+#endif
/**
* @}
*/
@@ -112,7 +122,15 @@ typedef struct
* @param __HANDLE__ specifies the PCCARD handle.
* @retval None
*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+#endif
/**
* @}
*/
@@ -146,6 +164,11 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/* PCCARD callback registering/unregistering */
+HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd.h
index 5461c445ec5cd9d467d902645ddb88a8226c8af2..2db595c44c4c738c667f9433ef33ba5d2bab0a70 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd.h
@@ -6,48 +6,30 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PCD_H
-#define __STM32F4xx_HAL_PCD_H
+#ifndef STM32F4xx_HAL_PCD_H
+#define STM32F4xx_HAL_PCD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_usb.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -66,58 +48,100 @@
*/
typedef enum
{
- HAL_PCD_STATE_RESET = 0x00U,
- HAL_PCD_STATE_READY = 0x01U,
- HAL_PCD_STATE_ERROR = 0x02U,
- HAL_PCD_STATE_BUSY = 0x03U,
- HAL_PCD_STATE_TIMEOUT = 0x04U
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
-#ifdef USB_OTG_GLPMCFG_LPMEN
/* Device LPM suspend state */
typedef enum
{
- LPM_L0 = 0x00U, /* on */
- LPM_L1 = 0x01U, /* LPM L1 sleep */
- LPM_L2 = 0x02U, /* suspend */
- LPM_L3 = 0x03U /* off */
-}PCD_LPM_StateTypeDef;
-#endif /* USB_OTG_GLPMCFG_LPMEN */
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+typedef enum
+{
+ PCD_BCD_ERROR = 0xFF,
+ PCD_BCD_CONTACT_DETECTION = 0xFE,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
+typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief PCD Handle Structure definition
*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12U]; /*!< Setup packet buffer */
-#ifdef USB_OTG_GLPMCFG_LPMEN
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
- uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-#ifdef USB_OTG_GCCFG_BCDEN
- uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
-#endif /* USB_OTG_GCCFG_BCDEN */
- void *pData; /*!< Pointer to upper stack Handler */
+
+
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
+ void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
+ void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
+ void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
+ void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
+ void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
+ void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
+
+ void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
+ void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
+ void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
+ void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
+ void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
+ void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
+
+ void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
* @}
*/
-/* Include PCD HAL Extension module */
+/* Include PCD HAL Extended module */
#include "stm32f4xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
@@ -128,9 +152,9 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#define PCD_SPEED_HIGH 0U
-#define PCD_SPEED_HIGH_IN_FULL 1U
-#define PCD_SPEED_FULL 2U
+#define PCD_SPEED_HIGH USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
@@ -140,19 +164,19 @@ typedef struct
*/
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
+#define PCD_PHY_UTMI 3U
/**
* @}
*/
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+ * @brief PCD Error Code definition
* @{
*/
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE 9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE 5U
-#endif /* USBD_FS_TRDT_VALUE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -166,72 +190,45 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
-#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
+ ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10U)
-
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_HS_WAKEUP_EXTI_LINE 0x00100000U /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
- }while(0U)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- }while(0U)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
- }while(0U)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
- }while(0U)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- }while(0U)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+ do { \
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
+ } while(0U)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
- }while(0U)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**
* @}
*/
@@ -249,6 +246,68 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+ * @brief HAL USB OTG PCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
+ HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
+ HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
+ HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
+ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
+ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+
+ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
+ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+ * @brief HAL USB OTG PCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
+
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -258,22 +317,22 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
@@ -289,7 +348,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
@@ -312,6 +371,60 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @}
*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
+#endif
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
@@ -328,14 +441,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F4xx_HAL_PCD_H */
+#endif /* STM32F4xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd_ex.h
index 86bb1db357a571c10cf150f724b1a18e600e7cd6..71e9a2c18b4f44f9db226da440e17b0ce3c05f43 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pcd_ex.h
@@ -2,52 +2,33 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.h
* @author MCD Application Team
- * @brief Header file of PCD HAL module.
+ * @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PCD_EX_H
-#define __STM32F4xx_HAL_PCD_EX_H
+#ifndef STM32F4xx_HAL_PCD_EX_H
+#define STM32F4xx_HAL_PCD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -56,52 +37,32 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-typedef enum
-{
- PCD_LPM_L0_ACTIVE = 0x00U, /* on */
- PCD_LPM_L1_ACTIVE = 0x01U /* LPM L1 sleep */
-}PCD_LPM_MsgTypeDef;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-typedef enum
-{
- PCD_BCD_ERROR = 0xFFU,
- PCD_BCD_CONTACT_DETECTION = 0xFEU,
- PCD_BCD_STD_DOWNSTREAM_PORT = 0xFDU,
- PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFCU,
- PCD_BCD_DEDICATED_CHARGING_PORT = 0xFBU,
- PCD_BCD_DISCOVERY_COMPLETED = 0x00U
-}PCD_BCD_MsgTypeDef;
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
-
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-void HAL_PCDEx_ADP_Sensing_Start(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx*/
/**
* @}
@@ -118,14 +79,13 @@ void HAL_PCDEx_ADP_Sensing_Callback(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_PCD_EX_H */
+#endif /* STM32F4xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr.h
index 5e1a8fd08acd644087bff3bcce384d566528f273..1a4b27bab5bb425c6eb3d68a486444c95879e143 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr_ex.h
index 956b1a1e540f26112c271d555b0f3409e27a9677..e461bff84cbbb6741a4f71d4f20fa0ca5d623433 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_pwr_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -225,11 +209,6 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-#if defined(STM32F469xx) || defined(STM32F479xx)
-void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
-void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
-#endif /* STM32F469xx || STM32F479xx */
-
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
@@ -298,11 +277,6 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of WUPP bit */
-#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos
-#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
-#endif /* STM32F469xx || STM32F479xx */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_qspi.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_qspi.h
index 054f7a96aa93613673c69d7a32bdfd80df821caf..039558aa04164865b574cd142ff20f5f387112de 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_qspi.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_qspi.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -114,7 +98,11 @@ typedef enum
/**
* @brief QSPI Handle Structure definition
*/
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+typedef struct __QSPI_HandleTypeDef
+#else
typedef struct
+#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
@@ -129,6 +117,21 @@ typedef struct
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
+ void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
+
+ void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
+ void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
+#endif
}QSPI_HandleTypeDef;
/**
@@ -197,6 +200,33 @@ typedef struct
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL QSPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
+ HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
+ HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
+ HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
+ HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
+ HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
+ HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
+ HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
+ HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
+ HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
+
+ HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
+ HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
+}HAL_QSPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL QSPI Callback pointer definition
+ */
+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
+#endif
/**
* @}
*/
@@ -213,6 +243,9 @@ typedef struct
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
+#endif
/**
* @}
*/
@@ -434,7 +467,15 @@ typedef struct
* @param __HANDLE__ QSPI handle.
* @retval None
*/
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+#endif
/** @brief Enable QSPI
* @param __HANDLE__ specifies the QSPI Handle.
@@ -582,6 +623,12 @@ void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
+
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/* QSPI callback registering/unregistering */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc.h
index fc89426f80d5924979967deb9bed1dde12f66734..36a639b45f577de991b3c174219e02f142388280 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc_ex.h
index 7cc12ed47dbc0ad1c6b382466da13e45bac43814..3cb7b6e56a1817bd25af43916842517b75ac921c 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rcc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -4730,6 +4714,7 @@ typedef struct
* using it.
* @{
*/
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
@@ -4737,6 +4722,8 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
UNUSED(tmpreg); \
} while(0U)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
@@ -4744,6 +4731,8 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
UNUSED(tmpreg); \
} while(0U)
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
@@ -4758,6 +4747,7 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
UNUSED(tmpreg); \
} while(0U)
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
@@ -4765,11 +4755,16 @@ typedef struct
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
UNUSED(tmpreg); \
} while(0U)
-
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
/**
* @}
@@ -4782,16 +4777,28 @@ typedef struct
* using it.
* @{
*/
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
/**
* @}
@@ -5346,16 +5353,28 @@ typedef struct
* @brief Force or release AHB1 peripheral reset.
* @{
*/
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */
#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rng.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rng.h
index b56074ec111dfdf54309148d1851c9911cad8c9c..a7b1a59804252b5a17d9ad921f8999d24516a136 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rng.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rng.h
@@ -6,47 +6,25 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RNG_H
-#define __STM32F4xx_HAL_RNG_H
+#ifndef STM32F4xx_HAL_RNG_H
+#define STM32F4xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
- defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
- defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -54,6 +32,8 @@
* @{
*/
+#if defined (RNG)
+
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
@@ -65,7 +45,15 @@
* @{
*/
-/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
* @{
*/
typedef enum
@@ -76,16 +64,20 @@ typedef enum
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
-}HAL_RNG_StateTypeDef;
+} HAL_RNG_StateTypeDef;
/**
* @}
*/
-/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+typedef struct __RNG_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
{
RNG_TypeDef *Instance; /*!< Register base address */
@@ -93,9 +85,40 @@ typedef struct
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
+ __IO uint32_t ErrorCode; /*!< RNG Error code */
+
uint32_t RandomNumber; /*!< Last Generated RNG Data */
-}RNG_HandleTypeDef;
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
+ void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
+
+ void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
+ void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+} RNG_HandleTypeDef;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RNG Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
+
+ HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
+ HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
+
+} HAL_RNG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RNG Callback pointer definition
+ */
+typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
+typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
@@ -106,7 +129,6 @@ typedef struct
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
@@ -127,7 +149,21 @@ typedef struct
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
+/**
+ * @}
+ */
+/** @defgroup RNG_Error_Definition RNG Error Definition
+ * @{
+ */
+#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
+#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
+#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
@@ -137,7 +173,6 @@ typedef struct
*/
/* Exported macros -----------------------------------------------------------*/
-
/** @defgroup RNG_Exported_Macros RNG Exported Macros
* @{
*/
@@ -146,7 +181,15 @@ typedef struct
* @param __HANDLE__ RNG Handle
* @retval None
*/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_RNG_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @brief Enables the RNG peripheral.
@@ -167,9 +210,9 @@ typedef struct
* @param __HANDLE__ RNG Handle
* @param __FLAG__ RNG flag
* This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready
- * @arg RNG_FLAG_CECS: Clock error current status
- * @arg RNG_FLAG_SECS: Seed error current status
+ * @arg RNG_FLAG_DRDY: Data ready
+ * @arg RNG_FLAG_CECS: Clock error current status
+ * @arg RNG_FLAG_SECS: Seed error current status
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
@@ -184,8 +227,6 @@ typedef struct
*/
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
-
-
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__ RNG Handle
@@ -233,14 +274,23 @@ typedef struct
* @{
*/
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -250,14 +300,13 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
/**
* @}
@@ -267,7 +316,7 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
/**
* @}
*/
@@ -276,42 +325,6 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup RNG_Private_Macros RNG Private Macros
* @{
@@ -320,48 +333,28 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
/**
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
- * @{
- */
-
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
- * @{
- */
+#endif /* RNG */
/**
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
- STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_RNG_H */
+#endif /* STM32F4xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc.h
index aa6d17b7c38b73cd1de1e8b3e0588e9c1221e057..f5fcfdc6a80782bf0ca28f11ff448a4a5a0dc646 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -175,7 +159,11 @@ typedef struct
/**
* @brief RTC Handle Structure definition
*/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -185,8 +173,49 @@ typedef struct
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
+
+ void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
+
+ void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
+
+ void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
+
+ void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
+
+ void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
+
+ void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
+
+ void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
}RTC_HandleTypeDef;
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RTC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
+ HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
+}HAL_RTC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RTC Callback pointer definition
+ */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -425,7 +454,15 @@ typedef struct
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0u)
+#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
@@ -646,6 +683,12 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc_ex.h
index 99b53d3fc86469a6242d1f0846efa7d88193332f..8312c23cd0001c6e00483c392e440f76215f5237 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_rtc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai.h
index 5b4d75aa37b8ada80fc2e586e7f9a80bd9a38b0e..16cbccfae756e80fb7ed83db57e9d95597e21d91 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -200,7 +184,6 @@ typedef struct
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ref SAI_Block_Slot_Active */
}SAI_SlotInitTypeDef;
-
/**
* @}
*/
@@ -237,18 +220,48 @@ typedef struct __SAI_HandleTypeDef
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
- __IO uint32_t ErrorCode; /*!< SAI Error code */
-}SAI_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
+
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
+ void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
+ void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
+ void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
+ void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
+ void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
+ void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+} SAI_HandleTypeDef;
/**
* @}
*/
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief SAI callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
+ HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
+ HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
+ HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
+ HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
+ HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
+ HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
+} HAL_SAI_CallbackIDTypeDef;
+
+/**
+ * @brief SAI callback pointer definition
+ */
+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup SAI_Exported_Constants SAI Exported Constants
* @{
*/
@@ -265,6 +278,9 @@ typedef struct __SAI_HandleTypeDef
#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -559,17 +575,24 @@ typedef struct __SAI_HandleTypeDef
*/
/* Exported macro ------------------------------------------------------------*/
-
/** @defgroup SAI_Exported_Macros SAI Exported Macros
- * @brief macros to handle interrupts and specific configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific configurations
+ * @{
+ */
/** @brief Reset SAI handle state
* @param __HANDLE__ specifies the SAI Handle.
- * @retval NoneS
+ * @retval None
*/
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SAI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/** @brief Enable or disable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
@@ -645,15 +668,14 @@ typedef struct __SAI_HandleTypeDef
*/
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
- /**
+/**
* @}
*/
-/* Include RCC SAI Extension module */
+/* Include HAL SAI Extension module */
#include "stm32f4xx_hal_sai_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup SAI_Exported_Functions
* @{
*/
@@ -664,10 +686,18 @@ typedef struct __SAI_HandleTypeDef
*/
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
-HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/* SAI callbacks register/unregister functions ********************************/
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -831,7 +861,6 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
-
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai_ex.h
index 47820e562cd65b34c43b1eecba46852b6b76046d..4739537346d80f51f2f9e63aba7b50c0c8947fe1 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sai_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sd.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sd.h
index fe4651a13aae413a106694f64f55018861ac7c69..89731b79cf79fc8f96371446d547d922d35918d8 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sd.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sd.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -133,7 +117,7 @@ typedef struct
/**
* @brief SD handle Structure definition
*/
-typedef struct
+typedef struct __SD_HandleTypeDef
{
SD_TypeDef *Instance; /*!< SD registers base address */
@@ -165,6 +149,15 @@ typedef struct
uint32_t CID[4]; /*!< SD card identification number table */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
+
+ void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
+ void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
+#endif
}SD_HandleTypeDef;
/**
@@ -261,6 +254,32 @@ typedef struct
* @}
*/
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
+ HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
+ HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
+ HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
+
+ HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
+ HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
+}HAL_SD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
+ * @{
+ */
+typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+#endif
/**
* @}
*/
@@ -312,6 +331,10 @@ typedef struct
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
+#endif
+
/**
* @}
*/
@@ -360,6 +383,19 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+/** @brief Reset SD handle state.
+ * @param __HANDLE__ : SD handle.
+ * @retval None
+ */
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif
/**
* @brief Enable the SD device.
@@ -590,6 +626,12 @@ void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sdram.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sdram.h
index 9816570920969196e8890bac36476d4a016a1965..1ab41a0924c411c0c92fe7577feb1caa22e3fe58 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sdram.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sdram.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -72,12 +56,16 @@ typedef enum
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
-}HAL_SDRAM_StateTypeDef;
+} HAL_SDRAM_StateTypeDef;
/**
* @brief SDRAM handle Structure definition
*/
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SDRAM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
{
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
@@ -89,7 +77,34 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-}SDRAM_HandleTypeDef;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */
+ void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */
+ void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */
+ void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */
+#endif
+} SDRAM_HandleTypeDef;
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SDRAM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */
+ HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */
+ HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */
+ HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */
+ HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */
+}HAL_SDRAM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SDRAM Callback pointer definition
+ */
+typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
+typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
@@ -104,7 +119,15 @@ typedef struct
* @param __HANDLE__ specifies the SDRAM handle.
* @retval None
*/
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+#endif
/**
* @}
*/
@@ -145,6 +168,14 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/* SDRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smartcard.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smartcard.h
index 5ede76128eaaf5ef9346bbcd59a606bf0b0575e1..d329ac85cc2ae7466dec65828151249fb6d0dfd9 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smartcard.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smartcard.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -64,8 +48,8 @@ typedef struct
{
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+ - IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref SMARTCARD_Word_Length */
@@ -73,7 +57,7 @@ typedef struct
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref SMARTCARD_Stop_Bits */
- uint32_t Parity; /*!< Specifies the parity mode.
+ uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
@@ -167,40 +151,83 @@ typedef enum
/**
* @brief SMARTCARD handle Structure definition
*/
-typedef struct
+typedef struct __SMARTCARD_HandleTypeDef
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
- uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- __IO uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
- uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- __IO uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef gState; /* SmartCard state information related to global Handle management
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
- __IO HAL_SMARTCARD_StateTypeDef RxState; /* SmartCard state information related to Rx operations.
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
- __IO uint32_t ErrorCode; /* SmartCard Error code */
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Tx Complete Callback */
+
+ void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Error Callback */
+
+ void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Receive Complete Callback */
+
+ void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp DeInit callback */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMARTCARD Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
+ HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
+ HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
+ HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
+ HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
+ HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
+
+ HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
+ HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
-}SMARTCARD_HandleTypeDef;
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Callback pointer definition
+ */
+typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc); /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
@@ -210,16 +237,19 @@ typedef struct
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
* @{
*/
+
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
- * @brief SMARTCARD Error Code
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -227,7 +257,7 @@ typedef struct
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
@@ -235,8 +265,8 @@ typedef struct
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
*/
@@ -244,8 +274,8 @@ typedef struct
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
@@ -253,9 +283,9 @@ typedef struct
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
* @{
*/
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
* @}
*/
@@ -263,8 +293,8 @@ typedef struct
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
-#define SMARTCARD_POLARITY_LOW 0x00000000U
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define SMARTCARD_POLARITY_LOW 0x00000000U
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
@@ -272,8 +302,8 @@ typedef struct
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_PHASE_1EDGE 0x00000000U
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define SMARTCARD_PHASE_1EDGE 0x00000000U
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
*/
@@ -281,8 +311,8 @@ typedef struct
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
@@ -290,8 +320,8 @@ typedef struct
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
* @{
*/
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE 0x00000000U
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE 0x00000000U
/**
* @}
*/
@@ -299,8 +329,8 @@ typedef struct
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
* @{
*/
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
/**
* @}
*/
@@ -308,37 +338,37 @@ typedef struct
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
/**
* @}
*/
@@ -348,32 +378,32 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define SMARTCARD_FLAG_TXE 0x00000080U
-#define SMARTCARD_FLAG_TC 0x00000040U
-#define SMARTCARD_FLAG_RXNE 0x00000020U
-#define SMARTCARD_FLAG_IDLE 0x00000010U
-#define SMARTCARD_FLAG_ORE 0x00000008U
-#define SMARTCARD_FLAG_NE 0x00000004U
-#define SMARTCARD_FLAG_FE 0x00000002U
-#define SMARTCARD_FLAG_PE 0x00000001U
+#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
+#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
+#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
+ * - XXXX : Interrupt mask in the Y register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
- * - 10: CR3 register
+ * - 11: CR3 register
* @{
*/
-#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -389,20 +419,33 @@ typedef struct
/** @brief Reset SMARTCARD handle gstate & RxState
* @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/** @brief Flushs the Smartcard DR register
+/** @brief Flush the Smartcard DR register
* @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-/** @brief Checks whether the specified Smartcard flag is set or not.
+/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
@@ -417,8 +460,9 @@ typedef struct
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-/** @brief Clears the specified Smartcard pending flags.
+/** @brief Clear the specified Smartcard pending flags.
* @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
@@ -431,58 +475,55 @@ typedef struct
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
+ * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * SMARTCARD peripheral.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * SMARTCARD peripheral.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * SMARTCARD peripheral.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * SMARTCARD peripheral.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * SMARTCARD peripheral.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enables or disables the specified SmartCard interrupts.
+/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
@@ -490,10 +531,25 @@ typedef struct
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+
+/** @brief Disable the specified SmartCard interrupt.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
@@ -508,7 +564,7 @@ typedef struct
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
/** @brief Macro to enable the SMARTCARD's one bit sample method
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -536,14 +592,24 @@ typedef struct
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/** @brief Macros to enable or disable the SmartCard DMA request.
+/** @brief Macros to enable the SmartCard DMA request.
* @param __HANDLE__ specifies the SmartCard Handle.
* @param __REQUEST__ specifies the SmartCard DMA request.
* This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ * @retval None
*/
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
+
+/** @brief Macros to disable the SmartCard DMA request.
+ * @param __HANDLE__ specifies the SmartCard Handle.
+ * @param __REQUEST__ specifies the SmartCard DMA request.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+ * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+ * @retval None
+ */
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
/**
@@ -564,6 +630,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -603,7 +674,6 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-
/**
* @}
*/
@@ -621,20 +691,11 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/** @brief SMARTCARD interruptions flag mask
*
*/
-#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR3_EIE )
-
-#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
-#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* SMARTCARD BRR = mantissa + overflow + fraction
- = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
-#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+ USART_CR1_IDLEIE | USART_CR3_EIE )
-#define SMARTCARD_CR1_REG_INDEX 1U
-#define SMARTCARD_CR3_REG_INDEX 3U
+#define SMARTCARD_CR1_REG_INDEX 1U
+#define SMARTCARD_CR3_REG_INDEX 3U
/**
* @}
*/
@@ -643,19 +704,29 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
- ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+
+#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
+#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
+#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
+/* SMARTCARD BRR = mantissa + overflow + fraction
+ = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
+#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
+ (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
+ (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
+
/**
* @}
*/
@@ -676,6 +747,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smbus.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smbus.h
new file mode 100644
index 0000000000000000000000000000000000000000..0c80fd3ac20548bb7ff31d52e06e917f798b5e05
--- /dev/null
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_smbus.h
@@ -0,0 +1,733 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smbus.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_SMBUS_H
+#define __STM32F4xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMBUS Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 100kHz */
+
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is
+ selected. This parameter can be a 7-bit address. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+} SMBUS_InitTypeDef;
+
+/**
+ * @brief HAL State structure definition
+ * @note HAL SMBUS State value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : Abort (Abort user request on going)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized and ready to use. HAL SMBUS Init function called)
+ * b4 (not used)
+ * x : Should be set to 0
+ * b3
+ * 0 : Ready or Busy (No Listen mode ongoing)
+ * 1 : Listen (IP in Address Listen Mode)
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ */
+typedef enum
+{
+
+ HAL_SMBUS_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_SMBUS_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_SMBUS_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_SMBUS_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_SMBUS_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_SMBUS_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_SMBUS_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_SMBUS_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_SMBUS_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_SMBUS_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_SMBUS_STATE_ERROR = 0xE0U /*!< Error */
+} HAL_SMBUS_StateTypeDef;
+
+/**
+ * @brief HAL Mode structure definition
+ * @note HAL SMBUS Mode value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6 (not used)
+ * x : Should be set to 0
+ * b5
+ * 0 : None
+ * 1 : Slave (HAL SMBUS communication is in Slave/Device Mode)
+ * b4
+ * 0 : None
+ * 1 : Master (HAL SMBUS communication is in Master/Host Mode)
+ * b3-b2-b1-b0 (not used)
+ * xxxx : Should be set to 0000
+ */
+typedef enum
+{
+ HAL_SMBUS_MODE_NONE = 0x00U, /*!< No SMBUS communication on going */
+ HAL_SMBUS_MODE_MASTER = 0x10U, /*!< SMBUS communication is in Master Mode */
+ HAL_SMBUS_MODE_SLAVE = 0x20U, /*!< SMBUS communication is in Slave Mode */
+
+} HAL_SMBUS_ModeTypeDef;
+
+/**
+ * @brief SMBUS handle Structure definition
+ */
+typedef struct __SMBUS_HandleTypeDef
+{
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options this parameter can
+ be a value of @ref SMBUS_OPTIONS */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state and mode
+ context for internal usage */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */
+
+ __IO HAL_SMBUS_ModeTypeDef Mode; /*!< SMBUS communication mode */
+
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
+
+ __IO uint32_t Devaddress; /*!< SMBUS Target device address */
+
+ __IO uint32_t EventCount; /*!< SMBUS Event counter */
+
+ uint8_t XferPEC; /*!< SMBUS PEC data in reception mode */
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+ void (* AbortCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Abort callback */
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+} SMBUS_HandleTypeDef;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
+ HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
+ HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
+ HAL_SMBUS_ERROR_CB_ID = 0x07U, /*!< SMBUS Error callback ID */
+ HAL_SMBUS_ABORT_CB_ID = 0x08U, /*!< SMBUS Abort callback ID */
+ HAL_SMBUS_MSPINIT_CB_ID = 0x09U, /*!< SMBUS Msp Init callback ID */
+ HAL_SMBUS_MSPDEINIT_CB_ID = 0x0AU /*!< SMBUS Msp DeInit callback ID */
+
+} HAL_SMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMBUS Callback pointer definition
+ */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an I2C callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code
+ * @brief SMBUS Error Code
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SMBUS_ERROR_BERR 0x00000001U /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO 0x00000002U /*!< ARLO error */
+#define HAL_SMBUS_ERROR_AF 0x00000004U /*!< AF error */
+#define HAL_SMBUS_ERROR_OVR 0x00000008U /*!< OVR error */
+#define HAL_SMBUS_ERROR_TIMEOUT 0x00000010U /*!< Timeout Error */
+#define HAL_SMBUS_ERROR_ALERT 0x00000020U /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR 0x00000040U /*!< PEC error */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid Callback error */
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+ * @{
+ */
+#define SMBUS_ANALOGFILTER_ENABLE 0x00000000U
+#define SMBUS_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+ * @{
+ */
+#define SMBUS_ADDRESSINGMODE_7BIT 0x00004000U
+#define SMBUS_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLE 0x00000000U
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+ * @{
+ */
+#define SMBUS_GENERALCALL_DISABLE 0x00000000U
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_ENGC
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+ * @{
+ */
+#define SMBUS_NOSTRETCH_DISABLE 0x00000000U
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+ * @{
+ */
+#define SMBUS_PEC_DISABLE 0x00000000U
+#define SMBUS_PEC_ENABLE I2C_CR1_ENPEC
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+* @{
+*/
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE I2C_CR1_SMBUS
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)
+/**
+* @}
+*/
+
+/** @defgroup SMBUS_XferDirection_definition SMBUS XferDirection definition
+ * @{
+ */
+#define SMBUS_DIRECTION_RECEIVE 0x00000000U
+#define SMBUS_DIRECTION_TRANSMIT 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+ * @{
+ */
+#define SMBUS_FIRST_FRAME 0x00000001U
+#define SMBUS_NEXT_FRAME 0x00000002U
+#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC 0x00000003U
+#define SMBUS_LAST_FRAME_NO_PEC 0x00000004U
+#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC 0x00000005U
+#define SMBUS_LAST_FRAME_WITH_PEC 0x00000006U
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+ * @{
+ */
+#define SMBUS_IT_BUF I2C_CR2_ITBUFEN
+#define SMBUS_IT_EVT I2C_CR2_ITEVTEN
+#define SMBUS_IT_ERR I2C_CR2_ITERREN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+ * @{
+ */
+#define SMBUS_FLAG_SMBALERT 0x00018000U
+#define SMBUS_FLAG_TIMEOUT 0x00014000U
+#define SMBUS_FLAG_PECERR 0x00011000U
+#define SMBUS_FLAG_OVR 0x00010800U
+#define SMBUS_FLAG_AF 0x00010400U
+#define SMBUS_FLAG_ARLO 0x00010200U
+#define SMBUS_FLAG_BERR 0x00010100U
+#define SMBUS_FLAG_TXE 0x00010080U
+#define SMBUS_FLAG_RXNE 0x00010040U
+#define SMBUS_FLAG_STOPF 0x00010010U
+#define SMBUS_FLAG_ADD10 0x00010008U
+#define SMBUS_FLAG_BTF 0x00010004U
+#define SMBUS_FLAG_ADDR 0x00010002U
+#define SMBUS_FLAG_SB 0x00010001U
+#define SMBUS_FLAG_DUALF 0x00100080U
+#define SMBUS_FLAG_SMBHOST 0x00100040U
+#define SMBUS_FLAG_SMBDEFAULT 0x00100020U
+#define SMBUS_FLAG_GENCALL 0x00100010U
+#define SMBUS_FLAG_TRA 0x00100004U
+#define SMBUS_FLAG_BUSY 0x00100002U
+#define SMBUS_FLAG_MSL 0x00100001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMBUS handle state
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @retval None
+ */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#endif
+
+/** @brief Enable or disable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_IT_BUF: Buffer interrupt enable
+ * @arg SMBUS_IT_EVT: Event interrupt enable
+ * @arg SMBUS_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_IT_BUF: Buffer interrupt enable
+ * @arg SMBUS_IT_EVT: Event interrupt enable
+ * @arg SMBUS_IT_ERR: Error interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified SMBUS flag is set or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_FLAG_SMBALERT: SMBus Alert flag
+ * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg SMBUS_FLAG_PECERR: PEC error in reception flag
+ * @arg SMBUS_FLAG_OVR: Overrun/Underrun flag
+ * @arg SMBUS_FLAG_AF: Acknowledge failure flag
+ * @arg SMBUS_FLAG_ARLO: Arbitration lost flag
+ * @arg SMBUS_FLAG_BERR: Bus error flag
+ * @arg SMBUS_FLAG_TXE: Data register empty flag
+ * @arg SMBUS_FLAG_RXNE: Data register not empty flag
+ * @arg SMBUS_FLAG_STOPF: Stop detection flag
+ * @arg SMBUS_FLAG_ADD10: 10-bit header sent flag
+ * @arg SMBUS_FLAG_BTF: Byte transfer finished flag
+ * @arg SMBUS_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg SMBUS_FLAG_SB: Start bit flag
+ * @arg SMBUS_FLAG_DUALF: Dual flag
+ * @arg SMBUS_FLAG_SMBHOST: SMBus host header
+ * @arg SMBUS_FLAG_SMBDEFAULT: SMBus default header
+ * @arg SMBUS_FLAG_GENCALL: General call header flag
+ * @arg SMBUS_FLAG_TRA: Transmitter/Receiver flag
+ * @arg SMBUS_FLAG_BUSY: Bus busy flag
+ * @arg SMBUS_FLAG_MSL: Master/Slave flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)): \
+ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief Clears the SMBUS pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg SMBUS_FLAG_SMBALERT: SMBus Alert flag
+ * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg SMBUS_FLAG_PECERR: PEC error in reception flag
+ * @arg SMBUS_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg SMBUS_FLAG_AF: Acknowledge failure flag
+ * @arg SMBUS_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg SMBUS_FLAG_BERR: Bus error flag
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & SMBUS_FLAG_MASK))
+
+/** @brief Clears the SMBUS ADDR pending flag.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clears the SMBUS STOPF pending flag.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUS where x: 1, 2, or 3 to select the SMBUS peripheral.
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Enable the SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
+
+/** @brief Disable the SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral.
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+
+/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_ACK))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+
+/* Callbacks Register/UnRegister functions ************************************/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+
+/****** Filter Configuration functions */
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+#endif
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State, mode and Errors functions **************************************************/
+HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+HAL_SMBUS_ModeTypeDef HAL_SMBUS_GetMode(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Constants SMBUS Private Constants
+ * @{
+ */
+#define SMBUS_FLAG_MASK 0x0000FFFFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macros SMBUS Private Macros
+ * @{
+ */
+
+#define SMBUS_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
+
+#define SMBUS_RISE_TIME(__FREQRANGE__) ( ((__FREQRANGE__) + 1U))
+
+#define SMBUS_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+
+#define SMBUS_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+
+#define SMBUS_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define SMBUS_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+#define SMBUS_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+
+#define SMBUS_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+
+#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ENPEC)
+
+#define SMBUS_GET_PEC_VALUE(__HANDLE__) ((__HANDLE__)->XferPEC)
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+#endif
+#define IS_SMBUS_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == SMBUS_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 100000U))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
+
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+* @}
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spdifrx.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spdifrx.h
index db8f522ef5be933e66ab571a0b21642c9ccab1a8..73e30d22835a965de2422f1fbc00ead06e2759f0 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spdifrx.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spdifrx.h
@@ -6,49 +6,33 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SPDIFRX_H
-#define __STM32F4xx_HAL_SPDIFRX_H
+#ifndef STM32F4xx_HAL_SPDIFRX_H
+#define STM32F4xx_HAL_SPDIFRX_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F446xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(STM32F446xx)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#if defined (SPDIFRX)
/** @addtogroup SPDIFRX
* @{
@@ -82,18 +66,18 @@ typedef struct
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
- uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_V_Mask */
+ uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PE_Mask */
-}SPDIFRX_InitTypeDef;
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
+} SPDIFRX_InitTypeDef;
/**
* @brief SPDIFRX SetDataFormat structure definition
@@ -117,7 +101,8 @@ typedef struct
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
-}SPDIFRX_SetDataFormatTypeDef;
+
+} SPDIFRX_SetDataFormatTypeDef;
/**
* @brief HAL State structures definition
@@ -130,12 +115,16 @@ typedef enum
HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
-}HAL_SPDIFRX_StateTypeDef;
+} HAL_SPDIFRX_StateTypeDef;
/**
* @brief SPDIFRX handle Structure definition
*/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+typedef struct __SPDIFRX_HandleTypeDef
+#else
typedef struct
+#endif
{
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
@@ -143,7 +132,7 @@ typedef struct
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
- uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
+ uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
@@ -171,12 +160,44 @@ typedef struct
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
- __IO uint32_t ErrorCode; /* SPDIFRX Error code */
-}SPDIFRX_HandleTypeDef;
+ __IO uint32_t ErrorCode; /* SPDIFRX Error code */
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
+ void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
+ void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
+ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
+ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
+ void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */
+ void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+} SPDIFRX_HandleTypeDef;
/**
* @}
*/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SPDIFRX Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, /*!< SPDIFRX Data flow half completed callback ID */
+ HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, /*!< SPDIFRX Data flow completed callback */
+ HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, /*!< SPDIFRX Control flow half completed callback */
+ HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U, /*!< SPDIFRX Control flow completed callback */
+ HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */
+ HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */
+ HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */
+}HAL_SPDIFRX_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPDIFRX Callback pointer definition
+ */
+typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
@@ -184,12 +205,15 @@ typedef struct
/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
* @{
*/
-#define HAL_SPDIFRX_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SPDIFRX_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_SPDIFRX_ERROR_OVR 0x00000002U /*!< OVR error */
-#define HAL_SPDIFRX_ERROR_PE 0x00000004U /*!< Parity error */
-#define HAL_SPDIFRX_ERROR_DMA 0x00000008U /*!< DMA transfer error */
-#define HAL_SPDIFRX_ERROR_UNKNOWN 0x00000010U /*!< Unknown Error error */
+#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
+#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
+#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */
+#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
+#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -197,10 +221,10 @@ typedef struct
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
* @{
*/
-#define SPDIFRX_INPUT_IN0 0x00000000U
-#define SPDIFRX_INPUT_IN1 0x00010000U
-#define SPDIFRX_INPUT_IN2 0x00020000U
-#define SPDIFRX_INPUT_IN3 0x00030000U
+#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
+#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
+#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
+#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
/**
* @}
*/
@@ -208,10 +232,10 @@ typedef struct
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
* @{
*/
-#define SPDIFRX_MAXRETRIES_NONE 0x00000000U
-#define SPDIFRX_MAXRETRIES_3 0x00001000U
-#define SPDIFRX_MAXRETRIES_15 0x00002000U
-#define SPDIFRX_MAXRETRIES_63 0x00003000U
+#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
+#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
+#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
+#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
/**
* @}
*/
@@ -219,26 +243,26 @@ typedef struct
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
* @{
*/
-#define SPDIFRX_WAITFORACTIVITY_OFF 0x00000000U
-#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
+#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
/**
* @}
*/
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
-* @{
-*/
-#define SPDIFRX_PREAMBLETYPEMASK_OFF 0x00000000U
-#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
+ * @{
+ */
+#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
-* @{
-*/
-#define SPDIFRX_CHANNELSTATUS_OFF 0x00000000U /* The channel status and user bits are copied into the SPDIF_DR */
-#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+ * @{
+ */
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/
@@ -246,17 +270,17 @@ typedef struct
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
* @{
*/
-#define SPDIFRX_VALIDITYMASK_OFF 0x00000000U
-#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
+#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
-* @{
-*/
-#define SPDIFRX_PARITYERRORMASK_OFF 0x00000000U
-#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
+ * @{
+ */
+#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
+#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
/**
* @}
*/
@@ -264,8 +288,8 @@ typedef struct
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
* @{
*/
-#define SPDIFRX_CHANNEL_A 0x00000000U
-#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
+#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
+#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
/**
* @}
*/
@@ -273,9 +297,9 @@ typedef struct
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
* @{
*/
-#define SPDIFRX_DATAFORMAT_LSB 0x00000000U
-#define SPDIFRX_DATAFORMAT_MSB 0x00000010U
-#define SPDIFRX_DATAFORMAT_32BITS 0x00000020U
+#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
+#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
+#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
/**
* @}
*/
@@ -283,8 +307,8 @@ typedef struct
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
* @{
*/
-#define SPDIFRX_STEREOMODE_DISABLE 0x00000000U
-#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
+#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
+#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
/**
* @}
*/
@@ -293,8 +317,8 @@ typedef struct
* @{
*/
-#define SPDIFRX_STATE_IDLE 0xFFFFFFFCU
-#define SPDIFRX_STATE_SYNC 0x00000001U
+#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
+#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
/**
* @}
@@ -303,13 +327,13 @@ typedef struct
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
* @{
*/
-#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
-#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
-#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
-#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
-#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
-#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
-#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
+#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
+#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
+#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
+#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
+#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
+#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
+#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
/**
* @}
*/
@@ -317,15 +341,15 @@ typedef struct
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
* @{
*/
-#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
-#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
-#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
-#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
-#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
-#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
-#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
-#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
-#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
+#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
+#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
+#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
+#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
+#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
+#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
+#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
+#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
+#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
/**
* @}
*/
@@ -343,7 +367,15 @@ typedef struct
* @param __HANDLE__ SPDIFRX handle.
* @retval None
*/
-#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
+#else
+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
* @param __HANDLE__ specifies the SPDIFRX Handle.
@@ -364,8 +396,9 @@ typedef struct
*/
#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
+
/** @brief Enable or disable the specified SPDIFRX interrupts.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
@@ -381,7 +414,7 @@ typedef struct
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
* @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
@@ -396,8 +429,8 @@ typedef struct
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPDIFRX flag is set or not.
- * @param __HANDLE__ specifies the SPDIFRX Handle.
- * @param __FLAG__ specifies the flag to check.
+ * @param __HANDLE__ specifies the SPDIFRX Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_RXNE
* @arg SPDIFRX_FLAG_CSRNE
@@ -410,11 +443,11 @@ typedef struct
* @arg SPDIFRX_FLAG_TERR
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
- * @param __HANDLE__ specifies the USART Handle.
- * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_PERR
@@ -443,6 +476,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -455,7 +494,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
@@ -463,7 +502,6 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
-
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
@@ -480,8 +518,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
* @{
*/
/* Peripheral Control and State functions ************************************/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
/**
* @}
*/
@@ -496,32 +534,41 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
* @{
*/
-#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
- ((INPUT) == SPDIFRX_INPUT_IN2) || \
- ((INPUT) == SPDIFRX_INPUT_IN3) || \
- ((INPUT) == SPDIFRX_INPUT_IN0))
-#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
- ((RET) == SPDIFRX_MAXRETRIES_3) || \
- ((RET) == SPDIFRX_MAXRETRIES_15) || \
- ((RET) == SPDIFRX_MAXRETRIES_63))
-#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
- ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
-#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
- ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
+
+#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
+
+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+
+#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
- ((VAL) == SPDIFRX_VALIDITYMASK_ON))
-#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
- ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
-#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
- ((CHANNEL) == SPDIFRX_CHANNEL_B))
-#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
-#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
- ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
-
-#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
- ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+
+#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+
+#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
+
+#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+
+#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+
+#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+
/**
* @}
*/
@@ -537,7 +584,7 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
-
+#endif /* SPDIFRX */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spi.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spi.h
index 933f409995baefd05bbe5adae118bd84f600ea2f..c220b217484267ea44473325e9d39536b8cdfd36 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spi.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_spi.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SPI_H
-#define __STM32F4xx_HAL_SPI_H
+#ifndef STM32F4xx_HAL_SPI_H
+#define STM32F4xx_HAL_SPI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -62,43 +46,43 @@
*/
typedef struct
{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
- uint32_t DataSize; /*!< Specifies the SPI data size.
+ uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_mode */
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-}SPI_InitTypeDef;
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
+} SPI_InitTypeDef;
/**
* @brief HAL SPI State structure definition
@@ -111,46 +95,85 @@ typedef enum
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
-}HAL_SPI_StateTypeDef;
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
- SPI_TypeDef *Instance; /* SPI registers base address */
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
- SPI_InitTypeDef Init; /* SPI communication parameters */
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
- uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
- uint16_t TxXferSize; /* SPI Tx Transfer size */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
- __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
- uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
- uint16_t RxXferSize; /* SPI Rx Transfer size */
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
- __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
- void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
- void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
- DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
- HAL_LockTypeDef Lock; /* Locking object */
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
- __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
- __IO uint32_t ErrorCode; /* SPI Error code */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
-}SPI_HandleTypeDef;
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -163,13 +186,17 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
-#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
-#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
-#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
-#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
-#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
+#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -177,7 +204,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Mode SPI Mode
* @{
*/
-#define SPI_MODE_SLAVE 0x00000000U
+#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
@@ -186,7 +213,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
-#define SPI_DIRECTION_2LINES 0x00000000U
+#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
@@ -196,7 +223,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_8BIT 0x00000000U
+#define SPI_DATASIZE_8BIT (0x00000000U)
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
/**
* @}
@@ -205,7 +232,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
-#define SPI_POLARITY_LOW 0x00000000U
+#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
@@ -214,7 +241,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
-#define SPI_PHASE_1EDGE 0x00000000U
+#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
@@ -224,8 +251,8 @@ typedef struct __SPI_HandleTypeDef
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT 0x00000000U
-#define SPI_NSS_HARD_OUTPUT 0x00040000U
+#define SPI_NSS_HARD_INPUT (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
@@ -233,14 +260,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
-#define SPI_BAUDRATEPRESCALER_2 0x00000000U
-#define SPI_BAUDRATEPRESCALER_4 0x00000008U
-#define SPI_BAUDRATEPRESCALER_8 0x00000010U
-#define SPI_BAUDRATEPRESCALER_16 0x00000018U
-#define SPI_BAUDRATEPRESCALER_32 0x00000020U
-#define SPI_BAUDRATEPRESCALER_64 0x00000028U
-#define SPI_BAUDRATEPRESCALER_128 0x00000030U
-#define SPI_BAUDRATEPRESCALER_256 0x00000038U
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
@@ -248,7 +275,7 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
-#define SPI_FIRSTBIT_MSB 0x00000000U
+#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
@@ -257,8 +284,8 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLE 0x00000000U
-#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+#define SPI_TIMODE_DISABLE (0x00000000U)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
@@ -266,8 +293,8 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLE 0x00000000U
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
@@ -285,13 +312,14 @@ typedef struct __SPI_HandleTypeDef
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
/**
* @}
*/
@@ -300,7 +328,7 @@ typedef struct __SPI_HandleTypeDef
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
@@ -310,29 +338,48 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif
-/** @brief Enable or disable the specified SPI interrupts.
+/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__ specifies the SPI handle.
+ * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@@ -365,12 +412,12 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
} while(0U)
/** @brief Clear the SPI OVR pending flag.
@@ -403,14 +450,186 @@ typedef struct __SPI_HandleTypeDef
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__ specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of SPI SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of SPI CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if SPI Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Mode.
+ * This parameter can be a value of @ref SPI_Mode
+ * @retval None
+ */
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+ ((__MODE__) == SPI_MODE_MASTER))
+
+/** @brief Checks if SPI Direction Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * This parameter can be a value of @ref SPI_Direction
+ * @retval None
+ */
+#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Direction Mode parameter is 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
+
+/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief Checks if SPI Data Size parameter is in allowed range.
+ * @param __DATASIZE__ specifies the SPI Data Size.
+ * This parameter can be a value of @ref SPI_Data_Size
+ * @retval None
+ */
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_8BIT))
+
+/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the SPI serial clock steady state.
+ * This parameter can be a value of @ref SPI_Clock_Polarity
+ * @retval None
+ */
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
+
+/** @brief Checks if SPI Clock Phase parameter is in allowed range.
+ * @param __CPHA__ specifies the SPI Clock Phase.
+ * This parameter can be a value of @ref SPI_Clock_Phase
+ * @retval None
+ */
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
+
+/** @brief Checks if SPI Slave Select parameter is in allowed range.
+ * @param __NSS__ specifies the SPI Slave Select management parameter.
+ * This parameter can be a value of @ref SPI_Slave_Select_management
+ * @retval None
+ */
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+
+/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
+ * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
+ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ * @retval None
+ */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
+
+/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
+ * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
+ * This parameter can be a value of @ref SPI_MSB_LSB_transmission
+ * @retval None
+ */
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
+
+/** @brief Checks if SPI TI mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI TI mode.
+ * This parameter can be a value of @ref SPI_TI_mode
+ * @retval None
+ */
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+ ((__MODE__) == SPI_TIMODE_ENABLE))
+
+/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
+ * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
+ * This parameter can be a value of @ref SPI_CRC_Calculation
+ * @retval None
+ */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
+
+/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
+ * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
+ * @retval None
+ */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
+
+/** @brief Checks if DMA handle is valid.
+ * @param __HANDLE__ specifies a DMA Handle.
+ * @retval None
+ */
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
+
/**
* @}
*/
@@ -423,11 +642,17 @@ typedef struct __SPI_HandleTypeDef
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -435,16 +660,19 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
-/* I/O operation functions *****************************************************/
+/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
@@ -479,95 +707,6 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
* @}
*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
- ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
/**
* @}
*/
@@ -580,6 +719,6 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
}
#endif
-#endif /* __STM32F4xx_HAL_SPI_H */
+#endif /* STM32F4xx_HAL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sram.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sram.h
index 1e5b7d50fa0737d596c1fc30e487f1213f4c9d35..3752bc43bc2a233314d43ff2ac8c2fcbc28f85f0 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sram.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_sram.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -82,12 +66,16 @@ typedef enum
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
-}HAL_SRAM_StateTypeDef;
+} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -101,8 +89,32 @@ typedef struct
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-}SRAM_HandleTypeDef;
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
+#endif
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SRAM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
+ HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
+ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
+ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
+}HAL_SRAM_CallbackIDTypeDef;
+/**
+ * @brief HAL SRAM Callback pointer definition
+ */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
@@ -117,7 +129,15 @@ typedef struct
* @param __HANDLE__ SRAM handle
* @retval None
*/
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif
/**
* @}
@@ -155,6 +175,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim.h
index 013df81c84f4d492be1aa3bed846c5908df47158..92ed5ba0b13ea38e3136229412ea6a39cefcff00 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_TIM_H
-#define __STM32F4xx_HAL_TIM_H
+#ifndef STM32F4xx_HAL_TIM_H
+#define STM32F4xx_HAL_TIM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -63,14 +47,14 @@
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
@@ -81,41 +65,43 @@ typedef struct
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
* @brief TIM Output Compare Configuration Structure definition
*/
-
typedef struct
{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;
/**
@@ -127,22 +113,22 @@ typedef struct
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -154,15 +140,13 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;
-
/**
* @brief TIM Input Capture Configuration Structure definition
*/
-
typedef struct
{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -177,7 +161,6 @@ typedef struct
/**
* @brief TIM Encoder Configuration Structure definition
*/
-
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
@@ -213,49 +196,86 @@ typedef struct
*/
typedef struct
{
- uint32_t ClockSource; /*!< TIM clock sources.
+ uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity.
+ uint32_t ClockPolarity; /*!< TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler.
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
/**
- * @brief Clear Input Configuration Handle Structure definition
+ * @brief TIM Clear Input Configuration Handle Structure definition
*/
typedef struct
{
- uint32_t ClearInputState; /*!< TIM clear Input state.
+ uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources.
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+} TIM_MasterConfigTypeDef;
/**
* @brief TIM Slave configuration Structure definition
*/
-typedef struct {
+typedef struct
+{
uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
+ This parameter can be a value of @ref TIM_Slave_Mode */
uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
+ This parameter can be a value of @ref TIM_Trigger_Selection */
uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_SlaveConfigTypeDef;
+} TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the break input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
/**
* @brief HAL State structures definition
@@ -267,7 +287,7 @@ typedef enum
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
+} HAL_TIM_StateTypeDef;
/**
* @brief HAL Active channel structures definition
@@ -279,337 +299,451 @@ typedef enum
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
+} HAL_TIM_ActiveChannel;
/**
* @brief TIM Time Base Handle Structure definition
*/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
+ This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
-}TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
/**
* @}
*/
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
+#define TIM_DMABASE_DMAR 0x00000013U
/**
* @}
*/
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
/**
* @}
*/
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
* @{
*/
-#define TIM_COUNTERMODE_UP 0x00000000U
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
* @}
*/
-/** @defgroup TIM_ClockDivision TIM Clock Division
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_OCMODE_TIMING 0x00000000U
-#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
-
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
/**
* @}
*/
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_OCFAST_DISABLE 0x00000000U
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
-#define TIM_OCPOLARITY_HIGH 0x00000000U
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
-#define TIM_OCNPOLARITY_HIGH 0x00000000U
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET 0x00000000U
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
+
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET 0x00000000U
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
/**
* @}
*/
-/** @defgroup TIM_Channel TIM Channel
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
-#define TIM_CHANNEL_1 0x00000000U
-#define TIM_CHANNEL_2 0x00000004U
-#define TIM_CHANNEL_3 0x00000008U
-#define TIM_CHANNEL_4 0x0000000CU
-#define TIM_CHANNEL_ALL 0x00000018U
-
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
/**
* @}
*/
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
/**
* @}
*/
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE 0x00000000U
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
/**
* @}
*/
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
/**
* @}
*/
-/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
/**
* @}
*/
-/** @defgroup TIM_DMA_sources TIM DMA sources
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
* @{
*/
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
/**
* @}
*/
-/** @defgroup TIM_Event_Source TIM Event Source
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+ * @}
+ */
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
/**
* @}
*/
-/** @defgroup TIM_Flag_definition TIM Flag definition
+/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
/**
* @}
*/
-/** @defgroup TIM_Clock_Source TIM Clock Source
+/** @defgroup TIM_Channel TIM Channel
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 0x00000000U
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
/**
* @}
*/
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
@@ -617,10 +751,10 @@ typedef struct
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/
@@ -628,8 +762,8 @@ typedef struct
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE 0x00000000U
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
@@ -637,45 +771,46 @@ typedef struct
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE 0x00000000U
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
-
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
-#define TIM_LOCKLEVEL_OFF 0x00000000U
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
/**
* @}
*/
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
* @{
*/
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE 0x00000000U
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
/**
* @}
*/
-/** @defgroup TIM_Break_Polarity TIM Break Polarity
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
-#define TIM_BREAKPOLARITY_LOW 0x00000000U
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
* @{
*/
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+ (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
@@ -683,161 +818,148 @@ typedef struct
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET 0x00000000U
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
/**
* @}
*/
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
* @{
*/
-#define TIM_SLAVEMODE_DISABLE 0x00000000U
-#define TIM_SLAVEMODE_RESET 0x00000004U
-#define TIM_SLAVEMODE_GATED 0x00000005U
-#define TIM_SLAVEMODE_TRIGGER 0x00000006U
-#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
/**
* @}
*/
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+/** @defgroup TIM_Slave_Mode TIM Slave mode
* @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
/**
* @}
*/
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
* @{
*/
-#define TIM_TS_ITR0 0x00000000U
-#define TIM_TS_ITR1 0x00000010U
-#define TIM_TS_ITR2 0x00000020U
-#define TIM_TS_ITR3 0x00000030U
-#define TIM_TS_TI1F_ED 0x00000040U
-#define TIM_TS_TI1FP1 0x00000050U
-#define TIM_TS_TI2FP2 0x00000060U
-#define TIM_TS_ETRF 0x00000070U
-#define TIM_TS_NONE 0x0000FFFFU
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
/**
* @}
*/
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
/**
* @}
*/
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
/**
* @}
*/
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Selection
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
-#define TIM_TI1SELECTION_CH1 0x00000000U
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
* @}
*/
-/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_DCR 0x00000012U
-#define TIM_DMABASE_OR 0x00000013U
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
* @}
*/
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
-/** @defgroup DMA_Handle_index DMA Handle index
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
-/** @defgroup Channel_CC_State Channel CC State
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
-#define TIM_CCx_ENABLE 0x00000001U
-#define TIM_CCx_DISABLE 0x00000000U
-#define TIM_CCxN_ENABLE 0x00000004U
-#define TIM_CCxN_DISABLE 0x00000000U
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
/**
* @}
*/
@@ -845,22 +967,44 @@ typedef struct
/**
* @}
*/
+/* End of exported constants -------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
*/
-/** @brief Reset TIM handle state
- * @param __HANDLE__ TIM handle
+
+/** @brief Reset TIM handle state.
+ * @param __HANDLE__ TIM handle.
* @retval None
*/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
- */
+ */
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
/**
@@ -870,7 +1014,6 @@ typedef struct
*/
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
/**
* @brief Disable the TIM peripheral.
* @param __HANDLE__ TIM handle
@@ -878,32 +1021,31 @@ typedef struct
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
- } while(0U)
+ } while(0)
-/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
- } \
- } while(0U)
+ } \
+ } while(0)
/**
* @brief Disable the TIM main Output.
@@ -929,7 +1071,6 @@ typedef struct
*/
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
/** @brief Disable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
@@ -985,13 +1126,9 @@ typedef struct
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1009,13 +1146,9 @@ typedef struct
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
- * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
- * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1055,7 +1188,7 @@ typedef struct
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
@@ -1064,7 +1197,7 @@ typedef struct
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
*/
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
/**
* @brief Set the TIM Prescaler on runtime.
@@ -1074,98 +1207,44 @@ mode.
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
-/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @arg TIM_CHANNEL_5: get capture/compare 5 register value
- * @arg TIM_CHANNEL_6: get capture/compare 6 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-
/**
- * @brief Sets the TIM Counter Register value on runtime.
+ * @brief Set the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
- * @brief Gets the TIM Counter Register value on runtime.
+ * @brief Get the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
/**
- * @brief Sets the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __AUTORELOAD__ specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0U)
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
/**
- * @brief Gets the TIM Autoreload Register value on runtime.
+ * @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
/**
- * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
@@ -1175,26 +1254,27 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0U)
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
/**
- * @brief Gets the TIM Clock Division value on runtime.
+ * @brief Get the TIM Clock Division value on runtime.
* @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Sets the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
* @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1212,7 +1292,7 @@ mode.
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0U)
+ } while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@@ -1236,32 +1316,101 @@ mode.
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
* @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__HANDLE__)->Instance->CCR4))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
* overflow/underflow generates an update interrupt or DMA request (if
* enabled)
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+ ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
* @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
* following events generate an update interrupt or DMA request (if
* enabled):
- * _ Counter overflow/underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+ ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
- * @brief Sets the TIM Capture x input polarity on runtime.
+ * @brief Set the TIM Capture x input polarity on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1273,30 +1422,305 @@ mode.
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
* @retval None
*/
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0U)
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
+ ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
+ ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
+ ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
+ ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
/**
* @}
*/
+/* End of private macros -----------------------------------------------------*/
-/* Include TIM HAL Extension module */
+/* Include TIM HAL Extended module */
#include "stm32f4xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @addtogroup TIM_Exported_Functions_Group1
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
* @{
*/
-
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
@@ -1315,10 +1739,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group2
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
* @{
*/
-/* Timer Output Compare functions **********************************************/
+/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
@@ -1332,15 +1757,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group3
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
* @{
*/
-/* Timer PWM functions *********************************************************/
+/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
@@ -1354,15 +1779,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group4
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
* @{
*/
-/* Timer Input Capture functions ***********************************************/
+/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
@@ -1376,15 +1801,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group5
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
* @{
*/
-/* Timer One Pulse functions ***************************************************/
+/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
@@ -1392,24 +1817,23 @@ void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group6
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
* @{
*/
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
@@ -1418,73 +1842,83 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group7
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
* @{
*/
-/* Interrupt Handler functions **********************************************/
+/* Interrupt Handler functions ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group8
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
* @{
*/
/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group9
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
* @{
*/
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group10
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
* @{
*/
-/* Peripheral State functions **************************************************/
+/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
/**
* @}
*/
@@ -1492,267 +1926,33 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
- * @{
- */
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
- ((BASE) == TIM_DMABASE_CR2) || \
- ((BASE) == TIM_DMABASE_SMCR) || \
- ((BASE) == TIM_DMABASE_DIER) || \
- ((BASE) == TIM_DMABASE_SR) || \
- ((BASE) == TIM_DMABASE_EGR) || \
- ((BASE) == TIM_DMABASE_CCMR1) || \
- ((BASE) == TIM_DMABASE_CCMR2) || \
- ((BASE) == TIM_DMABASE_CCER) || \
- ((BASE) == TIM_DMABASE_CNT) || \
- ((BASE) == TIM_DMABASE_PSC) || \
- ((BASE) == TIM_DMABASE_ARR) || \
- ((BASE) == TIM_DMABASE_RCR) || \
- ((BASE) == TIM_DMABASE_CCR1) || \
- ((BASE) == TIM_DMABASE_CCR2) || \
- ((BASE) == TIM_DMABASE_CCR3) || \
- ((BASE) == TIM_DMABASE_CCR4) || \
- ((BASE) == TIM_DMABASE_BDTR) || \
- ((BASE) == TIM_DMABASE_DCR) || \
- ((BASE) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-/**
- * @}
- */
-
-/** @defgroup TIM_Mask_Definitions TIM Mask Definition
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
+/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
+* @{
+*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
- * @}
- */
+* @}
+*/
+/* End of private functions --------------------------------------------------*/
/**
* @}
@@ -1766,6 +1966,6 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat
}
#endif
-#endif /* __STM32F4xx_HAL_TIM_H */
+#endif /* STM32F4xx_HAL_TIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim_ex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim_ex.h
index 5ce155715a46ca7a5ed9ebbbceb3adb2205cc918..69b4ca3f594bc1dfcdb81dd04f7a0bc245d782d4 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim_ex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_tim_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
- * @brief Header file of TIM HAL Extension module.
+ * @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_TIM_EX_H
-#define __STM32F4xx_HAL_TIM_EX_H
+#ifndef STM32F4xx_HAL_TIM_EX_H
+#define STM32F4xx_HAL_TIM_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -53,7 +37,7 @@
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Exported Types
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
@@ -63,9 +47,8 @@
typedef struct
{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
@@ -73,206 +56,263 @@ typedef struct
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
-
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Break and Dead time configuration Structure definition
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level.
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-}TIM_BreakDeadTimeConfigTypeDef;
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
-/** @defgroup TIMEx_Remap TIM Remap
+/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
-#define TIM_TIM2_TIM8_TRGO 0x00000000U
-#define TIM_TIM2_ETH_PTP 0x00000400U
-#define TIM_TIM2_USBFS_SOF 0x00000800U
-#define TIM_TIM2_USBHS_SOF 0x00000C00U
-#define TIM_TIM5_GPIO 0x00000000U
-#define TIM_TIM5_LSI 0x00000040U
-#define TIM_TIM5_LSE 0x00000080U
-#define TIM_TIM5_RTC 0x000000C0U
-#define TIM_TIM11_GPIO 0x00000000U
-#define TIM_TIM11_HSE 0x00000002U
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define TIM_TIM9_TIM3_TRGO 0x10000000U
-#define TIM_TIM9_LPTIM 0x10000010U
-#define TIM_TIM5_TIM3_TRGO 0x10000000U
-#define TIM_TIM5_LPTIM 0x10000008U
-#define TIM_TIM1_TIM3_TRGO 0x10000000U
-#define TIM_TIM1_LPTIM 0x10000004U
-#endif /* STM32F413xx | STM32F423xx */
-
-#if defined (STM32F446xx)
-#define TIM_TIM11_SPDIFRX 0x00000001U
-#endif /* STM32F446xx */
+#if defined (TIM2)
+#if defined(TIM8)
+#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */
+#else
+#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */
+#endif /* TIM8 */
+#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */
+#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */
+#endif /* TIM2 */
+
+#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */
+#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */
+#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */
+#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
+
+#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */
+#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */
+#if defined(SPDIFRX)
+#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */
+#endif /* SPDIFRX*/
+
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
+#define LPTIM_REMAP_MASK 0x10000000U
+
+#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */
+#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */
+
+#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */
+#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */
+
+#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */
+#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */
+#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
+/**
+ * @}
+ */
+
/**
* @}
*/
+/* End of exported constants -------------------------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup TIMEx_SystemBreakInput TIM System Break Input
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
-#define TIM_SYSTEMBREAKINPUT_HARDFAULT 0x00000001U /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */
-#define TIM_SYSTEMBREAKINPUT_PVD 0x00000004U /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */
-#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD 0x00000005U /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */
+
/**
* @}
*/
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+#if defined(SPDIFRX)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
+#elif defined(TIM2)
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))) || \
+ (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
+ (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM9_LPTIM))))
+#elif defined(TIM8)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
+#else
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
+ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
+ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
+ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
+#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
+#else
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
+ ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM5_LSI) || \
+ ((TIM_REMAP) == TIM_TIM5_LSE) || \
+ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
+ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
+ ((TIM_REMAP) == TIM_TIM11_HSE))))
+#endif /* SPDIFRX */
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* End of private macro ------------------------------------------------------*/
+
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
-/** @addtogroup TIMEx_Exported_Functions_Group1
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
-/* Extension Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group6
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
* @{
*/
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group7
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
* @{
*/
-/* Extension Peripheral State functions **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+/* Extended Peripheral State functions ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@@ -280,76 +320,18 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Private Macros
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
-#if defined (STM32F446xx)
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM_TIM5_GPIO)||\
- ((TIM_REMAP) == TIM_TIM5_LSI)||\
- ((TIM_REMAP) == TIM_TIM5_LSE)||\
- ((TIM_REMAP) == TIM_TIM5_RTC)||\
- ((TIM_REMAP) == TIM_TIM11_GPIO)||\
- ((TIM_REMAP) == TIM_TIM11_SPDIFRX)||\
- ((TIM_REMAP) == TIM_TIM11_HSE))
-#elif defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM_TIM5_GPIO)||\
- ((TIM_REMAP) == TIM_TIM5_LSI)||\
- ((TIM_REMAP) == TIM_TIM5_LSE)||\
- ((TIM_REMAP) == TIM_TIM5_RTC)||\
- ((TIM_REMAP) == TIM_TIM11_GPIO)||\
- ((TIM_REMAP) == TIM_TIM11_HSE)||\
- ((TIM_REMAP) == TIM_TIM9_TIM3_TRGO)||\
- ((TIM_REMAP) == TIM_TIM9_LPTIM)||\
- ((TIM_REMAP) == TIM_TIM5_TIM3_TRGO)||\
- ((TIM_REMAP) == TIM_TIM5_LPTIM)||\
- ((TIM_REMAP) == TIM_TIM1_TIM3_TRGO)||\
- ((TIM_REMAP) == TIM_TIM1_LPTIM))
-#else
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
- ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
- ((TIM_REMAP) == TIM_TIM5_GPIO)||\
- ((TIM_REMAP) == TIM_TIM5_LSI)||\
- ((TIM_REMAP) == TIM_TIM5_LSE)||\
- ((TIM_REMAP) == TIM_TIM5_RTC)||\
- ((TIM_REMAP) == TIM_TIM11_GPIO)||\
- ((TIM_REMAP) == TIM_TIM11_HSE))
-#endif /* STM32F446xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT) (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\
- ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\
- ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD))
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
-
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Private Functions
- * @{
- */
-
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
+/* End of private functions --------------------------------------------------*/
/**
* @}
@@ -363,6 +345,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
}
#endif
-#endif /* __STM32F4xx_HAL_TIM_EX_H */
+
+#endif /* STM32F4xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_uart.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_uart.h
index fb81afa4c7ebc19871e7094fdd47c4fffe068357..bd47cfbd494fa07c8bf715e84295630036e9e18f 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_uart.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_uart.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,7 +22,7 @@
#define __STM32F4xx_HAL_UART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -84,13 +68,12 @@ typedef struct
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
- or disabled.
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling */
-}UART_InitTypeDef;
+} UART_InitTypeDef;
/**
* @brief HAL UART State structures definition
@@ -103,14 +86,14 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -120,9 +103,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -150,12 +133,12 @@ typedef enum
Value is allowed for gState only */
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
+} HAL_UART_StateTypeDef;
/**
* @brief UART handle Structure definition
*/
-typedef struct
+typedef struct __UART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< UART registers base address */
@@ -188,26 +171,72 @@ typedef struct
__IO uint32_t ErrorCode; /*!< UART Error code */
-}UART_HandleTypeDef;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
+
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
+
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
+/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_Error_Code UART Error Code
- * @brief UART Error Code
* @{
*/
-#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -256,12 +285,12 @@ typedef struct
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
/**
* @}
*/
- /** @defgroup UART_State UART State
+/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE 0x00000000U
@@ -283,7 +312,7 @@ typedef struct
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B 0x00000020U
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
/**
* @}
*/
@@ -292,7 +321,7 @@ typedef struct
* @{
*/
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK 0x00000800U
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
/**
* @}
*/
@@ -320,10 +349,9 @@ typedef struct
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
- * - 0001: CR1 register
- * - 0010: CR2 register
- * - 0011: CR3 register
- *
+ * - 0001: CR1 register
+ * - 0010: CR2 register
+ * - 0011: CR3 register
* @{
*/
@@ -352,24 +380,35 @@ typedef struct
/** @brief Reset UART handle gstate & RxState
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
/** @brief Flushes the UART DR register
* @param __HANDLE__ specifies the UART Handle.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
@@ -384,13 +423,12 @@ typedef struct
* @arg UART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
@@ -411,56 +449,56 @@ typedef struct
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/** @brief Clear the UART PE pending flag.
+/** @brief Clears the UART PE pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg = 0x00U; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
-/** @brief Clear the UART FE pending flag.
+/** @brief Clears the UART FE pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART NE pending flag.
+/** @brief Clears the UART NE pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART ORE pending flag.
+/** @brief Clears the UART ORE pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART IDLE pending flag.
+/** @brief Clears the UART IDLE pending flag.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
@@ -473,14 +511,14 @@ typedef struct
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define UART_IT_MASK 0x0000FFFFU
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
@@ -493,14 +531,14 @@ typedef struct
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Checks whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * UART Handle selects the USARTx or UARTy peripheral
+ * (USART,UART availability and x,y values depending on device).
* @param __IT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
@@ -509,14 +547,14 @@ typedef struct
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ERR: Error interrupt
+ * @arg UART_IT_ERR: Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
/** @brief Enable CTS flow control
- * This macro allows to enable CTS hardware flow control for a given UART instance,
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
@@ -525,7 +563,8 @@ typedef struct
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
@@ -535,7 +574,7 @@ typedef struct
} while(0U)
/** @brief Disable CTS flow control
- * This macro allows to disable CTS hardware flow control for a given UART instance,
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
@@ -544,7 +583,8 @@ typedef struct
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
@@ -563,7 +603,8 @@ typedef struct
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
@@ -582,7 +623,8 @@ typedef struct
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be USART1, USART2 or LPUART.
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+ * It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
@@ -591,13 +633,13 @@ typedef struct
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
-/** @brief macros to enables the UART's one bit sample method
+/** @brief Macro to enable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-/** @brief macros to disables the UART's one bit sample method
+/** @brief Macro to disable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -623,24 +665,33 @@ typedef struct
* @{
*/
-/** @addtogroup UART_Exported_Functions_Group1
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
+
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group2
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
* @{
*/
+
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -665,9 +716,10 @@ void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
/**
* @}
*/
@@ -707,6 +759,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/** @brief UART interruptions flag mask
*
*/
+#define UART_IT_MASK 0x0000FFFFU
+
#define UART_CR1_REG_INDEX 1U
#define UART_CR2_REG_INDEX 2U
#define UART_CR3_REG_INDEX 3U
@@ -741,7 +795,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_usart.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_usart.h
index a2e90ce69a6425f1eabcb0c0259f755c80eade58..97160a8ca7c55dd894fd39400081343c32d763b7 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_usart.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_usart.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,7 +22,7 @@
#define __STM32F4xx_HAL_USART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -73,7 +57,7 @@ typedef struct
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
- uint32_t Parity; /*!< Specifies the parity mode.
+ uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
@@ -92,7 +76,7 @@ typedef struct
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
+} USART_InitTypeDef;
/**
* @brief HAL State structures definition
@@ -107,40 +91,80 @@ typedef enum
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
+} HAL_USART_StateTypeDef;
/**
* @brief USART handle Structure definition
*/
-typedef struct
+typedef struct __USART_HandleTypeDef
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
- USART_InitTypeDef Init; /* Usart communication parameters */
+ uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
- uint8_t *pTxBuffPtr; /* Pointer to Usart Tx transfer Buffer */
+ uint16_t RxXferSize; /*!< Usart Rx Transfer size */
- uint16_t TxXferSize; /* Usart Tx Transfer size */
+ __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
- __IO uint16_t TxXferCount; /* Usart Tx Transfer Counter */
+ DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
- uint8_t *pRxBuffPtr; /* Pointer to Usart Rx transfer Buffer */
+ DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
- uint16_t RxXferSize; /* Usart Rx Transfer size */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint16_t RxXferCount; /* Usart Rx Transfer Counter */
+ __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
- DMA_HandleTypeDef *hdmatx; /* Usart Tx DMA Handle parameters */
+ __IO uint32_t ErrorCode; /*!< USART Error code */
- DMA_HandleTypeDef *hdmarx; /* Usart Rx DMA Handle parameters */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
+ void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
+ void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
+ void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
- HAL_LockTypeDef Lock; /* Locking object */
+ void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
+ void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+} USART_HandleTypeDef;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL USART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
+ HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
+ HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
+ HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
+ HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
+ HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
+ HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
- __IO HAL_USART_StateTypeDef State; /* Usart communication state */
+ HAL_USART_MSPINIT_CB_ID = 0x07U, /*!< USART MspInit callback ID */
+ HAL_USART_MSPDEINIT_CB_ID = 0x08U /*!< USART MspDeInit callback ID */
- __IO uint32_t ErrorCode; /* USART Error code */
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL USART Callback pointer definition
+ */
+typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-}USART_HandleTypeDef;
/**
* @}
*/
@@ -154,12 +178,15 @@ typedef struct
* @brief USART Error Code
* @{
*/
-#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -167,8 +194,8 @@ typedef struct
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
-#define USART_WORDLENGTH_8B 0x00000000U
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define USART_WORDLENGTH_8B 0x00000000U
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
@@ -176,10 +203,10 @@ typedef struct
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#define USART_STOPBITS_1 0x00000000U
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define USART_STOPBITS_1 0x00000000U
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
*/
@@ -187,9 +214,9 @@ typedef struct
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE 0x00000000U
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define USART_PARITY_NONE 0x00000000U
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
@@ -197,9 +224,9 @@ typedef struct
/** @defgroup USART_Mode USART Mode
* @{
*/
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
/**
* @}
*/
@@ -207,8 +234,8 @@ typedef struct
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE 0x00000000U
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
+#define USART_CLOCK_DISABLE 0x00000000U
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
@@ -216,26 +243,26 @@ typedef struct
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW 0x00000000U
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define USART_POLARITY_LOW 0x00000000U
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
-/** @defgroup USART_Clock_Phase USART Clock Phase
+/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE 0x00000000U
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define USART_PHASE_1EDGE 0x00000000U
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
*/
-/** @defgroup USART_Last_Bit USART Last Bit
+/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE 0x00000000U
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define USART_LASTBIT_DISABLE 0x00000000U
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
@@ -243,8 +270,8 @@ typedef struct
/** @defgroup USART_NACK_State USART NACK State
* @{
*/
-#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE 0x00000000U
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE 0x00000000U
/**
* @}
*/
@@ -254,14 +281,14 @@ typedef struct
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define USART_FLAG_TXE 0x00000080U
-#define USART_FLAG_TC 0x00000040U
-#define USART_FLAG_RXNE 0x00000020U
-#define USART_FLAG_IDLE 0x00000010U
-#define USART_FLAG_ORE 0x00000008U
-#define USART_FLAG_NE 0x00000004U
-#define USART_FLAG_FE 0x00000002U
-#define USART_FLAG_PE 0x00000001U
+#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
+#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
+#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
+#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
+#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
+#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
+#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
+#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
@@ -273,19 +300,14 @@ typedef struct
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
- *
* @{
*/
-#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -301,14 +323,22 @@ typedef struct
/** @brief Reset USART handle state
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief Checks whether the specified Smartcard flag is set or not.
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit data register empty flag
@@ -323,9 +353,9 @@ typedef struct
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-/** @brief Clears the specified Smartcard pending flags.
+/** @brief Clear the specified USART pending flags.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
@@ -346,12 +376,12 @@ typedef struct
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg = 0x00U; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
@@ -359,35 +389,35 @@ typedef struct
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART ORE pending flag.
+/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified USART interrupts.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -396,19 +426,18 @@ typedef struct
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __IT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -419,14 +448,14 @@ typedef struct
* @arg USART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
/** @brief Macro to enable the USART's one bit sample method
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
/** @brief Macro to disable the USART's one bit sample method
* @param __HANDLE__ specifies the USART Handle.
@@ -439,14 +468,14 @@ typedef struct
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
-#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
-#define __HAL_USART_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
@@ -464,6 +493,13 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -495,7 +531,7 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
@@ -525,9 +561,9 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-#define USART_CR1_REG_INDEX 1U
-#define USART_CR2_REG_INDEX 2U
-#define USART_CR3_REG_INDEX 3U
+#define USART_CR1_REG_INDEX 1U
+#define USART_CR2_REG_INDEX 2U
+#define USART_CR3_REG_INDEX 3U
/**
* @}
*/
@@ -536,30 +572,49 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
- ((NACK) == USART_NACK_DISABLE))
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
- ((CLOCK) == USART_CLOCK_ENABLE))
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || \
+ ((CPHA) == USART_PHASE_2EDGE))
+
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || \
+ ((CPOL) == USART_POLARITY_HIGH))
+
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
-#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+ ((LENGTH) == USART_WORDLENGTH_9B))
+
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+
+#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 12500000U)
+
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
+
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+
+ /* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+
+#define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+ (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U))
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_wwdg.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_wwdg.h
index da906ec229e825a118bb305e6f52da60986bc9ea..fbc628cfffd317cf477825d0e6f7c58217b1d755 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_wwdg.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_hal_wwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_WWDG_H
-#define __STM32F4xx_HAL_WWDG_H
+#ifndef STM32F4xx_HAL_WWDG_H
+#define STM32F4xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
@@ -53,6 +37,7 @@
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
@@ -74,18 +59,44 @@ typedef struct
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
-}WWDG_InitTypeDef;
+} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
typedef struct
+#endif
{
- WWDG_TypeDef *Instance; /*!< Register base address */
+ WWDG_TypeDef *Instance; /*!< Register base address */
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif
+} WWDG_HandleTypeDef;
-}WWDG_HandleTypeDef;
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL WWDG common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+}HAL_WWDG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL WWDG Callback pointer definition
+ */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+
+#endif
/**
* @}
*/
@@ -116,10 +127,10 @@ typedef struct
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -127,7 +138,7 @@ typedef struct
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
-#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
+#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
@@ -142,9 +153,9 @@ typedef struct
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
@@ -165,15 +176,15 @@ typedef struct
*/
/**
- * @brief Enables the WWDG peripheral.
- * @param __HANDLE__ WWDG handle
+ * @brief Enable the WWDG peripheral.
+ * @param __HANDLE__ WWDG handle
* @retval None
*/
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
- * @brief Enables the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @brief Enable the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -183,23 +194,23 @@ typedef struct
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
- * @brief Checks whether the selected WWDG interrupt has occurred or not.
+ * @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-/** @brief Clear the WWDG's interrupt pending bits
+/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
@@ -209,22 +220,22 @@ typedef struct
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the WWDG's pending flags.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to clear.
+ * @brief Clear the WWDG's pending flags.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
- * @param __HANDLE__ WWDG Handle.
- * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
- * This parameter can be one of the following values:
+/** @brief Check whether the specified WWDG interrupt source is enabled or not.
+ * @param __HANDLE__ WWDG Handle.
+ * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
@@ -235,6 +246,7 @@ typedef struct
*/
/* Exported functions --------------------------------------------------------*/
+
/** @addtogroup WWDG_Exported_Functions
* @{
*/
@@ -245,6 +257,12 @@ typedef struct
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif
+
/**
* @}
*/
@@ -255,7 +273,7 @@ void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_adc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_adc.h
index fbb2236d46de609d15c9a6186c9d9d3270aed7be..01ece7c6232074e7878acde646b27408906ecbd6 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_adc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_adc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -269,6 +253,18 @@ extern "C" {
/* ADC registers bits positions */
#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
/**
* @}
*/
@@ -299,7 +295,7 @@ extern "C" {
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
/**
* @}
@@ -1654,6 +1650,64 @@ typedef struct
/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
)
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2403,7 +2457,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -2496,7 +2550,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
return (uint32_t) (READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -3065,7 +3119,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_JOFR1_JOFFSET1,
@@ -3092,7 +3146,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JOFR1_JOFFSET1)
@@ -3189,7 +3243,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
MODIFY_REG(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
@@ -3262,7 +3316,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
@@ -3499,7 +3553,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
MODIFY_REG(*preg,
ADC_HTR_HT,
@@ -3522,7 +3576,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
}
@@ -4061,7 +4115,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4088,7 +4142,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4115,7 +4169,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4142,7 +4196,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -4169,7 +4223,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_bus.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_bus.h
index 73483f1aed93b21dd3c5231f4c2ec0ac802df715..66da28fe2419f98af932a8f7f95c61e53286246d 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_bus.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_bus.h
@@ -23,29 +23,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_cortex.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_cortex.h
index 5255c4d4865cac26092d924e8cd21fe2714de811..cfa8fbe7a896bfc54fe191b6d8b8138508ff5c53 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_cortex.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_cortex.h
@@ -22,29 +22,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_crc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_crc.h
index 0a00d7939bc79e13c00a14f30e97d384d2cb30dd..2d05b679495b0a49453d55dbd4ed4626c7fff664 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_crc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_crc.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_CRC_H
-#define __STM32F4xx_LL_CRC_H
+#ifndef STM32F4xx_LL_CRC_H
+#define STM32F4xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
@@ -61,6 +45,13 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
@@ -78,7 +69,7 @@ extern "C" {
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
@@ -107,13 +98,16 @@ extern "C" {
/**
* @brief Reset the CRC calculation unit.
+ * @note If Programmable Initial CRC value feature
+ * is available, also set the Data Register to the value stored in the
+ * CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
- WRITE_REG(CRCx->CR, CRC_CR_RESET);
+ SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
@@ -164,7 +158,7 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
@@ -205,6 +199,6 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
}
#endif
-#endif /* __STM32F4xx_LL_CRC_H */
+#endif /* STM32F4xx_LL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dac.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dac.h
index 80a7dab5e4f72cc614c0b6bb830e0fb0462146c1..fda3bd37b2cfd68206080d908f6dd4ff96bc1e3a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dac.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dac.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -141,7 +125,7 @@ extern "C" {
* @retval Pointer to register address
*/
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
/**
* @}
@@ -1122,7 +1106,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
MODIFY_REG(*preg,
DAC_DHR12R1_DACC1DHR,
@@ -1147,7 +1131,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
MODIFY_REG(*preg,
DAC_DHR12L1_DACC1DHR,
@@ -1172,7 +1156,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
MODIFY_REG(*preg,
DAC_DHR8R1_DACC1DHR,
@@ -1257,7 +1241,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+ register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma.h
index 5ba321d9d028b45c9c6c191086d8fedc476356bf..45e6b0c075d8b4a9fb051ed8d6ea9466bd04a715 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma2d.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma2d.h
index 3824a7d4d923e74835776cb7d8d1ce26ff3dca36..6864b54c4750778657b8cbcb821e188e93a3c654 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma2d.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_dma2d.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_DMA2D_H
-#define __STM32F4xx_LL_DMA2D_H
+#ifndef STM32F4xx_LL_DMA2D_H
+#define STM32F4xx_LL_DMA2D_H
#ifdef __cplusplus
extern "C" {
@@ -133,7 +117,9 @@ typedef struct
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
- uint32_t LineOffset; /*!< Specifies the output line offset value.
+
+
+ uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
@@ -148,6 +134,7 @@ typedef struct
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
+
} LL_DMA2D_InitTypeDef;
/**
@@ -162,7 +149,7 @@ typedef struct
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
- @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
- uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
+ uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using unitary functions
@@ -232,6 +219,8 @@ typedef struct
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
- @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
+
+
} LL_DMA2D_LayerCfgTypeDef;
/**
@@ -326,10 +315,10 @@ typedef struct
/** @defgroup DMA2D_LL_EC_MODE Mode
* @{
*/
-#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
-#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
-#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
-#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
+#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
+#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
+#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
+#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
@@ -375,6 +364,9 @@ typedef struct
* @}
*/
+
+
+
/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
* @{
*/
@@ -384,6 +376,7 @@ typedef struct
* @}
*/
+
/**
* @}
*/
@@ -404,7 +397,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in DMA2D register.
@@ -412,7 +405,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -449,7 +442,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
}
/**
@@ -486,7 +479,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
}
/**
@@ -511,7 +504,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
}
/**
@@ -578,6 +571,9 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
}
+
+
+
/**
* @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll OOR LO LL_DMA2D_SetLineOffset
@@ -784,7 +780,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
+ return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
}
/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
@@ -833,7 +829,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
+ return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
}
/**
@@ -933,6 +929,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
}
+
/**
* @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
@@ -1165,7 +1162,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
+ return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
}
/**
@@ -1265,6 +1262,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
}
+
/**
* @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
@@ -1468,7 +1466,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
}
/**
@@ -1479,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
}
/**
@@ -1490,7 +1488,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
}
/**
@@ -1501,7 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
}
/**
@@ -1512,7 +1510,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
}
/**
@@ -1523,7 +1521,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
+ return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
}
/**
@@ -1740,7 +1738,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
}
/**
@@ -1751,7 +1749,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
}
/**
@@ -1762,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
}
/**
@@ -1773,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
}
/**
@@ -1784,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
}
/**
@@ -1795,7 +1793,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
{
- return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
+ return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
}
@@ -1844,6 +1842,6 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
}
#endif
-#endif /* __STM32F4xx_LL_DMA2D_H */
+#endif /* STM32F4xx_LL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_exti.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_exti.h
index a633c48729655376009f6543e5575f761c26beb7..c816e266efa32a79527b115d020001a7d2ef3f1d 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_exti.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_exti.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fmc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fmc.h
index 8c3e10a02dea5d890afd08f2378ad25968146492..7df20672ed91807413bc8641df5fcf93835d53a4 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fmc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fsmc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fsmc.h
index 59b6064b320653c60dd9a9a8152b0ab288cdc657..15664d2447534fb6f2bb223d6fd815b3aaf43687 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fsmc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_fsmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_gpio.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_gpio.h
index 7eb8464fa2cb6c89004fca655bd6e65fc5ebe386..3f1b3a1d6e5006403a425cd8b52880f828be3e94 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_gpio.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_gpio.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_i2c.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_i2c.h
index 69f44ce05b4dacd27b766604b452632b37ed89af..b173cc699b69f66ae3158c580e11b82ab24c626a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_i2c.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_i2c.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1309,7 +1293,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
/**
* @brief Indicate the status of 10-bit header sent (master mode).
- * @note RESET: When no ADD10 event occured.
+ * @note RESET: When no ADD10 event occurred.
* SET: When the master has sent the first address byte (header).
* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
* @param I2Cx I2C Instance.
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_iwdg.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_iwdg.h
index 49a106cc05e47ee8b0a674950982ac469bd141a8..571135118072dd48bd47916d7c850d24bafdb659 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_iwdg.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_iwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_IWDG_H
-#define __STM32F4xx_LL_IWDG_H
+#ifndef STM32F4xx_LL_IWDG_H
+#define STM32F4xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
@@ -61,12 +45,10 @@ extern "C" {
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
-
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
/**
* @}
*/
@@ -85,7 +67,6 @@ extern "C" {
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
-
/**
* @}
*/
@@ -159,7 +140,7 @@ extern "C" {
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
@@ -170,7 +151,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
@@ -181,7 +162,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
@@ -192,7 +173,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
@@ -229,7 +210,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->PR));
+ return (READ_REG(IWDGx->PR));
}
/**
@@ -252,7 +233,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->RLR));
+ return (READ_REG(IWDGx->RLR));
}
@@ -272,7 +253,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
@@ -283,12 +264,11 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
-
/**
- * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
+ * @brief Check if flags Prescaler & Reload Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
@@ -296,7 +276,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
}
/**
@@ -312,7 +292,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
* @}
*/
-#endif /* IWDG) */
+#endif /* IWDG */
/**
* @}
@@ -322,6 +302,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
}
#endif
-#endif /* __STM32F4xx_LL_IWDG_H */
+#endif /* STM32F4xx_LL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_lptim.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_lptim.h
index 615d7fbbd8a53729e7141e43512d50830d7bb4fe..636e5fa4e655fbd2a41dca974564034d84c7a726 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_lptim.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_lptim.h
@@ -4,38 +4,22 @@
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
- * @attention
+ * @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_LPTIM_H
-#define __STM32F4xx_LL_LPTIM_H
+#ifndef STM32F4xx_LL_LPTIM_H
+#define STM32F4xx_LL_LPTIM_H
#ifdef __cplusplus
extern "C" {
@@ -47,8 +31,9 @@ extern "C" {
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
+
#if defined (LPTIM1)
-
+
/** @defgroup LPTIM_LL LPTIM
* @{
*/
@@ -143,8 +128,8 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
* @{
*/
-#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__))
+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
@@ -303,7 +287,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -312,12 +296,25 @@ typedef struct
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
* @{
*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
* @{
*/
@@ -335,17 +332,6 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
-/**
- * @brief Disable the LPTIM instance
- * @rmtoll CR ENABLE LL_LPTIM_Disable
- * @param LPTIMx Low-Power Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
-{
- CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
-}
-
/**
* @brief Indicates whether the LPTIM instance is enabled.
* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
@@ -354,7 +340,7 @@ __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
}
/**
@@ -375,7 +361,6 @@ __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t Opera
MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
}
-
/**
* @brief Set the LPTIM registers update mode (enable/disable register preload)
* @note This function must be called when the LPTIM instance is disabled.
@@ -623,7 +608,6 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
-
/**
* @}
*/
@@ -671,7 +655,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
}
/**
@@ -711,7 +695,6 @@ __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
- * (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
@@ -931,7 +914,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
}
/**
@@ -961,7 +944,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
}
/**
@@ -976,14 +959,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
}
/**
- * @brief Inform application whether a autoreload match interrupt has occured.
+ * @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
}
/**
@@ -1005,7 +988,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
}
/**
@@ -1020,14 +1003,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
}
/**
@@ -1042,14 +1025,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
}
/**
- * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
+ * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
}
/**
@@ -1071,7 +1054,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
}
/**
@@ -1093,7 +1076,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
}
/**
@@ -1134,7 +1117,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
}
/**
@@ -1167,7 +1150,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
}
/**
@@ -1200,7 +1183,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
}
/**
@@ -1233,7 +1216,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
}
/**
@@ -1266,7 +1249,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
}
/**
@@ -1299,7 +1282,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
}
/**
@@ -1332,26 +1315,13 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
}
/**
* @}
*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
- * @{
- */
-
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
/**
* @}
*/
@@ -1370,6 +1340,6 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_Ini
}
#endif
-#endif /* __STM32F4xx_LL_LPTIM_H */
+#endif /* STM32F4xx_LL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_pwr.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_pwr.h
index 0d507c35df7239500a5e761796c84daad51b2744..69d463e25f53059bc8d80c65f397d7320a438aa6 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_pwr.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_pwr.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rcc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rcc.h
index 90354506bbf342395d89df7edc608467f83341f8..c7e93d941b78a1b2cf0e8d3f94e3a44a9e53241e 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rcc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -5354,7 +5338,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
@@ -5474,7 +5458,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PL
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
@@ -5678,7 +5662,7 @@ __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
#if defined(RCC_PLLI2SCFGR_PLLI2SM)
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rng.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rng.h
index db1725d204a67f084de71e16f914e8086356bac2..c142717b0cfb9212716e2984d6f4d2429a3477ac 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rng.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rng.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_RNG_H
-#define __STM32F4xx_LL_RNG_H
+#ifndef STM32F4xx_LL_RNG_H
+#define STM32F4xx_LL_RNG_H
#ifdef __cplusplus
extern "C" {
@@ -48,7 +32,7 @@ extern "C" {
* @{
*/
-#if defined(RNG)
+#if defined (RNG)
/** @defgroup RNG_LL RNG
* @{
@@ -65,6 +49,7 @@ extern "C" {
* @{
*/
+
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
@@ -163,7 +148,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
+ return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
/**
@@ -182,7 +167,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
+ return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
/**
@@ -193,7 +178,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
/**
@@ -204,7 +189,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
/**
@@ -215,7 +200,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
/**
@@ -226,7 +211,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
+ return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
/**
@@ -292,7 +277,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
{
- return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
+ return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
/**
@@ -322,7 +307,6 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
/**
@@ -338,7 +322,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
* @}
*/
-#endif /* defined(RNG) */
+#endif /* RNG */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rtc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rtc.h
index 7f4efff049ef321e4331f825b3fd8f39022aa0c4..c4f9422565bf383ad03137e2371c278b6a151c90 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rtc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_rtc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1210,10 +1194,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
- return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
}
/**
@@ -1248,10 +1229,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
- return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos);
}
/**
@@ -1286,10 +1264,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
}
/**
@@ -1482,10 +1457,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
}
/**
@@ -1578,10 +1550,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
- return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos);
}
/**
@@ -1611,10 +1580,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
- return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
}
/**
@@ -1811,10 +1777,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
- return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
}
/**
@@ -1906,10 +1869,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
- return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
+ return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
}
/**
@@ -1937,10 +1897,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
- return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
}
/**
@@ -1968,10 +1925,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
}
/**
@@ -2189,10 +2143,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
- return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
+ return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
}
/**
@@ -2284,10 +2235,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
- return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
}
/**
@@ -2315,10 +2263,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
- return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_sdmmc.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_sdmmc.h
index 1205363be47a2b76f6f81f3f2150e3deceed8b32..965dd46eb619de46bb1ada2fb12ae83d9d320441 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_sdmmc.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_sdmmc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_spi.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_spi.h
index 0d98b940303747df8b2bd69b245a5590d3e62afb..13d1883af367aaa499da62e0b7609b57f685131f 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_spi.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_spi.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_SPI_H
-#define __STM32F4xx_LL_SPI_H
+#ifndef STM32F4xx_LL_SPI_H
+#define STM32F4xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
@@ -162,7 +146,7 @@ typedef struct
* @{
*/
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
/**
* @}
*/
@@ -252,8 +236,8 @@ typedef struct
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
* @{
*/
-#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
/**
* @}
*/
@@ -336,7 +320,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
@@ -628,7 +612,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
/**
@@ -747,7 +731,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -758,7 +742,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
/**
@@ -769,7 +753,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
/**
@@ -780,7 +764,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
@@ -791,7 +775,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
@@ -809,7 +793,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
/**
@@ -820,7 +804,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
}
/**
@@ -844,11 +828,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void) tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
@@ -966,7 +949,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
/**
@@ -977,7 +960,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
/**
@@ -988,7 +971,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
/**
@@ -1029,7 +1012,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1062,7 +1045,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1115,7 +1098,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
- SPIx->DR = TxData;
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif
}
/**
@@ -1127,7 +1115,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
SPIx->DR = TxData;
+#endif
}
/**
@@ -1313,16 +1306,16 @@ typedef struct
* @{
*/
-#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
/**
* @}
*/
@@ -1407,7 +1400,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
/**
@@ -1616,7 +1609,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
#if defined(SPI_I2SCFGR_ASTRTEN)
@@ -1650,7 +1643,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
}
#endif /* SPI_I2SCFGR_ASTRTEN */
@@ -1714,7 +1707,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
@@ -1739,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
/**
@@ -2031,6 +2024,6 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_
}
#endif
-#endif /* __STM32F4xx_LL_SPI_H */
+#endif /* STM32F4xx_LL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_system.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_system.h
index 899b4cd377f2099d2537da9f857032518d924e6c..cf342408859a18459dc29d04020a40e9dd41d699 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_system.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_system.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_tim.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_tim.h
index d17cddf36d5978cb0ce11067c072cc89c6e86388..fcdfd6e461f751fd58a4b33e358c054c28e38d27 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_tim.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_tim.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -117,7 +101,6 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @}
*/
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{
@@ -132,16 +115,16 @@ static const uint8_t SHIFT_TAB_OISx[] =
#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7FU)
-#define DT_DELAY_2 ((uint8_t)0x3FU)
-#define DT_DELAY_3 ((uint8_t)0x1FU)
-#define DT_DELAY_4 ((uint8_t)0x1FU)
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00U)
-#define DT_RANGE_2 ((uint8_t)0x80U)
-#define DT_RANGE_3 ((uint8_t)0xC0U)
-#define DT_RANGE_4 ((uint8_t)0xE0U)
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
/**
@@ -622,7 +605,7 @@ typedef struct
#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!TIMx_CCRy else active.*/
#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/
@@ -662,7 +645,7 @@ typedef struct
/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
* @{
*/
-#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
@@ -707,7 +690,7 @@ typedef struct
* @{
*/
#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
/**
* @}
@@ -716,9 +699,9 @@ typedef struct
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{
*/
-#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
/**
* @}
*/
@@ -753,14 +736,14 @@ typedef struct
/** @defgroup TIM_LL_EC_TS Trigger Selection
* @{
*/
-#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
/**
* @}
*/
@@ -861,7 +844,6 @@ typedef struct
#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
/**
* @}
*/
@@ -924,7 +906,6 @@ typedef struct
* @}
*/
-
/**
* @}
*/
@@ -944,7 +925,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in TIM register.
@@ -952,7 +933,7 @@ typedef struct
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -974,9 +955,9 @@ typedef struct
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
@@ -987,7 +968,7 @@ typedef struct
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -998,7 +979,7 @@ typedef struct
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -1086,7 +1067,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
/**
@@ -1119,7 +1100,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
/**
@@ -1188,6 +1169,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
@@ -1201,7 +1185,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
- MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
}
/**
@@ -1243,7 +1227,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+ CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
}
/**
@@ -1254,7 +1238,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
/**
@@ -1585,7 +1569,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
- return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
/**
@@ -1623,7 +1607,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -1658,7 +1642,7 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -1687,7 +1671,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -1827,7 +1811,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1849,7 +1833,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1871,9 +1855,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
@@ -1893,7 +1877,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1914,7 +1898,7 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1935,9 +1919,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
@@ -1960,7 +1944,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -1983,7 +1967,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2008,13 +1992,13 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@@ -2205,7 +2189,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2233,7 +2217,7 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2257,7 +2241,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2283,7 +2267,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2308,7 +2292,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2346,7 +2330,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2383,7 +2367,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2480,7 +2464,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
/**
@@ -2591,7 +2575,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
/**
@@ -2740,7 +2724,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
/**
@@ -2801,7 +2785,11 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
+ __IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+ /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
}
/**
@@ -2814,7 +2802,11 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
+ __IO uint32_t tmpreg;
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+ /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
}
/**
@@ -2830,7 +2822,11 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
+ __IO uint32_t tmpreg;
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+ /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
+ tmpreg = READ_REG(TIMx->BDTR);
+ (void)(tmpreg);
}
/**
@@ -2889,7 +2885,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
/**
@@ -2932,7 +2928,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
/**
@@ -2968,7 +2964,6 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
@@ -2992,7 +2987,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
- MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
}
/**
@@ -3048,7 +3043,6 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
* @}
*/
-
/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
* @{
*/
@@ -3071,7 +3065,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
/**
@@ -3093,7 +3087,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
/**
@@ -3115,7 +3109,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
/**
@@ -3137,7 +3131,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
/**
@@ -3159,7 +3153,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
/**
@@ -3181,7 +3175,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
/**
@@ -3203,7 +3197,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
/**
@@ -3225,7 +3219,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
/**
@@ -3247,7 +3241,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
/**
@@ -3269,7 +3263,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
/**
@@ -3291,7 +3285,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
/**
@@ -3313,7 +3307,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
/**
@@ -3353,7 +3347,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
/**
@@ -3386,7 +3380,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
/**
@@ -3419,7 +3413,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
/**
@@ -3452,7 +3446,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
/**
@@ -3485,7 +3479,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
/**
@@ -3518,7 +3512,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
/**
@@ -3551,7 +3545,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
/**
@@ -3584,7 +3578,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
/**
@@ -3624,7 +3618,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
/**
@@ -3657,7 +3651,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
@@ -3690,7 +3684,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
@@ -3723,7 +3717,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
/**
@@ -3756,7 +3750,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
/**
@@ -3789,7 +3783,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
/**
@@ -3822,7 +3816,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usart.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usart.h
index f6433c7e6ba0a83de52476330bb9c030cc796897..c75c68f3356bd4ec9f45d7257054c0853314bcb4 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usart.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usart.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1982,7 +1966,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
{
- WRITE_REG(USARTx->SR , ~(USART_SR_TC));
+ WRITE_REG(USARTx->SR, ~(USART_SR_TC));
}
/**
@@ -1993,7 +1977,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
{
- WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
+ WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
}
/**
@@ -2006,7 +1990,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
{
- WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
+ WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
}
/**
@@ -2019,7 +2003,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
*/
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
{
- WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
+ WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
}
/**
@@ -2398,7 +2382,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
{
/* return address of DR register */
- return ((uint32_t) &(USARTx->DR));
+ return ((uint32_t) & (USARTx->DR));
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usb.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usb.h
index 8eae25c1b8d6b31b7ccca9982f71bc3a23ddfb9f..a1f31b3a649df1344cf7efc7d3ab274cfc132cdd 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usb.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_usb.h
@@ -2,57 +2,38 @@
******************************************************************************
* @file stm32f4xx_ll_usb.h
* @author MCD Application Team
- * @brief Header file of USB Core HAL module.
+ * @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_USB_H
-#define __STM32F4xx_LL_USB_H
+#ifndef STM32F4xx_LL_USB_H
+#define STM32F4xx_LL_USB_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
-/** @addtogroup STM32F4xx_HAL
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-/** @addtogroup USB_Core
+/** @addtogroup USB_LL
* @{
*/
@@ -61,32 +42,34 @@
/**
* @brief USB Mode definition
*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
typedef enum
{
- USB_OTG_DEVICE_MODE = 0U,
- USB_OTG_HOST_MODE = 1U,
- USB_OTG_DRD_MODE = 2U
-
-}USB_OTG_ModeTypeDef;
+ USB_DEVICE_MODE = 0,
+ USB_HOST_MODE = 1,
+ USB_DRD_MODE = 2
+} USB_OTG_ModeTypeDef;
/**
* @brief URB States definition
*/
-typedef enum {
- URB_IDLE = 0U,
+typedef enum
+{
+ URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
-
-}USB_OTG_URBStateTypeDef;
+} USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
-typedef enum {
- HC_IDLE = 0U,
+typedef enum
+{
+ HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_NAK,
@@ -95,144 +78,135 @@ typedef enum {
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
-
-}USB_OTG_HCStateTypeDef;
+} USB_OTG_HCStateTypeDef;
/**
- * @brief PCD Initialization Structure definition
+ * @brief USB OTG Initialization Structure definition
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t Host_channels; /*!< Host Channels number.
- This parameter Depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint32_t Host_channels; /*!< Host Channels number.
+ This parameter Depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
- uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
+ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS_ */
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY_ */
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY_ */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
+ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+} USB_OTG_CfgTypeDef;
-}USB_OTG_CfgTypeDef;
-
-/**
- * @brief OTG End Point Initialization Structure definition
- */
typedef struct
{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type_ */
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t even_odd_frame; /*!< IFrame parity
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t even_odd_frame; /*!< IFrame parity
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint16_t tx_fifo_num; /*!< Transmission FIFO number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint16_t tx_fifo_num; /*!< Transmission FIFO number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
- uint32_t xfer_len; /*!< Current transfer length */
+ uint32_t xfer_len; /*!< Current transfer length */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+} USB_OTG_EPTypeDef;
-}USB_OTG_EPTypeDef;
-
-/**
- * @brief OTG HC Initialization Structure definition
- */
typedef struct
{
- uint8_t dev_addr ; /*!< USB device address.
- This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
+ uint8_t dev_addr ; /*!< USB device address.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
- uint8_t ch_num; /*!< Host channel number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t ch_num; /*!< Host channel number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t ep_num; /*!< Endpoint number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t ep_num; /*!< Endpoint number.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t ep_is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t ep_is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
+ uint8_t speed; /*!< USB Host speed.
+ This parameter can be any value of @ref USB_Core_Speed_ */
- uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
- uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
+ uint8_t ep_type; /*!< Endpoint Type.
+ This parameter can be any value of @ref USB_EP_Type_ */
- uint16_t max_packet; /*!< Endpoint Max packet size.
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+ uint16_t max_packet; /*!< Endpoint Max packet size.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t data_pid; /*!< Initial data PID.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid; /*!< Initial data PID.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
- uint32_t xfer_len; /*!< Current transfer length. */
+ uint32_t xfer_len; /*!< Current transfer length. */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
- uint8_t toggle_in; /*!< IN transfer current toggle flag.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t toggle_in; /*!< IN transfer current toggle flag.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t toggle_out; /*!< OUT transfer current toggle flag
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t toggle_out; /*!< OUT transfer current toggle flag
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
+ uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
- uint32_t ErrCnt; /*!< Host channel error count.*/
+ uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
- This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+ This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-}USB_OTG_HCTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -240,6 +214,16 @@ typedef struct
* @{
*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+ * @{
+ */
+#define USB_OTG_CORE_ID_300A 0x4F54300AU
+#define USB_OTG_CORE_ID_310A 0x4F54310AU
+/**
+ * @}
+ */
+
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
@@ -250,18 +234,29 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_Speed_ USB Core Speed
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_HS_SPEED 0U
+#define USBD_HSINFS_SPEED 1U
+#define USBH_HS_SPEED 0U
+#define USBD_FS_SPEED 2U
+#define USBH_FS_SPEED 1U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0U
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
-#define USB_OTG_SPEED_LOW 2U
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
-/** @defgroup USB_Core_PHY_ USB Core PHY
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1U
@@ -270,28 +265,42 @@ typedef struct
* @}
*/
-/** @defgroup USB_Core_MPS_ USB Core MPS
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE 5U
+#define USBD_DEFAULT_TRDT_VALUE 9U
+#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
-/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1U)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1U)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1U)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1U)
+#define USB_OTG_HS_MAX_PACKET_SIZE 512U
+#define USB_OTG_FS_MAX_PACKET_SIZE 64U
+#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
-/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+ * @{
+ */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
@@ -302,7 +311,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP0_MPS_ USB EP0 MPS
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
@@ -313,7 +322,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP_Speed_ USB EP Speed
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
@@ -323,7 +332,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_EP_Type_ USB EP Type
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
@@ -335,7 +344,7 @@ typedef struct
* @}
*/
-/** @defgroup USB_STS_Defines_ USB STS Defines
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
@@ -347,7 +356,7 @@ typedef struct
* @}
*/
-/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
@@ -357,7 +366,7 @@ typedef struct
* @}
*/
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
@@ -382,78 +391,98 @@ typedef struct
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
-#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
-#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+#define EP_ADDR_MSK 0xFU
/**
* @}
*/
+
/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
+ uint8_t ch_num,
+ uint8_t epnum,
+ uint8_t dev_address,
+ uint8_t speed,
+ uint8_t ep_type,
+ uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
@@ -462,14 +491,21 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_LL_USB_H */
+#endif /* STM32F4xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_utils.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_utils.h
index b90e5f6bad9478c30343a0587ea86e07c5248747..3510f716965e9c764210c1176d777f72b435b5a1 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_utils.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_utils.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -237,7 +221,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
- return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
}
/**
@@ -255,7 +239,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
- return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_wwdg.h b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_wwdg.h
index 3e3b09308744b12ec13262dd85b299dcb481b5b2..9fed6aad0d83633c81eb375610789c30816d760a 100644
--- a/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_wwdg.h
+++ b/stm32cube/stm32f4xx/drivers/include/stm32f4xx_ll_wwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_WWDG_H
-#define __STM32F4xx_LL_WWDG_H
+#ifndef STM32F4xx_LL_WWDG_H
+#define STM32F4xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
@@ -56,23 +40,19 @@ extern "C" {
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-
/* Private constants ---------------------------------------------------------*/
-
/* Private macros ------------------------------------------------------------*/
-
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
-
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
@@ -80,10 +60,10 @@ extern "C" {
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
-#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -119,7 +99,6 @@ extern "C" {
* @}
*/
-
/**
* @}
*/
@@ -155,7 +134,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+ return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
@@ -182,7 +161,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+ return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
@@ -196,7 +175,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
- * @retval None
+* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
@@ -215,7 +194,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
@@ -247,7 +226,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
@@ -268,7 +247,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+ return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
@@ -310,7 +289,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+ return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/Legacy/stm32f4xx_hal_can.c b/stm32cube/stm32f4xx/drivers/src/Legacy/stm32f4xx_hal_can.c
index 650b029da95daf0519abfaa888ba8cf00a8e0bfb..49131abc2755a276923ff9ea6788bfa6f62db25b 100644
--- a/stm32cube/stm32f4xx/drivers/src/Legacy/stm32f4xx_hal_can.c
+++ b/stm32cube/stm32f4xx/drivers/src/Legacy/stm32f4xx_hal_can.c
@@ -82,29 +82,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -136,9 +120,7 @@
#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file'
#endif /* HAL_CAN_MODULE_ENABLED */
-#if 0 /* Disable systematic warning message */
#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
-#endif
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -391,7 +373,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
#if defined (CAN3)
/* Check the CAN instance */
if(hcan->Instance == CAN3)
- {
+ {
can_ip = CAN3;
}
else
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal.c
index c436faa948694abc9d22dc59b172b1993ed92316..f53d3f0929430442609ad9bc5a9a8da9e18fe904 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal.c
@@ -21,29 +21,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -66,11 +50,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.7.4
+ * @brief STM32F4xx HAL Driver version number V1.7.6
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@@ -542,15 +526,30 @@ void HAL_DisableCompensationCell(void)
}
/**
- * @brief Return the unique device identifier (UID based on 96 bits)
- * @param UID pointer to 3 words array.
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
-void HAL_GetUID(uint32_t *UID)
+uint32_t HAL_GetUIDw2(void)
{
- UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
- UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
- UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc.c
index 4a89f186819b42019c4737533ad5f18efb713330..77d652ec2654a6cceb5bcaa6e57722808f38af23 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc.c
@@ -157,34 +157,90 @@
(#) Optionally, in case of usage of DMA:
(++) Deinitialize the DMA using function HAL_DMA_DeInit().
(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
+ *** Callback registration ***
+ ==============================================================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -283,14 +339,30 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
if(hadc->State == HAL_ADC_STATE_RESET)
{
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_ADC_MspInit(hadc);
}
/* Configuration of ADC parameters if previous preliminary actions are */
@@ -355,8 +427,18 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
/* correctly completed. */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -372,6 +454,208 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
return tmp_hal_status;
}
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @brief Initializes the ADC MSP.
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
@@ -507,12 +791,20 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+#if defined(ADC2) && defined(ADC3)
+ if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
+ || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+#endif /* ADC2 || ADC3 */
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+#if defined(ADC2) && defined(ADC3)
}
+#endif /* ADC2 || ADC3 */
}
else
{
@@ -807,12 +1099,20 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+#if defined(ADC2) && defined(ADC3)
+ if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
+ || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+#endif /* ADC2 || ADC3 */
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+#if defined(ADC2) && defined(ADC3)
}
+#endif /* ADC2 || ADC3 */
}
else
{
@@ -923,7 +1223,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
}
/* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
@@ -965,7 +1269,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
}
/* Conversion complete callback */
- HAL_ADCEx_InjectedConvCpltCallback(hadc);
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
@@ -982,7 +1291,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
@@ -1005,7 +1318,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
- HAL_ADC_ErrorCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
@@ -1117,12 +1434,20 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
{
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+#if defined(ADC2) && defined(ADC3)
+ if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
+ || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+#endif /* ADC2 || ADC3 */
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+#if defined(ADC2) && defined(ADC3)
}
+#endif /* ADC2 || ADC3 */
}
else
{
@@ -1356,17 +1681,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
- /* if ADC1 Channel_18 is selected enable VBAT Channel */
+ /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
+ /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
+ if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
+ {
+ tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
+ }
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
}
- /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+ /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
+ Channel_17 is selected for VREFINT enable TSVREFE */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
- /* Enable the TSVREFE channel*/
+ /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
+ if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
+ {
+ tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
+ }
+ /* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
@@ -1568,7 +1904,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
- hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
+ hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
@@ -1593,7 +1929,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
- hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
+ hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
@@ -1644,12 +1980,28 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
}
/* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
- else
+ else /* DMA and-or internal error occurred */
{
- /* Call DMA error callback */
- hadc->DMA_Handle->XferErrorCallback(hdma);
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
}
}
@@ -1662,8 +2014,12 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
@@ -1678,7 +2034,12 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc_ex.c
index deb793d31f13270fc82d05c48c3df5c0c16ba689..f1193a0ae120c298c584cd6a8226367acd83ef53 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_adc_ex.c
@@ -84,29 +84,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_can.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_can.c
index 10dc178d0e2c712e54f95cfbb46d92861658c2cc..a2ccfd5fd5f21d7042a0ad8e470c99e2aeda3da9 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_can.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_can.c
@@ -126,33 +126,85 @@
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
if automatic wake up mode is enabled.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+
+ By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ example @ref HAL_CAN_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()
+ or @ref HAL_CAN_Init() function.
+
+ When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -221,7 +273,7 @@
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
@@ -243,11 +295,40 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Reset callbacks to legacy functions */
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
+ hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcan->MspInitCallback == NULL)
+ {
+ hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ hcan->MspInitCallback(hcan);
+ }
+
+#else
if (hcan->State == HAL_CAN_STATE_RESET)
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -256,7 +337,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Check Sleep mode leave acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -277,7 +358,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait initialisation acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -387,10 +468,21 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
/* Stop the CAN module */
- HAL_CAN_Stop(hcan);
+ (void)HAL_CAN_Stop(hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->MspDeInitCallback == NULL)
+ {
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
+ }
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hcan->MspDeInitCallback(hcan);
+
+#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -437,6 +529,284 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
*/
}
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a CAN CallBack.
+ * To be used instead of the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = pCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = pCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a CAN CallBack.
+ * CAN callabck is redirected to the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = HAL_CAN_SleepCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
@@ -467,11 +837,12 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
- uint32_t filternbrbitpos = 0U;
+ uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check the parameters */
assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
@@ -481,7 +852,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
#if defined(CAN3)
/* Check the CAN instance */
@@ -536,7 +907,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
#endif
/* Convert filter number into bit position */
- filternbrbitpos = (1U) << sFilterConfig->FilterBank;
+ filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
@@ -601,7 +972,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
}
/* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
+ if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
}
@@ -660,7 +1031,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDe
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
{
@@ -674,7 +1045,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
@@ -712,7 +1083,7 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_LISTENING)
{
@@ -723,7 +1094,7 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
@@ -767,8 +1138,10 @@ HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
*/
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
{
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Request Sleep mode */
SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -798,9 +1171,10 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
{
__IO uint32_t count = 0;
uint32_t timeout = 1000000U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Wake up request */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -808,8 +1182,11 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
/* Wait sleep mode is exited */
do
{
+ /* Increment counter */
+ count++;
+
/* Check if timeout is reached */
- if (++count > timeout)
+ if (count > timeout)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
@@ -817,7 +1194,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
return HAL_ERROR;
}
}
- while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
/* Return function status */
return HAL_OK;
@@ -842,12 +1219,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
{
uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Sleep mode */
- if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
status = 1U;
}
@@ -872,6 +1250,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
+ uint32_t tsr = READ_REG(hcan->Instance->TSR);
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(pHeader->IDE));
@@ -887,19 +1267,28 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
- if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||
- ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||
- ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))
+ if (((tsr & CAN_TSR_TME0) != 0U) ||
+ ((tsr & CAN_TSR_TME1) != 0U) ||
+ ((tsr & CAN_TSR_TME2) != 0U))
{
/* Select an empty transmit mailbox */
- transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+ transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Check transmit mailbox value */
+ if (transmitmailbox > 2U)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+ return HAL_ERROR;
+ }
/* Store the Tx mailbox */
- *pTxMailbox = 1U << transmitmailbox;
+ *pTxMailbox = (uint32_t)1 << transmitmailbox;
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
@@ -968,28 +1357,30 @@ HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderType
*/
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 */
- if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
{
/* Add cancellation request for Tx Mailbox 0 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
}
/* Check Tx Mailbox 1 */
- if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
{
/* Add cancellation request for Tx Mailbox 1 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
}
/* Check Tx Mailbox 2 */
- if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
{
/* Add cancellation request for Tx Mailbox 2 */
SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
@@ -1016,24 +1407,25 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
{
uint32_t freelevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check Tx Mailbox 0 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 1 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
{
freelevel++;
}
/* Check Tx Mailbox 2 status */
- if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
{
freelevel++;
}
@@ -1058,12 +1450,13 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
{
uint32_t status = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check pending transmission request on the selected Tx Mailboxes */
if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
@@ -1090,12 +1483,13 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
{
uint32_t timestamp = 0U;
uint32_t transmitmailbox;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Select the Tx mailbox */
transmitmailbox = POSITION_VAL(TxMailbox);
@@ -1121,16 +1515,18 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
assert_param(IS_CAN_RX_FIFO(RxFifo));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
{
/* Check that the Rx FIFO 0 is not empty */
- if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
@@ -1138,10 +1534,10 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
return HAL_ERROR;
}
}
- else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
- if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
@@ -1166,14 +1562,14 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
/* Get the data */
- aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;
- aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;
- aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;
- aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;
- aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;
- aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;
- aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;
- aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;
+ aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+ aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+ aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+ aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+ aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+ aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+ aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+ aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
@@ -1181,7 +1577,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
}
- else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
@@ -1210,12 +1606,13 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
uint32_t filllevel = 0U;
+ HAL_CAN_StateTypeDef state = hcan->State;
/* Check function parameters */
assert_param(IS_CAN_RX_FIFO(RxFifo));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
if (RxFifo == CAN_RX_FIFO0)
{
@@ -1261,11 +1658,13 @@ uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
@@ -1292,11 +1691,13 @@ HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t
*/
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
/* Check function parameters */
assert_param(IS_CAN_IT(InactiveITs));
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Disable the selected interrupts */
__HAL_CAN_DISABLE_IT(hcan, InactiveITs);
@@ -1330,28 +1731,33 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
/* Transmit Mailbox empty interrupt management *****************************/
- if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
{
/* Transmit Mailbox 0 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP0) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP0) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
- if ((tsrflags & CAN_TSR_TXOK0) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK0) != 0U)
{
/* Transmission Mailbox 0 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST0) != RESET)
+ if ((tsrflags & CAN_TSR_ALST0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
}
- else if ((tsrflags & CAN_TSR_TERR0) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR0) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
@@ -1359,32 +1765,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 0 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 1 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP1) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP1) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
- if ((tsrflags & CAN_TSR_TXOK1) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK1) != 0U)
{
/* Transmission Mailbox 1 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST1) != RESET)
+ if ((tsrflags & CAN_TSR_ALST1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
}
- else if ((tsrflags & CAN_TSR_TERR1) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR1) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
@@ -1392,32 +1808,42 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 1 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
/* Transmit Mailbox 2 management *****************************************/
- if ((tsrflags & CAN_TSR_RQCP2) != RESET)
+ if ((tsrflags & CAN_TSR_RQCP2) != 0U)
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
- if ((tsrflags & CAN_TSR_TXOK2) != RESET)
+ if ((tsrflags & CAN_TSR_TXOK2) != 0U)
{
/* Transmission Mailbox 2 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
- if ((tsrflags & CAN_TSR_ALST2) != RESET)
+ if ((tsrflags & CAN_TSR_ALST2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
}
- else if ((tsrflags & CAN_TSR_TERR2) != RESET)
+ else if ((tsrflags & CAN_TSR_TERR2) != 0U)
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
@@ -1425,17 +1851,22 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
else
{
/* Transmission Mailbox 2 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
- if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
{
- if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)
+ if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
@@ -1446,35 +1877,45 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Receive FIFO 0 full interrupt management ********************************/
- if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
{
- if ((rf0rflags & CAN_RF0R_FULL0) != RESET)
+ if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
/* Receive FIFO 0 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
- if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
- if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
{
/* Receive FIFO 0 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
- if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
{
- if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)
+ if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
@@ -1485,67 +1926,87 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Receive FIFO 1 full interrupt management ********************************/
- if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
{
- if ((rf1rflags & CAN_RF1R_FULL1) != RESET)
+ if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
/* Receive FIFO 1 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
- if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
{
/* Check if message is still pending */
- if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
{
/* Receive FIFO 1 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
- if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)
+ if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
{
- if ((msrflags & CAN_MSR_SLAKI) != RESET)
+ if ((msrflags & CAN_MSR_SLAKI) != 0U)
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
/* Sleep Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->SleepCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
- if ((interrupts & CAN_IT_WAKEUP) != RESET)
+ if ((interrupts & CAN_IT_WAKEUP) != 0U)
{
- if ((msrflags & CAN_MSR_WKUI) != RESET)
+ if ((msrflags & CAN_MSR_WKUI) != 0U)
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
/* WakeUp Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->WakeUpFromRxMsgCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
- if ((interrupts & CAN_IT_ERROR) != RESET)
+ if ((interrupts & CAN_IT_ERROR) != 0U)
{
- if ((msrflags & CAN_MSR_ERRI) != RESET)
+ if ((msrflags & CAN_MSR_ERRI) != 0U)
{
/* Check Error Warning Flag */
- if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&
- ((esrflags & CAN_ESR_EWGF) != RESET))
+ if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+ ((esrflags & CAN_ESR_EWGF) != 0U))
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
@@ -1554,8 +2015,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Error Passive Flag */
- if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&
- ((esrflags & CAN_ESR_EPVF) != RESET))
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+ ((esrflags & CAN_ESR_EPVF) != 0U))
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
@@ -1564,8 +2025,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Bus-off Flag */
- if (((interrupts & CAN_IT_BUSOFF) != RESET) &&
- ((esrflags & CAN_ESR_BOFF) != RESET))
+ if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+ ((esrflags & CAN_ESR_BOFF) != 0U))
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
@@ -1574,8 +2035,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
}
/* Check Last Error Code Flag */
- if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&
- ((esrflags & CAN_ESR_LEC) != RESET))
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+ ((esrflags & CAN_ESR_LEC) != 0U))
{
switch (esrflags & CAN_ESR_LEC)
{
@@ -1623,8 +2084,13 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
hcan->ErrorCode |= errorcode;
/* Call Error callback function */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->ErrorCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1909,21 +2375,25 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
{
HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Check sleep mode acknowledge flag */
- if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
{
/* Sleep mode is active */
state = HAL_CAN_STATE_SLEEP_ACTIVE;
}
/* Check sleep mode request flag */
- else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
{
/* Sleep mode request is pending */
state = HAL_CAN_STATE_SLEEP_PENDING;
}
+ else
+ {
+ /* Neither sleep mode request nor sleep mode acknowledge */
+ }
}
/* Return CAN state */
@@ -1951,9 +2421,10 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
{
HAL_StatusTypeDef status = HAL_OK;
+ HAL_CAN_StateTypeDef state = hcan->State;
- if ((hcan->State == HAL_CAN_STATE_READY) ||
- (hcan->State == HAL_CAN_STATE_LISTENING))
+ if ((state == HAL_CAN_STATE_READY) ||
+ (state == HAL_CAN_STATE_LISTENING))
{
/* Reset CAN error code */
hcan->ErrorCode = 0U;
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cec.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cec.c
index b9b32389320f12b4e597dcdd69a9073c4b301c13..5d9f683ae81c56319295495b74463805a43fee63 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cec.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cec.c
@@ -6,9 +6,9 @@
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
+ * + Initialization and de-initialization function
+ * + IO operation function
+ * + Peripheral Control function
*
*
@verbatim
@@ -40,36 +40,71 @@
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
[..]
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...)
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
-
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
+ @ref HAL_CEC_RegisterRxCpltCallback().
+
+ Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+
+ For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
+ @ref HAL_CEC_UnRegisterRxCpltCallback().
+
+ By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
+ or @ref HAL_CEC_Init() function.
+
+ When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -86,8 +121,7 @@
* @{
*/
#ifdef HAL_CEC_MODULE_ENABLED
-
-#if defined(STM32F446xx)
+#if defined (CEC)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -147,7 +181,7 @@
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
+ if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
@@ -164,40 +198,62 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
- if(hcec->gState == HAL_CEC_STATE_RESET)
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcec->MspInitCallback == NULL)
+ {
+ hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hcec->MspInitCallback(hcec);
+ }
+#else
+ if (hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
- hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
- hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
/* Enable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
@@ -217,7 +273,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if(hcec == NULL)
+ if (hcec == NULL)
{
return HAL_ERROR;
}
@@ -227,30 +283,43 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
hcec->gState = HAL_CEC_STATE_BUSY;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->MspDeInitCallback == NULL)
+ {
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hcec->MspDeInitCallback(hcec);
+
+#else
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Clear Flags */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
/* Disable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
@@ -283,9 +352,9 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
- hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
}
else
{
@@ -314,7 +383,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -328,7 +397,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -336,6 +405,244 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
the HAL_CEC_MspDeInit can be implemented in the user file
*/
}
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User CEC Callback
+ * To be used instead of the weak predefined callback
+ * @param hcec CEC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CEC Callback
+ * CEC callabck is redirected to the weak predefined callback
+ * @param hcec uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Register CEC RX complete Callback
+ * To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @param pCallback pointer to the Rx transfer compelete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+
+/**
+ * @brief UnRegister CEC RX complete Callback
+ * CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -351,15 +658,15 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
This subsection provides a set of functions allowing to manage the CEC data transfers.
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
(#) The communication is performed using Interrupts.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback() user callback will be executed when a communication
error is detected
(#) API's with Interrupt are :
@@ -378,7 +685,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/**
* @brief Send data in interrupt mode
* @param hcec CEC handle
- * @param InitiatorAddress Initiator logical address
+ * @param InitiatorAddress Initiator address
* @param DestinationAddress destination logical address
* @param pData pointer to input byte data buffer
* @param Size amount of data to be sent in bytes (without counting the header).
@@ -386,13 +693,14 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size)
{
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (hcec->gState == HAL_CEC_STATE_READY)
{
- if((pData == NULL ) && (Size > 0U))
+ if ((pData == NULL) && (Size > 0U))
{
return HAL_ERROR;
}
@@ -408,8 +716,8 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = (uint16_t)Size;
/* in case of no payload (Size = 0), sender is only pinging the system;
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
@@ -419,10 +727,11 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
}
/* send header block */
- hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
+ hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
+
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hcec);
@@ -452,7 +761,7 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
{
hcec->Init.RxBuffer = Rxbuffer;
}
@@ -466,13 +775,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
/* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg = 0U;
+ uint32_t reg;
reg = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if((reg & CEC_FLAG_ARBLST) != RESET)
+ if ((reg & CEC_FLAG_ARBLST) != 0U)
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -480,18 +789,19 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXBR) != RESET)
+ if ((reg & CEC_FLAG_RXBR) != 0U)
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
hcec->RxXferSize++;
/* read received byte */
- *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+ *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
+ hcec->Init.RxBuffer++;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXEND) != RESET)
+ if ((reg & CEC_FLAG_RXEND) != 0U)
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -500,32 +810,38 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
hcec->RxState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->Init.RxBuffer -= hcec->RxXferSize;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->RxCpltCallback(hcec, hcec->RxXferSize);
+#else
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
hcec->RxXferSize = 0U;
}
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXBR) != RESET)
+ if ((reg & CEC_FLAG_TXBR) != 0U)
{
if (hcec->TxXferCount == 0U)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
}
else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
hcec->TxXferCount--;
}
/* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXEND) != RESET)
- {
+ if ((reg & CEC_FLAG_TXEND) != 0U)
+ {
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
/* Tx process is ended, restore hcec->gState to Ready */
@@ -534,32 +850,48 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->TxCpltCallback(hcec);
+#else
HAL_CEC_TxCpltCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
+ CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = reg;
- __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
+ HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
- if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
- hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
- else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
- {
+ else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+ {
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
- }
-
+ }
+ else
+ {
+ /* Nothing todo*/
+ }
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->ErrorCallback(hcec);
+#else
/* Error Call Back */
HAL_CEC_ErrorCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing todo*/
}
-
}
/**
@@ -567,7 +899,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -597,7 +929,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
@@ -619,7 +951,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
[..]
This subsection provides a set of functions allowing to control the CEC.
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
@@ -631,7 +963,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ uint32_t temp1, temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
@@ -656,9 +988,7 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
/**
* @}
*/
-
-#endif /* STM32F446xx */
-
+#endif /* CEC */
#endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cortex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cortex.c
index c7c92fc1442f97e2abb48aa523b796d7f49b411e..e59e2a075570a2d3a1141e49cc1d534db45a053b 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cortex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cortex.c
@@ -68,29 +68,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_crc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_crc.c
index c009510534c9141bff0b492e92ff0a9a07eb3ae1..2c499e59e39ced9a4a4fe66d643326ceb35fbf84 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_crc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_crc.c
@@ -10,49 +10,34 @@
* + Peripheral State functions
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
[..]
- The CRC HAL driver can be used as follows:
-
- (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-
- (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
- a 32-bit data buffer using combination of the previous CRC value
- and the new one.
-
- (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
- a new 32-bit data buffer. This function resets the CRC computation
- unit before starting the computation to avoid getting wrong CRC values.
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++) specify generating polynomial (peripheral default or non-default one)
+ (++) specify initialization value (peripheral default or non-default one)
+ (++) specify input data format
+ (++) specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -64,7 +49,8 @@
* @{
*/
-/** @addtogroup CRC
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
* @{
*/
@@ -75,42 +61,41 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_Exported_Functions
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
-/** @addtogroup CRC_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### Initialization and de-initialization functions #####
- ==============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
- (+) Initialize the CRC MSP
- (+) DeInitialize CRC MSP
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
- * @brief Initializes the CRC according to the specified
- * parameters in the CRC_InitTypeDef and creates the associated handle.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
+ * @brief Initialize the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and create the associated handle.
+ * @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
@@ -118,7 +103,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
- if(hcrc->State == HAL_CRC_STATE_RESET)
+ if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
@@ -126,7 +111,6 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
HAL_CRC_MspInit(hcrc);
}
- /* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Change CRC peripheral state */
@@ -137,15 +121,14 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
}
/**
- * @brief DeInitializes the CRC peripheral.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
+ * @brief DeInitialize the CRC peripheral.
+ * @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
@@ -153,16 +136,28 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+ /* Check the CRC peripheral state */
+ if (hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
+ /* Reset CRC calculation unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* Reset IDR register content */
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
- /* Release Lock */
+ /* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
@@ -171,31 +166,31 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Initializes the CRC MSP.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
+ * @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRC_MspInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
- * @brief DeInitializes the CRC MSP.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
+ * @brief DeInitialize the CRC MSP.
+ * @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRC_MspDeInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
@@ -203,17 +198,20 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
* @}
*/
-/** @addtogroup CRC_Exported_Functions_Group2
- * @brief Peripheral Control functions
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
- (+) Compute the 32-bit CRC value of 32-bit data buffer,
+ (+) compute the 32-bit CRC value of a 32-bit data buffer
using combination of the previous CRC value and the new one.
- (+) Compute the 32-bit CRC value of 32-bit data buffer,
+
+ [..] or
+
+ (+) compute the 32-bit CRC value of a 32-bit data buffer
independently of the previous CRC value.
@endverbatim
@@ -221,106 +219,95 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
*/
/**
- * @brief Computes the 32-bit CRC of 32-bit data buffer using combination
- * of the previous CRC value and the new one.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @param pBuffer pointer to the buffer containing the data to be computed
- * @param BufferLength length of the buffer to be computed
- * @retval 32-bit CRC
+ * @brief Compute the 32-bit CRC value of a 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer.
+ * @param BufferLength input data buffer length (number of uint32_t words).
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcrc);
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
+ temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcrc);
-
/* Return the CRC computed value */
- return hcrc->Instance->DR;
+ return temp;
}
/**
- * @brief Computes the 32-bit CRC of 32-bit data buffer independently
- * of the previous CRC value.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
- * @param pBuffer Pointer to the buffer containing the data to be computed
- * @param BufferLength Length of the buffer to be computed
- * @retval 32-bit CRC
+ * @brief Compute the 32-bit CRC value of a 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer.
+ * @param BufferLength input data buffer length (number of uint32_t words).
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcrc);
+ uint32_t index; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
- /* Reset CRC Calculation Unit */
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
- /* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
+ /* Enter 32-bit input data to the CRC calculator */
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
+ temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcrc);
-
/* Return the CRC computed value */
- return hcrc->Instance->DR;
+ return temp;
}
/**
* @}
*/
-
-/** @addtogroup CRC_Exported_Functions_Group3
- * @brief Peripheral State functions
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### Peripheral State functions #####
- ==============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
+ This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
- * @brief Returns the CRC state.
- * @param hcrc pointer to a CRC_HandleTypeDef structure that contains
- * the configuration information for CRC
+ * @brief Return the CRC handle state.
+ * @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{
+ /* Return CRC handle state */
return hcrc->State;
}
@@ -332,6 +319,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
* @}
*/
+
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp.c
index a3dd3252cc74724a7aa0124a8b99942fbfa223db..390f6924cfe186b76f51700ff688eed61aeceffd 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp.c
@@ -5,10 +5,8 @@
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
- * + Initialization and de-initialization functions
- * + AES processing functions
- * + DES processing functions
- * + TDES processing functions
+ * + Initialization, de-initialization, set config and get config functions
+ * + DES/TDES, AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -18,16 +16,16 @@
##### How to use this driver #####
==============================================================================
[..]
- The CRYP HAL driver can be used as follows:
+ The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
- (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
+ (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
+ (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
@@ -37,60 +35,215 @@
interrupt on the two DMA Streams. The output stream should have higher
priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
- (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
- (##) The encryption/decryption key. It's size depends on the algorithm
- used for encryption/decryption
- (##) The initialization vector (counter). It is not used ECB mode.
+ (#)Initialize the CRYP according to the specified parameters :
+ (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+ (##) The key size: 128, 192 or 256.
+ (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
+ (##) The initialization vector (counter). It is not used in ECB mode.
+ (##) The key buffer used for encryption/decryption.
+ (##) The Header used only in AES GCM and CCM Algorithm for authentication.
+ (##) The HeaderSize The size of header buffer in word.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
i.e. they process the data and wait till the processing is finished,
- e.g. HAL_CRYP_AESCBC_Encrypt()
+ e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
i.e. they process the data under interrupt,
- e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+ e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
(##) DMA mode: encryption and decryption APIs are not blocking functions
i.e. the data transfer is ensured by DMA,
- e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
+ e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
(#)When the processing function is called at first time after HAL_CRYP_Init()
- the CRYP peripheral is initialized and processes the buffer in input.
- At second call, the processing function performs an append of the already
- processed buffer.
- When a new data block is to be processed, call HAL_CRYP_Init() then the
- processing function.
+ the CRYP peripheral is configured and processes the buffer in input.
+ At second call, no need to Initialize the CRYP, user have to get current configuration via
+ HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
+ new parametres, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ [..]
+ The cryptographic processor supports following standards:
+ (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
+ (##)64-bit data block processing
+ (##) chaining modes supported :
+ (+++) Electronic Code Book(ECB)
+ (+++) Cipher Block Chaining (CBC)
+ (##) keys length supported :64-bit, 128-bit and 192-bit.
+ (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
+ (##)128-bit data block processing
+ (##) chaining modes supported :
+ (+++) Electronic Code Book(ECB)
+ (+++) Cipher Block Chaining (CBC)
+ (+++) Counter mode (CTR)
+ (+++) Galois/counter mode (GCM/GMAC)
+ (+++) Counter with Cipher Block Chaining-Message(CCM)
+ (##) keys length Supported :
+ (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
+ (+++) for TinyAES IP: 128-bit and 256-bit
+
+ [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
+ (#) Algorithm supported :
+ (##) Galois/counter mode (GCM)
+ (##) Galois message authentication code (GMAC) :is exactly the same as
+ GCM algorithm composed only by an header.
+ (#) Four phases are performed in GCM :
+ (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+ (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+ computation only.
+ (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+ encryption + data XORing. It works in a similar way for ciphertext (C).
+ (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+ (#) structure of message construction in GCM is defined as below :
+ (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
+ (##) The authenticated header A (also knows as Additional Authentication Data AAD)
+ this part of the message is only authenticated, not encrypted.
+ (##) The plaintext message P is both authenticated and encrypted as ciphertext.
+ GCM standard specifies that ciphertext has same bit length as the plaintext.
+ (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
+ (on 64 bits)
+
+ [..] This section describe The AES Counter with Cipher Block Chaining-Message
+ Authentication Code (CCM) supported by both CRYP1 IP:
+ (#) Specific parameters for CCM :
+
+ (##) B0 block : According to NIST Special Publication 800-38C,
+ The first block B0 is formatted as follows, where l(m) is encoded in
+ most-significant-byte first order(see below table 3)
+
+ (+++) Q: a bit string representation of the octet length of P (plaintext)
+ (+++) q The octet length of the binary representation of the octet length of the payload
+ (+++) A nonce (N), n The octet length of the where n+q=15.
+ (+++) Flags: most significant octet containing four flags for control information,
+ (+++) t The octet length of the MAC.
+ (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
+ the associated data length expressed in bytes (a) defined as below:
+ (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
+ (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
+ (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
+ (##) CTRx block : control blocks
+ (+++) Generation of CTR1 from first block B0 information :
+ equal to B0 with first 5 bits zeroed and most significant bits storing octet
+ length of P also zeroed, then incremented by one ( see below Table 4)
+ (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
+
+ (#) Four phases are performed in CCM for CRYP1 IP:
+ (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
+ (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
+ computation only.
+ (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
+ encryption + data XORing. It works in a similar way for ciphertext (C).
+ (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : Input FIFO transfer completed callback.
+ (+) OutCpltCallback : Output FIFO transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CRYP MspInit.
+ (+) MspDeInitCallback : CRYP MspDeInit.
+
+ By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
+ or @ref HAL_CRYP_Init() function.
+
+ When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ Table 1. Initial Counter Block (ICB)
+ +-------------------------------------------------------+
+ | Initialization vector (IV) | Counter |
+ |----------------|----------------|-----------|---------|
+ 127 95 63 31 0
+
+
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
+
+ Table 2. GCM last block definition
+
+ +-------------------------------------------------------------------+
+ | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
+ |-----------|--------------------|-----------|----------------------|
+ | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
+ |-----------|--------------------|-----------|----------------------|
+
+ Table 3. B0 block
+ Octet Number Contents
+ ------------ ---------
+ 0 Flags
+ 1 ... 15-q Nonce N
+ 16-q ... 15 Q
+
+ the Flags field is formatted as follows:
+
+ Bit Number Contents
+ ---------- ----------------------
+ 7 Reserved (always zero)
+ 6 Adata
+ 5 ... 3 (t-2)/2
+ 2 ... 0 [q-1]3
+
+ Table 4. CTRx block
+ Bit Number Register Contents
+ ---------- --------------- -----------
+ 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
+ bit 0 that is set to 1
+ 95 ...64 CRYP_IV1L[31:0] B0[95:64]
+ 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
+ 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -102,592 +255,424 @@
* @{
*/
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-#if defined(CRYP)
+#if defined (AES) || defined (CRYP)
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYP_Private_define
+/** @addtogroup CRYP_Private_Defines
* @{
*/
-#define CRYP_TIMEOUT_VALUE 1U
+#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
+
+#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
+#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
+
+#if defined(AES)
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+#else /* CRYP */
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
+#endif /* End CRYP or AES */
+
+ /* CTR1 information to use in CCM algorithm */
+#define CRYP_CCM_CTR1_0 0x07FFFFFFU
+#define CRYP_CCM_CTR1_1 0xFFFFFF00U
+#define CRYP_CCM_CTR1_2 0x00000001U
+
+
/**
* @}
*/
+
/* Private macro -------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Macros
+ * @{
+ */
+
+#if defined(CRYP)
+
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+
+#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
+
+#else /*AES*/
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
+ (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
+ }while(0)
+#endif /* End AES or CRYP*/
+
+
+/**
+ * @}
+ */
+
+/* Private struct -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup CRYP_Private_Functions_prototypes
* @{
*/
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
+#endif /* AES or GCM CCM defined*/
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
+#if defined (CRYP)
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#endif /* GCM CCM defined*/
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#else /*AES*/
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+#endif /* End CRYP or AES */
+
/**
* @}
*/
+/* Exported functions ---------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup CRYP_Private_Functions
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ========================================================================================
+ ##### Initialization, de-initialization and Set and Get configuration functions #####
+ ========================================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRYP
+ (+) DeInitialize the CRYP
+ (+) Initialize the CRYP MSP
+ (+) DeInitialize the CRYP MSP
+ (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
+ Parameters which are configured in This section are :
+ (+) Key size
+ (+) Data Type : 32,16, 8 or 1bit
+ (+) AlgoMode :
+ - for CRYP1 IP :
+ ECB and CBC in DES/TDES Standard
+ ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
+ - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
+ (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle
- * @retval None
+@endverbatim
+ * @{
*/
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
/**
- * @brief Writes the Key in Key registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Initializes the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Key Pointer to Key buffer
- * @param KeySize Size of Key
- * @retval None
+ * @retval HAL status
*/
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
- uint32_t keyaddr = (uint32_t)Key;
-
- switch(KeySize)
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
{
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
+ return HAL_ERROR;
}
-}
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param InitVector Pointer to InitVector/InitCounter buffer
- * @param IVSize Size of the InitVector/InitCounter
- * @retval None
- */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+ assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+ assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
- switch(IVSize)
+ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
{
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
- break;
- /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- case CRYP_KEYSIZE_256B:
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- break;
- default:
- break;
- }
-}
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
-/**
- * @brief Process Data: Writes Input data in polling mode and read the output data
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer
- * @param Ilength Length of the Input buffer, must be a multiple of 16.
- * @param Output Pointer to the returned buffer
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
- uint32_t i = 0U;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ if(hcryp->MspInitCallback == NULL)
+ {
+ hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
+ }
- for(i=0U; (i < Ilength); i+=16U)
+ /* Init the low level hardware */
+ hcryp->MspInitCallback(hcryp);
+ }
+#else
+ if(hcryp->State == HAL_CRYP_STATE_RESET)
{
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
+ /* Allocate lock resource and initialize it */
+ hcryp->Lock = HAL_UNLOCKED;
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Init the low level hardware */
+ HAL_CRYP_MspInit(hcryp);
+ }
+ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type and Algorithm */
+#if defined (CRYP)
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
+#else /*AES*/
+
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
+#endif /* End AES or CRYP*/
+
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Process Data: Write Input data in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief De-Initializes the CRYP peripheral.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Input Pointer to the Input buffer
- * @param Ilength Length of the Input buffer, must be a multiple of 8
- * @param Output Pointer to the returned buffer
- * @param Timeout Specify Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0U;
+ /* Check the CRYP handle allocation */
+ if(hcryp == NULL)
+ {
+ return HAL_ERROR;
+ }
- uint32_t i = 0U;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
+
+ /* Reset CrypInCount and CrypOutCount */
+ hcryp->CrypInCount = 0;
+ hcryp->CrypOutCount = 0;
+ hcryp->CrypHeaderCount =0;
+
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- for(i=0U; (i < Ilength); i+=8U)
+ if(hcryp->MspDeInitCallback == NULL)
{
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
+ }
+ /* DeInit the low level hardware */
+ hcryp->MspDeInitCallback(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+#else
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ HAL_CRYP_MspDeInit(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Configure the CRYP according to the specified
+ * parameters in the CRYP_ConfigTypeDef
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
* the configuration information for CRYP module
- * @param inputaddr address of the Input buffer
- * @param Size Size of the Input buffer, must be a multiple of 16.
- * @param outputaddr address of the Output buffer
- * @retval None
+ * @retval HAL status
*/
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+ /* Check the CRYP handle allocation */
+ if((hcryp == NULL)|| (pConf == NULL) )
+ {
+ return HAL_ERROR;
+ }
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Check parameters */
+ assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
+ assert_param(IS_CRYP_DATATYPE(pConf->DataType));
+ assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Enable In DMA request */
- hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
+ /* Set CRYP parameters */
+ hcryp->Init.DataType = pConf->DataType;
+ hcryp->Init.pKey = pConf->pKey;
+ hcryp->Init.Algorithm = pConf->Algorithm;
+ hcryp->Init.KeySize = pConf->KeySize;
+ hcryp->Init.pInitVect = pConf->pInitVect;
+ hcryp->Init.Header = pConf->Header;
+ hcryp->Init.HeaderSize = pConf->HeaderSize;
+ hcryp->Init.B0 = pConf->B0;
+ hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
- /* Enable Out DMA request */
- hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+ /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/
+#if defined (CRYP)
-}
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
-/**
- * @brief Sets the CRYP peripheral in DES ECB mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
+#else /*AES*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
- /* Set the key */
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
+ /*clear error flags*/
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#endif /* End AES or CRYP */
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
-/**
- * @brief Sets the CRYP peripheral in DES CBC mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
+ /* Reset Error Code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
- /* Set the key */
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4U));
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
+ /* Set the default CRYP phase */
+ hcryp->Phase = CRYP_PHASE_READY;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
}
}
/**
- * @brief Sets the CRYP peripheral in TDES ECB mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Get CRYP Configuration parameters in associated handle.
+ * @param pConf: pointer to a CRYP_ConfigTypeDef structure
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
+ * @retval HAL status
*/
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Check the CRYP handle allocation */
+ if((hcryp == NULL)|| (pConf == NULL) )
{
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ return HAL_ERROR;
}
-}
-/**
- * @brief Sets the CRYP peripheral in TDES CBC mode
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Direction Encryption or decryption
- * @retval None
- */
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-}
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
-/**
- * @}
- */
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions
- * @{
- */
+ /* Get CRYP parameters */
+ pConf->DataType = hcryp->Init.DataType;
+ pConf->pKey = hcryp->Init.pKey;
+ pConf->Algorithm = hcryp->Init.Algorithm;
+ pConf->KeySize = hcryp->Init.KeySize ;
+ pConf->pInitVect = hcryp->Init.pInitVect;
+ pConf->Header = hcryp->Init.Header ;
+ pConf->HeaderSize = hcryp->Init.HeaderSize;
+ pConf->B0 = hcryp->Init.B0;
+ pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and de-initialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP according to the specified parameters
- in the CRYP_InitTypeDef and creates the associated handle
- (+) DeInitialize the CRYP peripheral
- (+) Initialize the CRYP MSP
- (+) DeInitialize CRYP MSP
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
-@endverbatim
- * @{
- */
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Initializes the CRYP according to the specified
- * parameters in the CRYP_InitTypeDef and creates the associated handle.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
+ /* Return function status */
+ return HAL_OK;
}
-
- /* Check the parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ else
{
- /* Allocate lock resource and initialize it */
- hcryp->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the key size and data type*/
- CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
-/**
- * @brief DeInitializes the CRYP peripheral.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
-
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
-
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
}
-
/**
* @brief Initializes the CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
@@ -695,6 +680,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspInit could be implemented in the user file
*/
@@ -702,7 +688,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
/**
* @brief DeInitializes CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
@@ -710,2038 +696,2904 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User CRYP Callback
+ * To be used instead of the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcryp);
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = pCallback;
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CRYP Callback
+ * CRYP callback is redirected to the weak predefined callback
+ * @param hcryp cryp handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+ * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcryp);
+
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+ hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
+ break;
+
+ case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+ hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
+ break;
+
+ case HAL_CRYP_ERROR_CB_ID :
+ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hcryp->State == HAL_CRYP_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CRYP_MSPINIT_CB_ID :
+ hcryp->MspInitCallback = HAL_CRYP_MspInit;
+ break;
+
+ case HAL_CRYP_MSPDEINIT_CB_ID :
+ hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcryp);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
+/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
* @brief processing functions.
*
@verbatim
==============================================================================
- ##### AES processing functions #####
+ ##### Encrypt Decrypt functions #####
==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES-128/192/256 using chaining modes
- (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
+ [..] This section provides API allowing to Encrypt/Decrypt Data following
+ Standard DES/TDES or AES, and Algorithm configured by the user:
+ (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
+ - Electronic Code Book(ECB)
+ - Cipher Block Chaining (CBC)
+ (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
+ - Electronic Code Book(ECB)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Cipher Block Chaining (CBC)
+ - Counter mode (CTR)
+ - Galois/counter mode (GCM)
+ - Counter with Cipher Block Chaining-Message(CCM)
[..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+ (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+ (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(ciphertext)
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint32_t algo;
+ HAL_StatusTypeDef status;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
{
- return HAL_TIMEOUT;
+ hcryp->Size = Size;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+#if defined (CRYP)
+ /* Set Encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- /* Return function status */
- return HAL_OK;
-}
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
-/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+ /* Statrt DES/TDES encryption process */
+ status = CRYP_TDES_Process(hcryp,Timeout);
+ break;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process(hcryp, Timeout);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ break;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ case CRYP_AES_CCM:
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp,Timeout);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#else /*AES*/
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ switch(algo)
+ {
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ /* AES encryption */
+ status = CRYP_AES_Encrypt(hcryp, Timeout);
+ break;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ case CRYP_AES_GCM_GMAC:
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process (hcryp,Timeout) ;
+ break;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ case CRYP_AES_CCM:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process(hcryp,Timeout);
+ break;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
}
+#endif /*end AES or CRYP */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
}
-
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(plaintext)
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ HAL_StatusTypeDef status;
+ uint32_t algo;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
}
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ switch(algo)
{
- return HAL_TIMEOUT;
- }
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /*Set Initialization Vector (IV)*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
+ /* Start DES/TDES decryption process */
+ status = CRYP_TDES_Process(hcryp, Timeout);
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ break;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process (hcryp, Timeout) ;
+ break;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ case CRYP_AES_CCM:
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+#else /*AES*/
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set Decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
- return HAL_TIMEOUT;
- }
- }
- }
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ switch(algo)
+ {
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* AES decryption */
+ status = CRYP_AES_Decrypt(hcryp, Timeout);
+ break;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ case CRYP_AES_GCM_GMAC:
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process (hcryp, Timeout) ;
+ break;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ case CRYP_AES_CCM:
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process(hcryp, Timeout);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
}
+#endif /* End AES or CRYP */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ if (status == HAL_OK)
+ {
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in interrupt mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word
+ * @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Change the CRYP state */
+ /* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* algo get algorithm selected */
+ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ switch(algo)
{
- return HAL_TIMEOUT;
- }
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Return function status */
- return HAL_OK;
-}
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Enable CRYP to start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+ break;
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
+ }
+
+#else /* AES */
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
+ /* AES encryption */
+ status = CRYP_AES_Encrypt_IT(hcryp);
+ break;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ case CRYP_AES_GCM_GMAC:
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ case CRYP_AES_CCM:
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /*end AES or CRYP*/
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in itnterrupt mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
- /* Set the CRYP peripheral in AES CBC mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+#if defined (CRYP)
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
+
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP and start DES/TDES process*/
+ __HAL_CRYP_ENABLE(hcryp);
+
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ case CRYP_AES_CCM:
+
+ /* AES CCMdecryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+#else /*AES*/
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_IT(hcryp);
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_IT (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_IT(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in DMA mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Input: Pointer to the input buffer (plaintext)
+ * @param Size: Length of the plaintext buffer in word.
+ * @param Output: Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state Busy */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ hcryp->Size = Size;
+ }
+
+#if defined (CRYP)
+
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ switch(algo)
+ {
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ }
/* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+#else /*AES*/
+ /* Set encryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
+
+ switch(algo)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the Initialization Vector*/
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+ }
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for AES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM encryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM encryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
+
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
-
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in DMA mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
+ * @param Input: Pointer to the input buffer (ciphertext )
+ * @param Size: Length of the plaintext buffer in word
+ * @param Output: Pointer to the output buffer(plaintext)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
{
- uint32_t tickstart = 0U;
-
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t algo;
+ HAL_StatusTypeDef status = HAL_OK;
if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
+ /* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+ hcryp->CrypInCount = 0U;
+ hcryp->CrypOutCount = 0U;
+ hcryp->pCrypInBuffPtr = Input;
+ hcryp->pCrypOutBuffPtr = Output;
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Calculate Size parameter in Byte*/
+ if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+ {
+ hcryp->Size = Size * 4U;
+ }
+ else
+ {
+ hcryp->Size = Size;
+ }
+
+#if defined (CRYP)
+
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ switch(algo)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ case CRYP_DES_ECB:
+ case CRYP_DES_CBC:
+ case CRYP_TDES_ECB:
+ case CRYP_TDES_CBC:
+
+ /*Set Key */
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ }
- return HAL_TIMEOUT;
+ /* Set the Initialization Vector*/
+ if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+ {
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
}
+
+ /* Flush FIFO */
+ HAL_CRYP_FIFO_FLUSH(hcryp);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Start DMA process transfer for DES/TDES */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ break;
+
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
+
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ case CRYP_AES_GCM:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+#endif /* GCM CCM defined*/
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+#else /*AES*/
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
+ /* Set decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* algo get algorithm selected */
+ algo = hcryp->Instance->CR & AES_CR_CHMOD;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ switch(algo)
+ {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ case CRYP_AES_ECB:
+ case CRYP_AES_CBC:
+ case CRYP_AES_CTR:
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* AES decryption */
+ status = CRYP_AES_Decrypt_DMA(hcryp);
+ break;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ case CRYP_AES_GCM_GMAC:
+ /* AES GCM decryption */
+ status = CRYP_AESGCM_Process_DMA (hcryp) ;
+ break;
+
+ case CRYP_AES_CCM:
+ /* AES CCM decryption */
+ status = CRYP_AESCCM_Process_DMA(hcryp);
+ break;
+
+ default:
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ break;
}
+#endif /* End AES or CRYP */
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ status = HAL_ERROR;
}
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @}
+ */
+
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ * @brief CRYP IRQ handler.
+ *
+@verbatim
+ ==============================================================================
+ ##### CRYP IRQ handler management #####
+ ==============================================================================
+[..] This section provides CRYP IRQ handler and callback functions.
+ (+) HAL_CRYP_IRQHandler CRYP interrupt request
+ (+) HAL_CRYP_InCpltCallback input data transfer complete callback
+ (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
+ (+) HAL_CRYP_ErrorCallback CRYP error callback
+ (+) HAL_CRYP_GetState return the CRYP state
+ (+) HAL_CRYP_GetError return the CRYP error code
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles cryptographic interrupt request.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
+#if defined (CRYP)
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U))
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ CRYP_TDES_IT(hcryp); /* DES or TDES*/
+ }
+ else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ CRYP_AES_IT(hcryp); /*AES*/
+ }
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) )
+ {
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
{
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
+#endif /* GCM CCM defined*/
+ else
+ {
+ /* Nothing to do */
+ }
+ }
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
-
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+#else /*AES*/
+ if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U))
+ {
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Clear computation complete flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* if header phase */
+ if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER )
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
}
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
+ else if(hcryp->Init.Algorithm == CRYP_AES_CCM)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* if header phase */
+ if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount )
+ {
+ CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
+ }
+ else /* if payload phase */
+ {
+ CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
+ }
+ }
+ else /* AES Algorithm ECB,CBC or CTR*/
+ {
+ CRYP_AES_IT(hcryp);
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ /* Check if error occurred */
+ if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ /* If write Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
+ }
+ /* If read Error occurred */
+ if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET)
+ {
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
+#endif /* End AES or CRYP */
+}
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief Return the CRYP error code.
+ * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for the CRYP IP
+ * @retval CRYP error code
+ */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+ return hcryp->ErrorCode;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
+ * @brief Returns the CRYP state.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval HAL state
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ return hcryp->State;
+}
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+/**
+ * @brief Input FIFO transfer completed callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_InCpltCallback could be implemented in the user file
+ */
+}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+/**
+ * @brief Output FIFO transfer completed callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_OutCpltCallback could be implemented in the user file
+ */
+}
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+/**
+ * @brief CRYP error callback.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval None
+ */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcryp);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CRYP_ErrorCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+ * @{
+ */
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ #if defined (CRYP)
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+/**
+ * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout: specify Timeout value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t temp; /* Temporary CrypOutBuff */
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
+ /*Start processing*/
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Temporary CrypInCount Value */
+ incount = hcryp->CrypInCount;
+ /* Write plain data and get cipher data */
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
+
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & errorCode*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
}
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
}
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
+ * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @retval none
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t temp; /* Temporary CrypOutBuff */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Write input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interruption */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
}
else
{
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
+#endif /* CRYP */
+
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
+ * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Write plain Ddta and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ if(hcryp->Size != 0U)
+ {
+#if defined (AES)
- /* Set the CRYP peripheral in AES ECB mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+#else /* CRYP */
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+#endif /* End AES or CRYP */
}
else
{
- return HAL_ERROR;
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pPlainData Pointer to the plaintext buffer
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure
+ * @param Timeout: Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & Key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Wait for BUSY flag to be raised */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_TIMEOUT;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-
- /* Set the CRYP peripheral in AES ECB decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+#endif /* End AES or CRYP */
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Return function status */
- return HAL_OK;
- }
- else
+ while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
{
- return HAL_ERROR;
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
}
-}
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- /* Set the CRYP peripheral in AES Key mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
+ count-- ;
+ if(count == 0U)
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Reset the ALGOMODE bits*/
- CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set the CRYP peripheral in AES CBC decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set decryption & key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for BUSY flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
+ }
- /* Return function status */
- return HAL_OK;
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
+
+ /* Set IV */
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+ if(hcryp->Size != 0U)
+ {
+
+#if defined (AES)
+
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+#else /* CRYP */
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#endif /* End AES or CRYP */
}
else
{
- return HAL_ERROR;
+ /* Process locked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
}
-}
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+ /* Key preparation for ECB/CBC */
+ if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (AES)
+ if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
+ {
+ /* Set key preparation for decryption operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Return to decryption operating mode(Mode 3)*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
+ }
+ else /*Mode 4 : decryption & key preparation*/
{
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES CTR mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
+ /* Set decryption & Key preparation operating mode*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
+ }
+#else /* CRYP */
+ /* change ALGOMODE to key preparation for decryption*/
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
- /* Set the Initialization Vector */
- CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+ /* Wait for BUSY flag to be raised */
+ count = CRYP_TIMEOUT_KEYPREPARATION;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Turn back to ALGOMODE of the configuration */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
+ }
+ else /*Algorithm CTR */
+ {
+ /* Set the Key*/
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+ }
- /* Return function status */
- return HAL_OK;
+ if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+ {
+ /* Set the Initialization Vector*/
+#if defined (AES)
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#else /* CRYP */
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+#endif /* End AES or CRYP */
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if(hcryp->Size != 0U)
+ {
+ /* Set the input and output addresses and start DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
else
{
- return HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
}
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @}
+ * @brief DMA CRYP input data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### DES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using DES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using ECB or CBC chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+ in the DMACR register */
+#if defined (CRYP)
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-@endverbatim
- * @{
- */
+#else /* AES */
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
+ if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+#endif /* End AES or CRYP */
+
+ /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @brief DMA CRYP output data process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Disable the DMA transfer for output FIFO request by resetting
+ the DOEN bit in the DMACR register */
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0U);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
+ if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
+ {
+ /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_DISABLE(hcryp);
+ }
+
+#else /*NO GCM CCM */
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
+#endif /* GCM CCM defined*/
+#else /* AES */
+
+ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
+
+ if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
{
- return HAL_TIMEOUT;
+ /* Disable CRYP (not allowed in GCM)*/
+ __HAL_CRYP_DISABLE(hcryp);
}
+#endif /* End AES or CRYP */
- /* Change the CRYP state */
+ /* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
+ /* Call output data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @brief DMA CRYP communication error callback.
+ * @param hdma: DMA handle
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Change the CRYP peripheral state */
+ hcryp->State= HAL_CRYP_STATE_READY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+#if defined (AES)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* AES */
- /* Return function status */
- return HAL_OK;
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Set the DMA configuration and start the DMA transfer
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @param inputaddr: address of the input buffer
+ * @param Size: size of the input buffer, must be a multiple of 16.
+ * @param outputaddr: address of the output buffer
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+
+ /* Set the DMA output error callback */
+ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0U);
+#if defined (CRYP)
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Enable the input DMA Stream */
+ if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
{
- return HAL_TIMEOUT;
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+ /* Enable the output DMA Stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable In/Out DMA request */
+ hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#else /* AES */
- /* Return function status */
- return HAL_OK;
+ if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
+ {
+ /* Enable CRYP (not allowed in GCM & CCM)*/
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Enable the DMA output stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+ /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Enable In and Out DMA requests */
+ if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
+ {
+ /* Enable only In DMA requests for CCM*/
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN ));
+ }
+ else
+ {
+ /* Enable In and Out DMA requests */
+ SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
+ }
+#endif /* End AES or CRYP */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Process Data: Write Input data in polling mode and used in AES functions.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
+ * @param Timeout: Specify Timeout value
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ uint32_t temp; /* Temporary CrypOutBuff */
+#if defined (CRYP)
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#if defined (CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /*Temporary CrypOutCount Value*/
+ incount = hcryp->CrypInCount;
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
{
- return HAL_TIMEOUT;
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change state & error code*/
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Return function status */
- return HAL_OK;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ }
+
+#else /* AES */
+
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+
+#endif /* End AES or CRYP */
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @brief Handle CRYP block input/output data handling under interruption.
+ * @note The function is called under interruption only, once
+ * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t temp; /* Temporary CrypOutBuff */
+#if defined (CRYP)
+ uint16_t incount; /* Temporary CrypInCount Value */
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if(hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#if defined (CRYP)
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /*Temporary CrypOutCount Value*/
+ incount = hcryp->CrypInCount;
+ if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0U);
+ if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
+#else /*AES*/
+
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+
+ if(hcryp->CrypOutCount == (hcryp->Size/4U))
{
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+ /* Disable Computation Complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
+
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
+
+ /* Call Output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- }
+ else
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ if(hcryp->CrypInCount == (hcryp->Size/4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+#endif /* End AES or CRYP */
- /* Return function status */
- return HAL_OK;
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Writes Key in Key registers.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
+ * @param KeySize: Size of Key
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0U);
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
+#if defined (CRYP)
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ switch(KeySize)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
+ break;
+ case CRYP_KEYSIZE_192B:
+ hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ break;
+ default:
+ break;
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+#else /*AES*/
+ switch(KeySize)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ case CRYP_KEYSIZE_256B:
+ hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3);
+ hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4);
+ hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5);
+ hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6);
+ hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7);
+ break;
+ case CRYP_KEYSIZE_128B:
+ hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey);
+ hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1);
+ hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2);
+ hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3);
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ break;
+ default:
+ break;
}
-
- /* Return function status */
- return HAL_OK;
+#endif /* End AES or CRYP */
}
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart;
+ uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /****************************** Init phase **********************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+#if defined(CRYP)
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /*Wait for the CRYPEN bit to be cleared*/
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+
+#else /* AES */
+ /* Workaround 1 : only AES.
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
+
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /* just wait for hash computation */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Return function status */
- return HAL_OK;
-}
+#endif /* End AES or CRYP */
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /************************ Header phase *************************************/
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ return HAL_ERROR;
+ }
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /*************************Payload phase ************************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#if defined(CRYP)
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Return function status */
- return HAL_OK;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+#endif /* End AES or CRYP */
+
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
+
+ /* Write input data and get output Data */
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
+
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state & error code */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
+ 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp,Timeout);
}
/* Return function status */
@@ -2749,2409 +3601,2647 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t
}
/**
- * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ __IO uint32_t count = 0U;
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif /* AES */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount =0U;
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /******************************* Init phase *********************************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set CRYP peripheral in DES ECB encryption mode */
- CRYP_SetDESECBMode(hcryp, 0U);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+#else /* AES */
- /* Set CRYP peripheral in DES CBC encryption mode */
- CRYP_SetDESCBCMode(hcryp, 0U);
+ /* Workaround 1 : only AES
+ Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set CRYP peripheral in DES ECB decryption mode */
- CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
+#endif /* End AES or CRYP */
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /***************************** Header phase *********************************/
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#if defined(CRYP)
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+#else /* AES */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Set CRYP peripheral in DES CBC decryption mode */
- CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Enable computation complete flag and error interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else
+ if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
{
- return HAL_ERROR;
- }
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @}
- */
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions
- * @brief processing functions.
- *
-@verbatim
- ==============================================================================
- ##### TDES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
- (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Write the payload Input block in the IN FIFO */
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-@endverbatim
- * @{
- */
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(hcryp->CrypInCount == ( hcryp->Size/4U))
+ {
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 16Bytes : first block is the last block*/
+ {
+ /* Workaround not implemented*/
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U- (uint32_t)(hcryp->Size);
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0U);
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if ((hcryp->Init.HeaderSize) < 4U)
+ {
+ for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ else if ((hcryp->Init.HeaderSize) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ }
+ else
{
- return HAL_TIMEOUT;
+ /* Nothing to do */
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
/* Return function status */
return HAL_OK;
}
+
/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ __IO uint32_t count = 0U;
+ uint32_t wordsize;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /*************************** Init phase ************************************/
- /* Enable CRYP */
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+#if defined(CRYP)
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+
+ /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Cypher Data and Get Plain Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_TIMEOUT;
- }
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode
- * then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+#else /* AES */
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /*Workaround 1 : only AES
+ Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
+ enabling the IP, datatype different from 32 bits can be configured.*/
+ /* Select DATATYPE 32 */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0U);
+ /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+ hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect);
+ hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1);
+ hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2);
+ hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3);
- /* Enable CRYP */
+ /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Write Plain Data and Get Cypher Data */
- if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+ /* just wait for hash computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode
- * then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+#endif /* End AES or CRYP */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /************************ Header phase *************************************/
- /* Write Cypher Data and Get Plain Data */
- if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
+ if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /************************ Payload phase ************************************/
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+#if defined(CRYP)
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0U);
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+#endif /* CRYP */
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ if(hcryp->Size != 0U)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
+ /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
+ {
+ wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ;
+
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- /* Disable IT */
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call the Output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
}
/* Return function status */
return HAL_OK;
}
+
/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption processing in polling mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t tickstart;
+ uint32_t wordsize= (uint32_t)(hcryp->Size)/4U;
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#if defined(AES)
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+#endif /* AES */
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /********************** Init phase ******************************************/
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0U);
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Return function status */
- return HAL_OK;
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
}
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ /*Wait for the CRYPEN bit to be cleared*/
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
+#else /* AES */
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* configured encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+
+ /* wait until the end of computation */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Return function status */
- return HAL_OK;
-}
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* From that point the whole message must be processed, first the Header then the payload.
+ First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
- if(hcryp->State == HAL_CRYP_STATE_READY)
+ if (hcryp->Init.HeaderSize != 0U)
{
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write Header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
- /* Enable CRYP */
- __HAL_CRYP_ENABLE(hcryp);
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
- }
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- hcryp->pCrypInBuffPtr += 8U;
- hcryp->CrypInCount -= 8U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
}
- else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+ /* Then the payload: cleartext payload (not the ciphertext payload).
+ Write input Data, no output Data to get */
+ if (hcryp->Size != 0U)
{
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
- hcryp->pCrypOutBuffPtr += 8U;
- hcryp->CrypOutCount -= 8U;
- if(hcryp->CrypOutCount == 0U)
+ if ((hcryp->Size % 16U) != 0U)
{
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Disable CRYP */
- __HAL_CRYP_DISABLE(hcryp);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
}
- }
-
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Set CRYP peripheral in TDES ECB encryption mode */
- CRYP_SetTDESECBMode(hcryp, 0U);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
- /* Return function status */
- return HAL_OK;
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ loopcounter++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ }
}
- else
+#endif /* End AES or CRYP */
+
+#if defined(CRYP)
+
+ /************************* Header phase *************************************/
+ /* Header block(B1) : associated data length expressed in bytes concatenated
+ with Associated Data (A)*/
+
+ if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
-}
-/**
- * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ /********************** Payload phase ***************************************/
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Set CRYP peripheral in TDES CBC encryption mode */
- CRYP_SetTDESCBCMode(hcryp, 0U);
+ if ((hcryp->Size % 16U) != 0U)
+ {
+ /* recalculate wordsize */
+ wordsize = ((wordsize/4U)*4U) ;
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Write input data and get output data */
+ while((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
+ {
+ /* Write plain data and get cipher data */
+ CRYP_AES_ProcessData(hcryp,Timeout);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
}
- else
+
+ if ((hcryp->Size % 16U) != 0U)
{
- return HAL_ERROR;
+ /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
+ 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
+ is selected, then the TAG message will be wrong.*/
+ CRYP_Workaround(hcryp,Timeout);
}
+#endif /* CRYP */
+
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption process in interrupt mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pCypherData Pointer to the cyphertext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+#if defined(CRYP)
+ __IO uint32_t count = 0U;
+#endif /* CRYP */
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
+
+#if defined(CRYP)
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+ /************ Init phase ************/
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set CRYP peripheral in TDES ECB decryption mode */
- CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
}
else
{
- return HAL_ERROR;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
}
-}
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
+
+ /* Enable CRYP */
+ __HAL_CRYP_ENABLE(hcryp);
+
+#else /* AES */
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* configured mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
+
+ /* Enable interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+
+#endif /* End AES or CRYP */
+
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM encryption/decryption process in DMA mode
+ * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 8
- * @param pPlainData Pointer to the plaintext buffer
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
+ uint32_t wordsize;
+ __IO uint32_t count = 0U;
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
+#if defined(CRYP)
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /************************** Init phase **************************************/
- /* Set CRYP peripheral in TDES CBC decryption mode */
- CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
+ CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT);
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Set the initialization vector (IV) with CTR1 information */
+ hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+ hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+ hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+ hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2;
- /* Return function status */
- return HAL_OK;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ /*Write the B0 packet into CRYP_DIN Register*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16);
+ hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16);
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0));
+ hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2));
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3));
}
else
{
- return HAL_ERROR;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3);
}
-}
-/**
- * @}
- */
+ /*Wait for the CRYPEN bit to be cleared*/
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions
- * @brief DMA callback functions.
- *
-@verbatim
- ==============================================================================
- ##### DMA callback functions #####
- ==============================================================================
- [..] This section provides DMA callback functions:
- (+) DMA Input data transfer complete
- (+) DMA Output data transfer complete
- (+) DMA error
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-@endverbatim
- * @{
- */
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
-/**
- * @brief Input FIFO transfer completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_InCpltCallback could be implemented in the user file
- */
-}
+#else /* AES */
-/**
- * @brief Output FIFO transfer completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_OutCpltCallback could be implemented in the user file
- */
-}
+ /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief CRYP error callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CRYP_ErrorCallback could be implemented in the user file
- */
-}
+ /* configured CCM chaining mode and encryption mode */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
-/**
- * @}
- */
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management
- * @brief CRYP IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### CRYP IRQ handler management #####
- ==============================================================================
-[..] This section provides CRYP IRQ handler function.
+ /* Set the initialization vector with zero values*/
+ hcryp->Instance->IVR3 = 0U;
+ hcryp->Instance->IVR2 = 0U;
+ hcryp->Instance->IVR1 = 0U;
+ hcryp->Instance->IVR0 = 0U;
-@endverbatim
- * @{
- */
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
-/**
- * @brief This function handles CRYP interrupt request.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+ /*Write the B0 packet into CRYP_DIN*/
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2);
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3);
+
+ /* wait until the end of computation */
+ count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+ do
{
- case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
- HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ count-- ;
+ if(count == 0U)
+{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
- HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
- HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+}
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
- HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
- HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+#endif /* AES */
- case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
- HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /********************* Header phase *****************************************/
- case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
- HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
- HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /******************** Payload phase *****************************************/
- case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
- HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
- HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+#if defined(CRYP)
- case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
- HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
- HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
- HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+#endif /* CRYP */
- case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
- HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
+ if(hcryp->Size != 0U)
+ {
+ /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Set the input and output addresses and start DMA transfer */
+ if ((hcryp->Size % 16U) == 0U)
+ {
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else
+ {
+ wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ;
- default:
- break;
+ /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
+ CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
}
-}
+ else /*Size = 0*/
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
-/**
- * @}
- */
-
-/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
-@endverbatim
- * @{
- */
+ /* Return function status */
+ return HAL_OK;
+}
/**
- * @brief Returns the CRYP state.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Sets the payload phase in iterrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @retval HAL state
+ * @retval state
*/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
- return hcryp->State;
-}
+ uint32_t loopcounter;
+ uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t lastwordsize;
+ uint32_t npblb;
+ #if defined(AES)
+ uint16_t outcount; /* Temporary CrypOutCount Value */
+#endif /* AES */
-/**
- * @}
- */
+ /***************************** Payload phase *******************************/
+#if defined(CRYP)
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI);
-/**
- * @}
- */
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
-#endif /* CRYP */
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
-#if defined (AES)
+ else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-/** @defgroup AES AES
- * @brief AES HAL module driver.
- * @{
- */
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ if(hcryp->CrypOutCount < (hcryp->Size/4U))
+ {
+ /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUT;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private functions --------------------------------------------------------*/
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
-static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
-/**
- * @}
- */
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ else if ((hcryp->Size %16U )!= 0U)
+ {
+ /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
+ Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
-/* Exported functions ---------------------------------------------------------*/
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
- ==============================================================================
- ##### Initialization and deinitialization functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CRYP according to the specified parameters
- in the CRYP_InitTypeDef and creates the associated handle
- (+) DeInitialize the CRYP peripheral
- (+) Initialize the CRYP MSP (MCU Specific Package)
- (+) De-Initialize the CRYP MSP
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- [..]
- (@) Specific care must be taken to format the key and the Initialization Vector IV!
-
- [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
- b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
- (+) as a sequence of words where the MSB word comes first (occupies the
- lowest memory address)
- (+) where each word is byte-swapped:
- (++) address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120
- (++) address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88
- (++) address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56
- (++) address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24
- [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
- The 4 32-bit words that make the key must be stored as follows in MCU memory:
- (+) address n+0 : 0x B12 B13 B14 B15
- (+) address n+4 : 0x B8 B9 B10 B11
- (+) address n+8 : 0x B4 B5 B6 B7
- (+) address n+C : 0x B0 B1 B2 B3
- [..] which leads to the expected setting
- (+) AES_KEYR3 = 0x B15 B14 B13 B12
- (+) AES_KEYR2 = 0x B11 B10 B9 B8
- (+) AES_KEYR1 = 0x B7 B6 B5 B4
- (+) AES_KEYR0 = 0x B3 B2 B1 B0
-
- [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
- The 8 32-bit words that make the key must be stored as follows in MCU memory:
- (+) address n+00 : 0x B28 B29 B30 B31
- (+) address n+04 : 0x B24 B25 B26 B27
- (+) address n+08 : 0x B20 B21 B22 B23
- (+) address n+0C : 0x B16 B17 B18 B19
- (+) address n+10 : 0x B12 B13 B14 B15
- (+) address n+14 : 0x B8 B9 B10 B11
- (+) address n+18 : 0x B4 B5 B6 B7
- (+) address n+1C : 0x B0 B1 B2 B3
- [..] which leads to the expected setting
- (+) AES_KEYR7 = 0x B31 B30 B29 B28
- (+) AES_KEYR6 = 0x B27 B26 B25 B24
- (+) AES_KEYR5 = 0x B23 B22 B21 B20
- (+) AES_KEYR4 = 0x B19 B18 B17 B16
- (+) AES_KEYR3 = 0x B15 B14 B13 B12
- (+) AES_KEYR2 = 0x B11 B10 B9 B8
- (+) AES_KEYR1 = 0x B7 B6 B5 B4
- (+) AES_KEYR0 = 0x B3 B2 B1 B0
-
- [..] Initialization Vector IV (4 32-bit words) format must follow the same as
- that of a 128-bit long key.
-
- [..]
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for(loopcounter = 0U; loopcounter < 4U; loopcounter++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer */
+ temp= hcryp->Instance->DOUT;
-@endverbatim
- * @{
- */
+ /*get CrypOutBuff from temporary buffer */
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp;
+ hcryp->CrypOutCount++;
+ }
+ }
+ if(hcryp->CrypOutCount >= (hcryp->Size/4U))
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI);
-/**
- * @brief Initialize the CRYP according to the specified
- * parameters in the CRYP_InitTypeDef and initialize the associated handle.
- * @note Specific care must be taken to format the key and the Initialization Vector IV
- * stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations
- * hereabove.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Check the instance */
- assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Check the parameters */
- assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
- assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
- assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));
- /* ChainingMode parameter is irrelevant when mode is set to Key derivation */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));
- }
- assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));
-
- /*========================================================*/
- /* Check the proper operating/chaining modes combinations */
- /*========================================================*/
- /* Check the proper chaining when the operating mode is key derivation and decryption */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
- ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)))
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
#else
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\
- ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) \
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))
-#endif
- {
- return HAL_ERROR;
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
}
- /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
+ else
{
- return HAL_ERROR;
+ /* Nothing to do */
}
+#else /* AES */
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ hcryp->CrypOutCount++;
+ temp = hcryp->Instance->DOUTR;
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+ hcryp->CrypOutCount++;
+ /*Temporary CrypOutCount Value*/
+ outcount = hcryp->CrypOutCount;
- /*================*/
- /* Initialization */
- /*================*/
- /* Initialization start */
- if(hcryp->State == HAL_CRYP_STATE_RESET)
+ if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) )
{
- /* Allocate lock resource and initialize it */
- hcryp->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_CRYP_MspInit(hcryp);
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
-
- /*=============================================================*/
- /* AES initialization common to all operating modes */
- /*=============================================================*/
- /* Set the Key size selection */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);
-
- /* Set the default CRYP phase when this parameter is not used.
- Phase is updated below in case of GCM/GMAC/CMAC(/CCM) setting. */
- hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;
-
+ /* Disable computation complete flag and errors interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /*=============================================================*/
- /* Carry on the initialization based on the AES operating mode */
- /*=============================================================*/
- /* Key derivation */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- /* Configure the Key registers */
- if (CRYP_SetKey(hcryp) != HAL_OK)
+ /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Output complete callback*/
+ hcryp->OutCpltCallback(hcryp);
+#else
+ /*Call legacy weak Output complete callback*/
+ HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+
+ else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
+ {
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
{
- return HAL_ERROR;
+ /* Call Input transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
- else
- /* Encryption / Decryption (with or without key derivation) / authentication */
+ else /* Last block of payload < 128bit*/
{
- /* Set data type, operating and chaining modes.
- In case of GCM or GMAC, data type is forced to 0b00 */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
+ /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
+ generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
+
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
{
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
+ lastwordsize = (16U-npblb)/4U;
}
else
{
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);
- }
-
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
- /* Specify the encryption/decryption phase in case of Galois counter mode (GCM),
- Galois message authentication code (GMAC), cipher message authentication code (CMAC)
- or Counter with Cipher Mode (CCM) when applicable */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter < 4U )
{
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);
- hcryp->Phase = HAL_CRYP_PHASE_START;
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
}
+ }
+#endif /* AES */
+
+}
- /* Configure the Key registers if no need to bypass this step */
- if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)
+/**
+ * @brief Sets the header phase in polling mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @param Timeout: Timeout value
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t loopcounter;
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+
+ if((hcryp->Init.HeaderSize != 0U))
+ {
+
+#if defined(CRYP)
+
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
{
- if (CRYP_SetKey(hcryp) != HAL_OK)
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
{
- return HAL_ERROR;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
}
}
-
- /* If applicable, configure the Initialization Vector */
- if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)
+ else
{
- if (CRYP_SetInitVector(hcryp) != HAL_OK)
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for CCF IFEM to be raised */
+ if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
- }
+ /* Wait until the complete message has been processed */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-#if defined(AES_CR_NPBLB)
- /* Clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
+ /* Process unlocked & return error */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
- /* Reset ErrorCode field */
- hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+#else /* AES */
- /* Reset Mode suspension request */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Return function status */
- return HAL_OK;
-}
+ }
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @brief DeInitialize the CRYP peripheral.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Check the CRYP handle allocation */
- if(hcryp == NULL)
- {
- return HAL_ERROR;
- }
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Set the default CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_READY;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Reset CrypInCount and CrypOutCount */
- hcryp->CrypInCount = 0U;
- hcryp->CrypOutCount = 0U;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /*Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
- /* Disable the CRYP Peripheral Clock */
- __HAL_CRYP_DISABLE();
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- HAL_CRYP_MspDeInit(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_RESET;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
+ }
+ else
+ {
+#if defined(AES)
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Release Lock */
- __HAL_UNLOCK(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+#endif /* AES */
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initialize the CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
+ * @brief Sets the header phase when using DMA in process
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_MspInit can be implemented in the user file
- */
-}
+ __IO uint32_t count = 0U;
+ uint32_t loopcounter;
-/**
- * @brief DeInitialize CRYP MSP.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if((hcryp->Init.HeaderSize != 0U))
+ {
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_MspDeInit can be implemented in the user file
- */
-}
+#if defined(CRYP)
-/**
- * @}
- */
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions
- * @brief Processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES algorithm in different chaining modes
- (+) Decrypt cyphertext using AES algorithm in different chaining modes
- [..] Three processing functions are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
-@endverbatim
- * @{
- */
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter < 4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
+ /* Wait for IFEM to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+ }
+ /* Wait until the complete message has been processed */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
-/**
- * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+#else /* AES */
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ if ((hcryp->Init.HeaderSize %4U )== 0U)
+ {
+ /* HeaderSize %4, no padding */
+ for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U)
+ {
+ /* Write the input block in the data input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
- return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);
-}
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ }
+ else
+ {
+ /*Write header block in the IN FIFO without last block */
+ for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U)
+ {
+ /* Write the Input block in the Data Input register */
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
-}
+ /*Wait on CCF flag*/
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if(count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Specify Timeout value
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ }
+#endif /* End AES or CRYP */
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else
{
- return HAL_ERROR;
- }
+#if defined(AES)
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);
-}
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-/**
- * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+#endif /* AES */
}
-
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
+ * @brief Sets the header phase in interrupt mode
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ uint32_t loopcounter;
+#if defined(AES)
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#endif
+ /***************************** Header phase *********************************/
+
+#if defined(CRYP)
+ if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
- return HAL_ERROR;
- }
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI );
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Disable the CRYP peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
-/**
- * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Enable Interrupts */
+ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI );
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer.
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
+ else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
-
-/**
- * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ { /* HeaderSize %4, no padding */
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else
{
- return HAL_ERROR;
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ loopcounter++;
+ }
}
+#else /* AES */
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
-
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
{
- return HAL_ERROR;
- }
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);
-}
+ /* Payload phase not supported in CCM AES2 */
+ if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ {
+ /* Select payload phase once the header phase is performed */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
+ }
+ if(hcryp->Init.Algorithm == CRYP_AES_CCM)
+ {
+ /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
+ hcryp->CrypHeaderCount++;
+ }
+ /* Write the payload Input block in the IN FIFO */
+ if(hcryp->Size == 0U)
+ {
+ /* Disable interrupts */
+ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE);
-/**
- * @brief Encrypt pPlainData in AES ECB encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Change the CRYP state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+
+ if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U))
+ {
+ /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered Input complete callback*/
+ hcryp->InCpltCallback(hcryp);
+#else
+ /*Call legacy weak Input complete callback*/
+ HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ else /* Size < 4 words : first block is the last block*/
+ {
+ /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
+ generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
+ payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size);
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) ==0U)
+ {
+ lastwordsize = (16U-npblb)/4U;
+ }
+ else
+ {
+ lastwordsize = ((16U-npblb)/4U) +1U;
+ }
-/**
- * @brief Encrypt pPlainData in AES CBC encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(loopcounter <4U )
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ }
+ else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
{
- return HAL_ERROR;
+ /* Write the input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
+ hcryp->CrypHeaderCount++;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
+ else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
{
- return HAL_ERROR;
+ /* Last block optionally pad the data with zeros*/
+ for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ while(loopcounter <4U )
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
-
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
+#endif /* End AES or CRYP */
}
+
/**
- * @brief Encrypt pPlainData in AES CTR encryption mode using DMA,
- * the cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Workaround used for GCM/CCM mode.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pCypherData Pointer to the cyphertext buffer.
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
+ * @param Timeout: specify Timeout value
+ * @retval None
*/
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ uint32_t lastwordsize;
+ uint32_t npblb;
+#if defined(CRYP)
+ uint32_t iv1temp;
+ uint32_t temp[4] = {0};
+ uint32_t temp2[4]= {0};
+#endif /* CRYP */
+ uint32_t intermediate_data[4]={0};
+ uint32_t index;
- return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);
-}
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size);
-/**
- * @brief Decrypt pCypherData in AES ECB decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb%4U) ==0U)
+ { lastwordsize = (16U-npblb)/4U;
}
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
+ else
+ {lastwordsize = ((16U-npblb)/4U) +1U;
}
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+#if defined(CRYP)
-/**
- * @brief Decrypt pCypherData in AES CBC decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
+ /* Workaround 2, case GCM encryption */
+ if (hcryp->Init.Algorithm == CRYP_AES_GCM)
{
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {/*Workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+ /*Load CRYP_IV1R register content in a temporary variable. Decrement the value
+ by 1 and reinsert the result in CRYP_IV1R register*/
+ hcryp->Instance->IV1RR = 0x5U;
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-/**
- * @brief Decrypt pCypherData in AES CTR decryption mode using DMA,
- * the decyphered data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16.
- * @param pPlainData Pointer to the plaintext buffer
- * @note This API is provided only to maintain compatibility with legacy software. Users should directly
- * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).
- * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- /* Re-initialize AES IP with proper parameters */
- if (HAL_CRYP_DeInit(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
- hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;
- hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;
- hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
- if (HAL_CRYP_Init(hcryp) != HAL_OK)
- {
- return HAL_ERROR;
- }
+ /* Enable CRYP to start the final phase */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(index=0; index < lastwordsize; index ++)
+ {
+ /* Write the last input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(index < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0U;
+ index++;
+ }
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for(index=0U; index< 4U;index++)
+ {
+ /* Read the output block from the output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUT;
-/**
- * @}
- */
+ /* Intermediate data buffer to be used in for the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
+ }
-/** @defgroup CRYP_Exported_Functions_Group3 Callback functions
- * @brief Callback functions.
- *
-@verbatim
- ==============================================================================
- ##### Callback functions #####
- ==============================================================================
- [..] This section provides Interruption and DMA callback functions:
- (+) DMA Input data transfer complete
- (+) DMA Output data transfer complete
- (+) DMA or Interrupt error
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /*workaround in order to properly compute authentication tags while doing
+ a GCM encryption with the last block of payload size inferior to 128 bits*/
+ /* Change the AES mode to GCM mode and Select Final phase */
+ /* configured CHMOD GCM */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
-@endverbatim
- * @{
- */
+ /* configured final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-/**
- * @brief CRYP error callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ for (index=0U; index < lastwordsize; index ++)
+ {
+ /*Write the intermediate_data in the IN FIFO */
+ hcryp->Instance->DIN=intermediate_data[index];
+ }
+ while(index < 4U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0x0U;
+ index++;
+ }
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_ErrorCallback can be implemented in the user file
- */
-}
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Input DMA transfer complete callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_InCpltCallback can be implemented in the user file
- */
-}
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
+ {
+ for( index=0U; index< 4U;index++)
+ {
+ intermediate_data[index]=hcryp->Instance->DOUT;
+ }
+ }
+ }
+ } /* End of GCM encryption */
+ else{ /* Workaround 2, case CCM decryption, in order to properly compute
+ authentication tags while doing a CCM decryption with the last block
+ of payload size inferior to 128 bits*/
-/**
- * @brief Output DMA transfer complete callback.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ iv1temp = hcryp->Instance->CSGCMCCM7R;
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYP_OutCpltCallback can be implemented in the user file
- */
-}
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @}
- */
+ temp[0]= hcryp->Instance->CSGCMCCM0R;
+ temp[1]= hcryp->Instance->CSGCMCCM1R;
+ temp[2]= hcryp->Instance->CSGCMCCM2R;
+ temp[3]= hcryp->Instance->CSGCMCCM3R;
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler
- * @brief AES IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### AES IRQ handler management #####
- ==============================================================================
-[..] This section provides AES IRQ handler function.
+ hcryp->Instance->IV1RR= iv1temp;
-@endverbatim
- * @{
- */
+ /* Configured CHMOD CTR */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
-/**
- * @brief Handle AES interrupt request.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- /* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)
- {
- /* If Write Error occurred */
- if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)
+ /* Enable CRYP to start the final phase */
+ __HAL_CRYP_ENABLE(hcryp);
+ }
+ /* Last block optionally pad the data with zeros*/
+ for(index=0; index < lastwordsize; index ++)
{
- hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
}
- /* If Read Error occurred */
- if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)
+ while(index < 4U)
{
- hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
+ /* Pad the data with zeros to have a complete block */
+ hcryp->Instance->DIN = 0U;
+ index++;
}
-
- /* If an error has been reported */
- if (hcryp->State == HAL_CRYP_STATE_ERROR)
+ /* Wait for OFNE flag to be raised */
+ if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
{
- /* Disable Error and Computation Complete Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Clear all Interrupt flags */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
-
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
-
- return;
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
- }
- /* Check if computation complete interrupt is enabled
- and if the computation complete flag is raised */
- if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))
- {
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))
-#endif
- {
- /* To ensure proper suspension requests management, CCF flag
- is reset in CRYP_AES_Auth_IT() according to the current
- phase under handling */
- CRYP_AES_Auth_IT(hcryp);
- }
- else
+ if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U)
{
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- CRYP_AES_IT(hcryp);
+ for(index=0U; index< 4U;index++)
+ {
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUT;
+
+ /*intermediate data buffer to be used in for the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index];
+ hcryp->CrypOutCount++;
+ }
}
- }
-}
-/**
- * @}
- */
+ if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
+ {
+ temp2[0]= hcryp->Instance->CSGCMCCM0R;
+ temp2[1]= hcryp->Instance->CSGCMCCM1R;
+ temp2[2]= hcryp->Instance->CSGCMCCM2R;
+ temp2[3]= hcryp->Instance->CSGCMCCM3R;
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ /* configured CHMOD CCM */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
-@endverbatim
- * @{
- */
+ /* configured Header phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
-/**
- * @brief Return the CRYP handle state.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL state
- */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
- /* Return CRYP handle state */
- return hcryp->State;
-}
+ /*set to zero the bits corresponding to the padded bits*/
+ for(index = lastwordsize; index<4U; index ++)
+ {
+ intermediate_data[index] =0U;
+ }
+ if ((npblb %4U)==1U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+ }
+ if ((npblb %4U)==2U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+ }
+ if ((npblb %4U)==3U)
+ {
+ intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+ }
+ for(index=0U; index < 4U ; index ++)
+ {
+ intermediate_data[index] ^= temp[index];
+ intermediate_data[index] ^= temp2[index];
+ }
+ for(index = 0U; index < 4U; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DIN = intermediate_data[index] ;
+ }
-/**
- * @brief Return the CRYP peripheral error.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @note The returned error is a bit-map combination of possible errors
- * @retval Error bit-map
- */
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
-{
- return hcryp->ErrorCode;
-}
+ /* Wait for BUSY flag to be raised */
+ if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
-/**
- * @}
- */
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @}
- */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ } /* End of CCM WKA*/
-/** @addtogroup CRYP_Private_Functions
- * @{
- */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#else /* AES */
-/**
- * @brief Write the Key in KeyRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t keyaddr = 0x0U;
+ /*Workaround 2: case GCM encryption, during payload phase and before inserting
+ the last block of paylaod, which size is inferior to 128 bits */
- if ((uint32_t)(hcryp->Init.pKey == NULL))
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
- return HAL_ERROR;
+ /* configured CHMOD CTR */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
+ }
+ /* last block optionally pad the data with zeros*/
+ for(index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+ hcryp->CrypInCount++;
+ }
+ while(index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ hcryp->State = HAL_CRYP_STATE_READY;
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- keyaddr = (uint32_t)(hcryp->Init.pKey);
-
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ for(index = 0U; index< 4U;index++)
{
- hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
+ /* Read the Output block from the Output FIFO */
+ intermediate_data[index] = hcryp->Instance->DOUTR;
+
+ /*intermediate data buffer to be used in the workaround*/
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index];
+ hcryp->CrypOutCount++;
}
- hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
+ if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
+ {
+ /* configured CHMOD GCM */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
- return HAL_OK;
-}
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+ /*Write the intermediate_data in the IN FIFO */
+ for(index = 0U; index < lastwordsize; index ++)
+ {
+ hcryp->Instance->DINR = intermediate_data[index];
+ }
+ while(index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ for( index = 0U; index< 4U;index++)
+ {
+ intermediate_data[index]=hcryp->Instance->DOUTR;
+ }
+ }/*End of Workaround 2*/
+#endif /* End AES or CRYP */
+}
+#endif /* AES or GCM CCM defined*/
+#if defined (CRYP)
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)
/**
- * @brief Write the InitVector/InitCounter in IVRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
+ * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t ivaddr = 0x0U;
+ uint32_t tickstart;
-#if !defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- hcryp->Instance->IVR3 = 0U;
- hcryp->Instance->IVR2 = 0U;
- hcryp->Instance->IVR1 = 0U;
- hcryp->Instance->IVR0 = 0U;
- }
- else
-#endif
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
{
- if (hcryp->Init.pInitVect == NULL)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- return HAL_ERROR;
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ return HAL_ERROR;
+ }
}
+ }
+ return HAL_OK;
+}
+#endif /* GCM CCM defined*/
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
- ivaddr = (uint32_t)(hcryp->Init.pInitVect);
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
+ while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+ {
+ return HAL_ERROR;
+ }
+ }
}
return HAL_OK;
}
-
/**
- * @brief Handle CRYP block input/output data handling under interruption.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by HAL_CRYPEx_AES_IT().
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t inputaddr = 0U;
- uint32_t outputaddr = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* Get the output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ uint32_t tickstart;
- /* Read the last available output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- }
- else
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Read the derived key from the Key registers */
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
- outputaddr+=4U;
+ return HAL_ERROR;
}
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
}
+ }
+ return HAL_OK;
+}
- /* In case of ciphering or deciphering, check if all output text has been retrieved;
- In case of key derivation, stop right there */
- if ((hcryp->CrypOutCount == 0U) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))
- {
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
+#else /* AES */
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+/**
+ * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* reset ModeSuspend */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
-
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) )
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ return HAL_OK;
+}
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+#endif /* End AES or CRYP */
- return HAL_OK;
- }
- else /* Process the rest of input data */
- {
- /* Get the Intput data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
+/**
+ * @}
+ */
- /* Write the next input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
/**
* @}
*/
-#endif /* AES */
+/**
+ * @}
+ */
#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* TinyAES or CRYP*/
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp_ex.c
index 01497e311ce8a158d619d79397413278a8e035bd..6a9f243c632c3709d032aec2ecf938f69e4147ea 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_cryp_ex.c
@@ -12,84 +12,23 @@
##### How to use this driver #####
==============================================================================
[..]
- The CRYP Extension HAL driver can be used as follows:
- (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
- (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())
- (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable two DMA streams one for managing data transfer from
- memory to peripheral (input stream) and another stream for managing data
- transfer from peripheral to memory (output stream)
- (+++) Associate the initialized DMA handle to the CRYP DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
- (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
- (##) The encryption/decryption key. Its size depends on the algorithm
- used for encryption/decryption
- (##) The initialization vector (counter). It is not used ECB mode.
- (#)Three processing (encryption/decryption) functions are available:
- (##) Polling mode: encryption and decryption APIs are blocking functions
- i.e. they process the data and wait till the processing is finished
- e.g. HAL_CRYPEx_AESGCM_Encrypt()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()
- (##) DMA mode: encryption and decryption APIs are not blocking functions
- i.e. the data transfer is ensured by DMA
- e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()
- (#)When the processing function is called at first time after HAL_CRYP_Init()
- the CRYP peripheral is initialized and processes the buffer in input.
- At second call, the processing function performs an append of the already
- processed buffer.
- When a new data block is to be processed, call HAL_CRYP_Init() then the
- processing function.
- (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms
- which provide authentication messages.
- HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those
- authentication messages.
- Call those functions after the processing ones (polling, interrupt or DMA).
- e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data
- then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message
- -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.
- -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length
- (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).
- (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
+ The CRYP extension HAL driver can be used as follows:
+ (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API
+ to get the authentication messages :
+ (##) HAL_CRYPEx_AESGCM_GenerateAuthTAG
+ (##) HAL_CRYPEx_AESCCM_GenerateAuthTAG
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -100,22 +39,51 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-
+#if defined (AES) || defined (CRYP)
+#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
*/
-#ifdef HAL_CRYP_MODULE_ENABLED
-#if defined(CRYP)
+#ifdef HAL_CRYP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_define
+/** @addtogroup CRYPEx_Private_Defines
* @{
*/
-#define CRYPEx_TIMEOUT_VALUE 1U
+#if defined(AES)
+#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
+#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
+#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
+#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */
+
+#else /* CRYP */
+
+#define CRYP_PHASE_INIT 0x00000000U
+#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
+#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
+#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
+
+#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
+#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
+#endif /* End AES or CRYP */
+
+#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
+#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+
+ /* CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0 0x07FFFFFFU
+#define CRYP_CCM_CTR0_3 0xFFFFFF00U
+
+
/**
* @}
*/
@@ -123,905 +91,375 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions_prototypes CRYP Private Functions Prototypes
- * @{
- */
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
-static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);
-static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup CRYPEx_Private_Functions
+
+
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ * @brief Extended processing functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended AES processing functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to generate the authentication
+ TAG in Polling mode
+ (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
+ (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
+ they should be used after Encrypt/Decrypt operation.
- /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
+@endverbatim
+ * @{
+ */
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief generate the GCM authentication TAG.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param AuthTag: Pointer to the authentication buffer
+ * @param Timeout: Timeout duration
+ * @retval HAL status
*/
-static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart;
+ uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
+ uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
+ uint32_t tagaddr = (uint32_t)AuthTag;
- /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit
- in the DMACR register */
- hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
+ {
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
+ }
+ else /* Initialization phase has not been performed*/
+ {
+ /* Disable the Peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hcryp->State= HAL_CRYP_STATE_READY;
- HAL_CRYP_ErrorCallback(hcryp);
-}
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
-/**
- * @brief Writes the Key in Key registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Key Pointer to Key buffer
- * @param KeySize Size of Key
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Key;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
- switch(KeySize)
- {
- case CRYP_KEYSIZE_256B:
- /* Key Initialisation */
- hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_192B:
- hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- case CRYP_KEYSIZE_128B:
- hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
- break;
- default:
- break;
- }
-}
+#if defined(CRYP)
-/**
- * @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param InitVector Pointer to InitVector/InitCounter buffer
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
-{
- uint32_t ivaddr = (uint32_t)InitVector;
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
-}
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
-/**
- * @brief Process Data: Writes Input data in polling mode and read the Output data.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer, must be a multiple of 16
- * @param Output Pointer to the returned buffer
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t i = 0U;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
+ /*ALGODIR bit must be set to ‘0’.*/
+ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
- for(i=0U; (i < Ilength); i+=16U)
- {
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Write the number of bits in header (64 bits) followed by the number of bits
+ in the payload */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = (uint32_t)(headerlength);
+ hcryp->Instance->DIN = 0U;
+ hcryp->Instance->DIN = (uint32_t)(inputlength);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ /* Wait for OFNE flag to be raised */
+ tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP Peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- /* Read the Output block from the OUT FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- }
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Sets the header phase
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer, must be a multiple of 16
- * @param Timeout Timeout value
- * @retval None
- */
-static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t loopcounter = 0U;
- uint32_t headeraddr = (uint32_t)Input;
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- /* Prevent unused argument(s) compilation warning */
- UNUSED(Ilength);
+#else /* AES*/
- /***************************** Header phase *********************************/
- if(hcryp->Init.HeaderSize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16U)
+ /* Write the number of bits in header (64 bits) followed by the number of bits
+ in the payload */
+ if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength));
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength));
}
-
- /* Wait until the complete message has been processed */
-
- /* Get tick */
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __REV((uint32_t)(headerlength));
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __REV((uint32_t)(inputlength));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U);
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
+ {
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(headerlength);
+ hcryp->Instance->DINR = 0U;
+ hcryp->Instance->DINR = (uint32_t)(inputlength);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ /* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- }
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Sets the DMA configuration and start the DMA transfer.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param inputaddr Address of the Input buffer
- * @param Size Size of the Input buffer, must be a multiple of 16
- * @param outputaddr Address of the Output buffer
- * @retval None
- */
-static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4U);
+#endif /* End AES or CRYP */
- /* Enable In DMA request */
- hcryp->Instance->DMACR = CRYP_DMACR_DIEN;
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Enable the DMA Out DMA Stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4U);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Enable Out DMA request */
- hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+ else
+ {
+ /* Busy error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ /* Return function status */
+ return HAL_OK;
}
/**
- * @}
- */
-
-/* Exported functions---------------------------------------------------------*/
-/** @addtogroup CRYPEx_Exported_Functions
- * @{
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### Extended AES processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes
- (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes
- (+) Finish the processing. This function is available only for GCM and CCM
- [..] Three processing methods are available:
- (+) Polling mode
- (+) Interrupt mode
- (+) DMA mode
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode then
- * encrypt pPlainData. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * @brief AES CCM Authentication TAG generation.
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
+ * @param AuthTag: Pointer to the authentication buffer
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
+ uint32_t tagaddr = (uint32_t)AuthTag;
+ uint32_t ctr0 [4]={0};
+ uint32_t ctr0addr = (uint32_t)ctr0;
+ uint32_t tickstart;
- /* Process Locked */
- __HAL_LOCK(hcryp);
+ if(hcryp->State == HAL_CRYP_STATE_READY)
+ {
+ /* Process locked */
+ __HAL_LOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *********************/
- if(headersize != 0U)
+ /* Check if initialization phase has already been performed */
+ if(hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
+ /* Change the CRYP phase */
+ hcryp->Phase = CRYPEx_PHASE_FINAL;
}
- /*********************** Formatting the block B0 **************************/
- if(headersize != 0U)
+ else /* Initialization phase has not been performed*/
{
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
+ /* Disable the peripheral */
+ __HAL_CRYP_DISABLE(hcryp);
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
+ /* Sequence error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /************************* Formatting the initial counter *****************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks
- are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
+#if defined(CRYP)
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+ /* Disable CRYP to start the final phase */
+ __HAL_CRYP_DISABLE(hcryp);
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
+ /* Select final phase & ALGODIR bit must be set to ‘0’. */
+ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Write the counter block in the IN FIFO, CTR0 information from B0
+ data has to be swapped according to the DATATYPE*/
+ ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1]=hcryp->Init.B0[1];
+ ctr0[2]=hcryp->Init.B0[2];
+ ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr));
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
+ {
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr));
+ }
+ else
+ {
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DIN = *(uint32_t*)(ctr0addr);
+ }
+ /* Wait for OFNE flag to be raised */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
+ /* Disable the CRYP peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
/* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /***************************** Header phase *******************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode then
- * encrypt pPlainData. The cypher data are available in pCypherData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode then
- * decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Computes the authentication TAG.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Size Total length of the plain/cyphertext buffer
- * @param AuthTag Pointer to the authentication buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint64_t headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
- uint64_t inputlength = Size * 8U; /* input length in bits */
- uint32_t tagaddr = (uint32_t)AuthTag;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL;
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the number of bits in header (64 bits) followed by the number of bits
- in the payload */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DR = __RBIT(headerlength >> 32U);
- hcryp->Instance->DR = __RBIT(headerlength);
- hcryp->Instance->DR = __RBIT(inputlength >> 32U);
- hcryp->Instance->DR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DR = __REV(headerlength >> 32U);
- hcryp->Instance->DR = __REV(headerlength);
- hcryp->Instance->DR = __REV(inputlength >> 32U);
- hcryp->Instance->DR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32U), 16U);
- hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16U);
- hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32U), 16U);
- hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DR = (uint32_t)(headerlength >> 32U);
- hcryp->Instance->DR = (uint32_t)(headerlength);
- hcryp->Instance->DR = (uint32_t)(inputlength >> 32U);
- hcryp->Instance->DR = (uint32_t)(inputlength);
- }
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -1032,4951 +470,199 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
tagaddr+=4U;
*(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Computes the authentication TAG for AES CCM mode.
- * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param AuthTag Pointer to the authentication buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t tagaddr = (uint32_t)AuthTag;
- uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;
- uint32_t temptag[4U] = {0U}; /* Temporary TAG (MAC) */
- uint32_t loopcounter;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)
- {
- /* Change the CRYP phase */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL;
-
- /* Disable CRYP to start the final phase */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select final phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Write the counter block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
- ctraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)ctraddr;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the Auth TAG in the IN FIFO */
- temptag[0U] = hcryp->Instance->DOUT;
- temptag[1U] = hcryp->Instance->DOUT;
- temptag[2U] = hcryp->Instance->DOUT;
- temptag[3U] = hcryp->Instance->DOUT;
- }
-
- /* Copy temporary authentication TAG in user TAG buffer */
- for(loopcounter = 0U; loopcounter < hcryp->Init.TagSize ; loopcounter++)
- {
- /* Set the authentication TAG buffer */
- *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode then
- * decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *********************/
- if(headersize != 0U)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 **************************/
- if(headersize != 0U)
- {
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2U))) >> 1U) & (uint8_t)0x07U) << 3U);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15U) - hcryp->Init.IVSize) - (uint8_t)1U) & (uint8_t)0x07U);
-
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
-
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
-
- /************************* Formatting the initial counter *****************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /***************************** Header phase *******************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Write Plain Data and Get Cypher Data */
- if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
-
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
-
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0U)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0U)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0U)
- {
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
-
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0U)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call Input transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- if(Size != 0U)
- {
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
- else
- {
- /* Process Locked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt
- * then decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t tickstart = 0U;
- uint32_t headersize = hcryp->Init.HeaderSize;
- uint32_t headeraddr = (uint32_t)hcryp->Init.Header;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0U)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0U)
- {
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1U) & (uint8_t)0x07) << 3U);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
-
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Enable Interrupts */
- __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
- {
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Write the Input block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(inputaddr);
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- if(hcryp->CrypInCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
- /* Call the Input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
- }
- }
- else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
- {
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- if(hcryp->CrypOutCount == 0U)
- {
- __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Call Input transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pPlainData Pointer to the plaintext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pCypherData Pointer to the cyphertext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t headersize;
- uint32_t headeraddr;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pPlainData;
- outputaddr = (uint32_t)pCypherData;
-
- headersize = hcryp->Init.HeaderSize;
- headeraddr = (uint32_t)hcryp->Init.Header;
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pPlainData;
- hcryp->pCrypOutBuffPtr = pCypherData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0U)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0U)
- {
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07) << 3);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
-
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer.
- * @param Size Length of the cyphertext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES GCM decryption mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);
-
- /* Enable CRYP to start the init phase */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the header phase */
- if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1U) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Disable the CRYP peripheral */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
-
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA
- * then decrypted pCypherData. The cypher data are available in pPlainData.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pCypherData Pointer to the cyphertext buffer
- * @param Size Length of the plaintext buffer, must be a multiple of 16
- * @param pPlainData Pointer to the plaintext buffer
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
- uint32_t tickstart = 0U;
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t headersize;
- uint32_t headeraddr;
- uint32_t loopcounter = 0U;
- uint32_t bufferidx = 0U;
- uint8_t blockb0[16U] = {0};/* Block B0 */
- uint8_t ctr[16U] = {0}; /* Counter */
- uint32_t b0addr = (uint32_t)blockb0;
-
- if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
- {
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pCypherData;
- outputaddr = (uint32_t)pPlainData;
-
- headersize = hcryp->Init.HeaderSize;
- headeraddr = (uint32_t)hcryp->Init.Header;
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pCypherData;
- hcryp->pCrypOutBuffPtr = pPlainData;
- hcryp->CrypOutCount = Size;
-
- /* Change the CRYP peripheral state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hcryp->Phase == HAL_CRYP_PHASE_READY)
- {
- /************************ Formatting the header block *******************/
- if(headersize != 0U)
- {
- /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
- if(headersize < 65280U)
- {
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
- hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
- headersize += 2U;
- }
- else
- {
- /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
- hcryp->Init.pScratch[bufferidx++] = 0xFFU;
- hcryp->Init.pScratch[bufferidx++] = 0xFEU;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
- hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
- headersize += 6U;
- }
- /* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
- for(loopcounter = 0U; loopcounter < headersize; loopcounter++)
- {
- hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];
- }
- /* Check if the header size is modulo 16 */
- if ((headersize % 16U) != 0U)
- {
- /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */
- for(loopcounter = headersize; loopcounter <= ((headersize/16U) + 1U) * 16U; loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = 0U;
- }
- /* Set the header size to modulo 16 */
- headersize = ((headersize/16U) + 1U) * 16U;
- }
- /* Set the pointer headeraddr to hcryp->Init.pScratch */
- headeraddr = (uint32_t)hcryp->Init.pScratch;
- }
- /*********************** Formatting the block B0 ************************/
- if(headersize != 0U)
- {
- blockb0[0U] = 0x40U;
- }
- /* Flags byte */
- /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07U) */
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07) << 3);
- blockb0[0U] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);
-
- for (loopcounter = 0U; loopcounter < hcryp->Init.IVSize; loopcounter++)
- {
- blockb0[loopcounter+1U] = hcryp->Init.pInitVect[loopcounter];
- }
- for ( ; loopcounter < 13U; loopcounter++)
- {
- blockb0[loopcounter+1U] = 0U;
- }
-
- blockb0[14U] = (Size >> 8U);
- blockb0[15U] = (Size & 0xFFU);
-
- /************************* Formatting the initial counter ***************/
- /* Byte 0:
- Bits 7 and 6 are reserved and shall be set to 0
- Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter
- blocks are distinct from B0
- Bits 0, 1, and 2 contain the same encoding of q as in B0
- */
- ctr[0U] = blockb0[0U] & 0x07U;
- /* byte 1 to NonceSize is the IV (Nonce) */
- for(loopcounter = 1U; loopcounter < hcryp->Init.IVSize + 1U; loopcounter++)
- {
- ctr[loopcounter] = blockb0[loopcounter];
- }
- /* Set the LSB to 1 */
- ctr[15U] |= 0x01U;
-
- /* Set the key */
- CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-
- /* Set the CRYP peripheral in AES CCM mode */
- __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);
-
- /* Set the Initialization Vector */
- CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);
-
- /* Select init phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- b0addr = (uint32_t)blockb0;
- /* Write the blockb0 block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
- b0addr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(b0addr);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
- {
- /* Check for the Timeout */
-
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
-
- }
- }
- /***************************** Header phase *****************************/
- if(headersize != 0U)
- {
- /* Select header phase */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable Crypto processor */
- __HAL_CRYP_ENABLE(hcryp);
-
- for(loopcounter = 0U; (loopcounter < headersize); loopcounter+=16U)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- /* Write the header block in the IN FIFO */
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- hcryp->Instance->DR = *(uint32_t*)(headeraddr);
- headeraddr+=4U;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)
- {
- /* Change state */
- hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Save formatted counter into the scratch buffer pScratch */
- for(loopcounter = 0U; (loopcounter < 16U); loopcounter++)
- {
- hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];
- }
- /* Reset bit 0 */
- hcryp->Init.pScratch[15U] &= 0xFEU;
- /* Select payload phase once the header phase is performed */
- __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Flush FIFO */
- __HAL_CRYP_FIFO_FLUSH(hcryp);
-
- /* Set the phase */
- hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
- }
- /* Set the input and output addresses and start DMA transfer */
- CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Unlock process */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management
- * @brief CRYPEx IRQ handler.
- *
-@verbatim
- ==============================================================================
- ##### CRYPEx IRQ handler management #####
- ==============================================================================
-[..] This section provides CRYPEx IRQ handler function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief This function handles CRYPEx interrupt request.
- * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-
-void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
- switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
- {
- case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:
- HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:
- HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:
- HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0U, NULL);
- break;
-
- case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:
- HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0U, NULL);
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* CRYP */
-
-#if defined (AES)
-
-/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
- * @{
- */
-#define CRYP_CCF_TIMEOUTVALUE 22000U /*!< CCF flag raising time-out value */
-#define CRYP_BUSY_TIMEOUTVALUE 22000U /*!< BUSY flag reset time-out value */
-
-#define CRYP_POLLING_OFF 0x0U /*!< No polling when padding */
-#define CRYP_POLLING_ON 0x1U /*!< Polling when padding */
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
- * @{
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
- * @{
- */
-
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function
- * @brief Extended callback functions.
- *
-@verbatim
- ===============================================================================
- ##### Extended callback functions #####
- ===============================================================================
- [..] This section provides callback function:
- (+) Computation completed.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Computation completed callbacks.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval None
- */
-__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcryp);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES extended processing functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.
- Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated
- based on the processing type. Three processing types are available:
- (++) Polling mode
- (++) Interrupt mode
- (++) DMA mode
- (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES
- algorithm in different chaining modes.
- Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase
- so that steps can be skipped if so required. Functions are only differentiated based on the processing type.
- Three processing types are available:
- (++) Polling mode
- (++) Interrupt mode
- (++) DMA mode
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Carry out in polling mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
- * chaining modes ECB, CBC and CTR are managed by this function in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * Parameter is meaningless in case of key derivation.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * Parameter is meaningless in case of key derivation.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption, or pointer to the derivative keys in
- * case of key derivation only.
- * @param Timeout Specify Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)
-{
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Call CRYP_ReadKey() API if the operating mode is set to
- key derivation, CRYP_ProcessData() otherwise */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- else
- {
- if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* If the state has not been set to SUSPENDED, set it to
- READY, otherwise keep it as it is */
- if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Carry out in interrupt mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and
- * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * Parameter is meaningless in case of key derivation.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * Parameter is meaningless in case of key derivation.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption, or pointer to the derivative keys in
- * case of key derivation only.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0U;
-
- if(hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* If operating mode is not limited to key derivation only,
- get the buffers addresses and sizes */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
-
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pInputData;
- hcryp->pCrypOutBuffPtr = pOutputData;
- hcryp->CrypOutCount = Size;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Enable Computation Complete Flag and Error Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
- /* If operating mode is key derivation only, the input data have
- already been entered during the initialization process. For
- the other operating modes, they are fed to the CRYP hardware
- block at this point. */
- if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* Initiate the processing under interrupt in entering
- the first input data */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- /* Write the first input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Carry out in DMA mode the ciphering or deciphering operation according to
- * hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption
- * or key derivation+decryption.
- * @param Size Length of the input data buffer in bytes, must be a multiple of 16.
- * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of
- * decryption/key derivation+decryption.
- * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.
- * @note Supported operating modes are encryption, decryption and key derivation with decryption.
- * @note No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx
- * registers must be done by software.
- * @note This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx
- * registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.
- * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0U;
- uint32_t outputaddr = 0U;
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* Check parameters setting */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
- {
- /* no DMA channel is provided for key derivation operating mode,
- access to AES_KEYRx registers must be done by software */
- return HAL_ERROR;
- }
- else
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Set the input and output addresses and start DMA transfer */
- CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Return function status */
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B0 block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @param Timeout Specify Timeout value
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)
-{
- uint32_t index = 0U;
- uint32_t inputaddr = 0U;
- uint32_t outputaddr = 0U;
- uint32_t tagaddr = 0U;
- uint64_t headerlength = 0U;
- uint64_t inputlength = 0U;
- uint64_t payloadlength = 0U;
- uint32_t difflength = 0U;
- uint32_t addhoc_process = 0U;
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC (or CCM) header phase resumption, we can have pInputData = NULL and Size = 0 */
- if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U)))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. Therefore, the
- API just waits for the CCF flag to be set. */
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
- }
-
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
-
-#if !defined(AES_CR_NPBLB)
- /* in case of CMAC, enter B0 block in header phase, before the header itself. */
- /* If Size = 0 (possible case of resumption after CMAC header phase suspension),
- skip these steps and go directly to header buffer feeding to the HW */
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0U))
- {
- inputaddr = (uint32_t)pInputData;
-
- for(index=0U; (index < Size); index += 16U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Size))
- {
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the total number of bytes (B blocks + header) that remain to be
- processed at this point */
- hcryp->CrypInCount = hcryp->Init.HeaderSize + Size - (index+16U);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- } /* for(index=0; (index < Size); index += 16) */
- }
-#endif /* !defined(AES_CR_NPBLB) */
-
- /* Enter header */
- inputaddr = (uint32_t)hcryp->Init.Header;
- /* Local variable headerlength is a number of bytes multiple of 128 bits,
- remaining header data (if any) are handled after this loop */
- headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ;
- if ((hcryp->Init.HeaderSize % 16U) != 0U)
- {
- difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);
- }
- for(index=0U; index < headerlength; index += 16U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < headerlength))
- {
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the total number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = hcryp->Init.HeaderSize - (index+16U);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- }
-
- /* Case header length is not a multiple of 16 bytes */
- if (difflength != 0U)
- {
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
- }
-
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
-
- /* if the header phase has been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Enter payload */
- /* Specific handling to manage payload last block size less than 128 bits */
- if ((Size % 16U) != 0U)
- {
- payloadlength = (Size/16U) * 16U;
- difflength = (uint32_t) (Size - payloadlength);
- addhoc_process = 1U;
- }
- else
- {
- payloadlength = Size;
- addhoc_process = 0U;
- }
-
- /* Feed payload */
- for(index=0U; index < payloadlength; index += 16U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Retrieve output data: read the output block
- from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < payloadlength))
- {
- /* no flag waiting under IRQ handling */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Ensure that Busy flag is reset */
- if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- }
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = Size - (index+16U);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
-
- }
-
- /* Additional processing to manage GCM(/CCM) encryption and decryption cases when
- payload last block size less than 128 bits */
- if (addhoc_process == 1U)
- {
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
- } /* (addhoc_process == 1) */
-
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- tagaddr = (uint32_t)pOutputData;
-
-#if defined(AES_CR_NPBLB)
- /* By default, clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
- inputlength = Size * 8U; /* input length in bits */
-
-
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32U);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32U);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(headerlength, 16U);
- hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(inputlength, 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
-#endif
-
-
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Read the Auth TAG in the Data Out register */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the final phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-/**
- * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B0 block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
-{
-
- uint32_t inputaddr = 0U;
- uint64_t headerlength = 0U;
- uint64_t inputlength = 0U;
- uint32_t index = 0U;
- uint32_t addhoc_process = 0U;
- uint32_t difflength = 0U;
- uint32_t difflengthmod4 = 0U;
- uint32_t mask[3U] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
-
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC header phase resumption, we can have pInputData = NULL and Size = 0 */
- if (((pInputData != NULL) && (Size == 0U)) || ((pInputData == NULL) && (Size != 0U)))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Enable Computation Complete Flag and Error Interrupts */
- __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. Therefore, the
- software just waits for the CCF interrupt to be raised and which will
- be handled by CRYP_AES_Auth_IT() API. */
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
-
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- /* In case of CMAC, B blocks are first entered, before the header.
- Therefore, B blocks and the header are entered back-to-back
- as if it was only one single block.
- However, in case of resumption after suspension, if all the
- B blocks have been entered (in that case, Size = 0), only the
- remainder of the non-processed header bytes are entered. */
- if (Size != 0U)
- {
- hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = pInputData;
- }
- else
- {
- hcryp->CrypInCount = hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
- else
- {
- /* Get the header addresses and sizes */
- hcryp->CrypInCount = hcryp->Init.HeaderSize;
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
-
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);
- }
-
- /* Enable the Peripheral */
- __HAL_CRYP_ENABLE();
-
- /* Increment/decrement instance pointer/counter */
- if (hcryp->CrypInCount == 0U)
- {
- /* Case of no header */
- hcryp->State = HAL_CRYP_STATE_READY;
- return HAL_OK;
- }
- else if (hcryp->CrypInCount < 16U)
- {
- hcryp->CrypInCount = 0U;
- addhoc_process = 1U;
- difflength = (uint32_t) (hcryp->Init.HeaderSize);
- difflengthmod4 = difflength%4U;
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- }
-
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
- {
- /* All B blocks will have been entered after the next
- four DINR writing, so point at header buffer for
- the next iteration */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
-
- /* Enter header first block to initiate the process
- in the Data Input register */
- if (addhoc_process == 0U)
- {
- /* Header has size equal or larger than 128 bits */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- else
- {
- /* Header has size less than 128 bits */
- /* Enter complete words when possible */
- for(index=0U; index < (difflength/4U); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0U)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- hcryp->Instance->DINR = 0U;
- }
-
- }
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- /* Get the buffer addresses and sizes */
- hcryp->CrypInCount = Size;
- hcryp->pCrypInBuffPtr = pInputData;
- hcryp->pCrypOutBuffPtr = pOutputData;
- hcryp->CrypOutCount = Size;
-
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);
-
- /* if the header phase has been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- /* Specific handling to manage payload size less than 128 bits */
- if (Size < 16U)
- {
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
- {
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
- }
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
- /* Set hcryp->CrypInCount to 0 (no more data to enter) */
- hcryp->CrypInCount = 0U;
-
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes,
- to have a complete block of 128 bits */
- difflength = (uint32_t) (Size);
- difflengthmod4 = difflength%4U;
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
- to have a complete block of 128 bits */
- for(index=0U; index < (difflength/4U); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
- /* If required, manage input data size not multiple of 32 bits */
- if (difflengthmod4 != 0U)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
- }
- /* Wrap-up in padding with zero-words if applicable */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- hcryp->Instance->DINR = 0U;
- }
- }
- else
- {
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
-
- /* Enter payload first block to initiate the process
- in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- hcryp->pCrypOutBuffPtr = pOutputData;
-
-#if defined(AES_CR_NPBLB)
- /* By default, clear NPBLB field */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);
-#endif
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
- inputlength = Size * 8U; /* Input length in bits */
- /* Write the number of bits in the header on 64 bits followed by the number
- of bits in the payload on 64 bits as well */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32U);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32U);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(headerlength, 16U);
- hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(inputlength, 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
-#endif
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- return HAL_ERROR;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
-
-/**
- * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering
- * operation according to hcryp->Init structure fields.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param pInputData
- * - pointer to payload data in GCM payload phase,
- * - pointer to B0 block in CMAC header phase,
- * - pointer to C block in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init, header and final phases.
- * @param Size
- * - length of the input payload data buffer in bytes,
- * - length of B block (in bytes) in CMAC header phase,
- * - length of C block (in bytes) in CMAC final phase.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases.
- * @param pOutputData
- * - pointer to plain or cipher text in GCM payload phase,
- * - pointer to authentication tag in GCM/GMAC and CMAC final phases.
- * - Parameter is meaningless in case of GCM/GMAC init and header phases
- * and in case of CMAC header phase.
- * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.
- * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes
- * can be skipped by the user if so required.
- * @note pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)
-{
- uint32_t inputaddr = 0U;
- uint32_t outputaddr = 0U;
- uint32_t tagaddr = 0U;
- uint64_t headerlength = 0U;
- uint64_t inputlength = 0U;
- uint64_t payloadlength = 0U;
-
-
- if (hcryp->State == HAL_CRYP_STATE_READY)
- {
- /* input/output parameters check */
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0U))
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if ((pInputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
- }
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- if (pOutputData == NULL)
- {
- return HAL_ERROR;
- }
-#if defined(AES_CR_NPBLB)
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))
-#endif
- {
- return HAL_ERROR;
- }
- }
-
- /* Process Locked */
- __HAL_LOCK(hcryp);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_BUSY;
-
- /*==============================================*/
- /* GCM/GMAC (or CCM when applicable) init phase */
- /*==============================================*/
- /* In case of init phase, the input data (Key and Initialization Vector) have
- already been entered during the initialization process. No DMA transfer is
- required at that point therefore, the software just waits for the CCF flag
- to be raised. */
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* just wait for hash computation */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- /*===============================*/
- /* GCM/GMAC or CMAC header phase */
- /*===============================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)
- {
- /* Set header phase; for GCM or GMAC, set data-byte at this point */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);
- }
- else
- {
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);
- }
-
-#if !defined(AES_CR_NPBLB)
- /* enter first B0 block in polling mode (no DMA transfer for B0) */
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- inputaddr = (uint32_t)pInputData;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
-
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- }
-#endif
-
- /* No header case */
- if (hcryp->Init.Header == NULL)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
-
- inputaddr = (uint32_t)hcryp->Init.Header;
- if ((hcryp->Init.HeaderSize % 16U) != 0U)
- {
-
- if (hcryp->Init.HeaderSize < 16U)
- {
- CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);
-
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
-
- /* CCF flag indicating header phase AES processing completion
- will be checked at the start of the next phase:
- - payload phase (GCM / CCM when applicable)
- - final phase (GMAC or CMAC). */
- }
- else
- {
- /* Local variable headerlength is a number of bytes multiple of 128 bits,
- remaining header data (if any) are handled after this loop */
- headerlength = (((hcryp->Init.HeaderSize)/16U)*16U) ;
- /* Store the ending transfer point */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;
- hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */
-
- /* Set the input and output addresses and start DMA transfer */
- /* (incomplete DMA transfer, will be wrapped up after completion of
- the first one (initiated here) with data padding */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0U);
- }
- }
- else
- {
- hcryp->CrypInCount = 0U;
- /* Set the input address and start DMA transfer */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0U);
- }
-
- }
- /*============================================*/
- /* GCM (or CCM when applicable) payload phase */
- /*============================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
- {
- /* Coming from header phase, wait for CCF flag to be raised
- if header present and fed to the IP in the previous phase */
- if (hcryp->Init.Header != NULL)
- {
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- }
- else
- {
- /* Enable the Peripheral since wasn't in header phase (no header case) */
- __HAL_CRYP_ENABLE();
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);
-
- /* Specific handling to manage payload size less than 128 bits */
- if ((Size % 16U) != 0U)
- {
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
- if (Size < 16U)
- {
- /* Block is now entered in polling mode, no actual gain in resorting to DMA */
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
-
- CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON);
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
- }
- else
- {
- payloadlength = (Size/16U) * 16U;
-
- /* Store the ending transfer points */
- hcryp->pCrypInBuffPtr = pInputData + payloadlength;
- hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;
- hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */
-
- /* Set the input and output addresses and start DMA transfer */
- /* (incomplete DMA transfer, will be wrapped up with data padding
- after completion of the one initiated here) */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);
- }
- }
- else
- {
- hcryp->CrypInCount = 0U;
- inputaddr = (uint32_t)pInputData;
- outputaddr = (uint32_t)pOutputData;
-
- /* Set the input and output addresses and start DMA transfer */
- CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
- }
- }
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- /* If coming from header phase (GMAC or CMAC case),
- wait for CCF flag to be raised */
- if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE)
- {
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- }
-
- tagaddr = (uint32_t)pOutputData;
-
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);
-
- /* if the header and payload phases have been bypassed, AES must be enabled again */
- if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)
- {
- __HAL_CRYP_ENABLE();
- }
-
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)
- {
- headerlength = hcryp->Init.HeaderSize * 8U; /* Header length in bits */
- inputlength = Size * 8U; /* input length in bits */
- /* Write the number of bits in the header on 64 bits followed by the number
- of bits in the payload on 64 bits as well */
- if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
- {
- hcryp->Instance->DINR = __RBIT((headerlength)>>32U);
- hcryp->Instance->DINR = __RBIT(headerlength);
- hcryp->Instance->DINR = __RBIT((inputlength)>>32U);
- hcryp->Instance->DINR = __RBIT(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
- {
- hcryp->Instance->DINR = __REV((headerlength)>>32U);
- hcryp->Instance->DINR = __REV(headerlength);
- hcryp->Instance->DINR = __REV((inputlength)>>32U);
- hcryp->Instance->DINR = __REV(inputlength);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
- {
- hcryp->Instance->DINR = __ROR((headerlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(headerlength, 16U);
- hcryp->Instance->DINR = __ROR((inputlength)>>32U, 16U);
- hcryp->Instance->DINR = __ROR(inputlength, 16U);
- }
- else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)
- {
- hcryp->Instance->DINR = (uint32_t)(headerlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(headerlength);
- hcryp->Instance->DINR = (uint32_t)(inputlength>>32U);
- hcryp->Instance->DINR = (uint32_t)(inputlength);
- }
- }
-#if !defined(AES_CR_NPBLB)
- else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
- {
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- inputaddr = (uint32_t)pInputData;
- /* Enter the last block made of a 128-bit value formatted
- from the original B0 packet. */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
-#endif
-
- /* No DMA transfer is required at that point therefore, the software
- just waits for the CCF flag to be raised. */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Read the Auth TAG in the IN FIFO */
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- tagaddr+=4U;
- *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
-
- /* Mark that the final phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- }
- /*=================================================*/
- /* case incorrect hcryp->Init.GCMCMACPhase setting */
- /*=================================================*/
- else
- {
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions
- * @brief Extended processing functions.
- *
-@verbatim
- ==============================================================================
- ##### AES extended suspension and resumption functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) save in memory the Initialization Vector, the Key registers, the Control register or
- the Suspend registers when a process is suspended by a higher priority message
- (+) write back in CRYP hardware block the saved values listed above when the suspended
- lower priority message processing is resumed.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief In case of message processing suspension, read the Initialization Vector.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Initialization Vector.
- * @note This value has to be stored for reuse by writing the AES_IVRx registers
- * as soon as the interrupted processing has to be resumed.
- * Applicable to all chaining modes.
- * @note AES must be disabled when reading or resetting the IV values.
- * @retval None
- */
-void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);
-}
-
-/**
- * @brief In case of message processing resumption, rewrite the Initialization
- * Vector in the AES_IVRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved Initialization Vector to
- * write back in the CRYP hardware block.
- * @note Applicable to all chaining modes.
- * @note AES must be disabled when reading or resetting the IV values.
- * @retval None
- */
-void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- uint32_t ivaddr = (uint32_t)Input;
-
- hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Suspend Registers.
- * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- /* In case of GCM payload phase encryption, check that suspension can be carried out */
- if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))
- {
- /* Ensure that Busy flag is reset */
- if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;
- hcryp->State = HAL_CRYP_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- HAL_CRYP_ErrorCallback(hcryp);
- return ;
- }
- }
-
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend
- * Registers in the AES_SUSPxR registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved suspend registers to
- * write back in the CRYP hardware block.
- * @retval None
- */
-void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- uint32_t ivaddr = (uint32_t)Input;
-
- hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));
- ivaddr+=4U;
- hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Key Registers.
- * @param KeySize Indicates the key size (128 or 256 bits).
- * @note These values have to be stored for reuse by writing back the AES_KEYRx registers
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Output;
-
- if (KeySize == CRYP_KEYSIZE_256B)
- {
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);
- keyaddr+=4U;
- }
-
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);
- keyaddr+=4U;
- *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0);
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key
- * Registers in the AES_KEYRx registers.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved key registers to
- * write back in the CRYP hardware block.
- * @param KeySize Indicates the key size (128 or 256 bits)
- * @retval None
- */
-void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)
-{
- uint32_t keyaddr = (uint32_t)Input;
-
- if (KeySize == CRYP_KEYSIZE_256B)
- {
- hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- }
-
- hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));
- keyaddr+=4U;
- hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));
-}
-
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the buffer containing the saved Control Register.
- * @note This values has to be stored for reuse by writing back the AES_CR register
- * as soon as the interrupted processing has to be resumed.
- * @retval None
- */
-void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)
-{
- *(uint32_t*)(Output) = hcryp->Instance->CR;
-}
-
-/**
- * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control
- * Registers in the AES_CR register.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the buffer containing the saved Control Register to
- * write back in the CRYP hardware block.
- * @retval None
- */
-void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)
-{
- hcryp->Instance->CR = *(uint32_t*)(Input);
- /* At the same time, set handle state back to READY to be able to resume the AES calculations
- without the processing APIs returning HAL_BUSY when called. */
- hcryp->State = HAL_CRYP_STATE_READY;
-}
-
-/**
- * @brief Request CRYP processing suspension when in polling or interruption mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @note Set the handle field SuspendRequest to the appropriate value so that
- * the on-going CRYP processing is suspended as soon as the required
- * conditions are met.
- * @note It is advised not to suspend the CRYP processing when the DMA controller
- * is managing the data transfer
- * @retval None
- */
-void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
-{
- /* Set Handle Suspend Request field */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup CRYPEx_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA CRYP Input Data process complete callback
- * for GCM, GMAC or CMAC chainging modes.
- * @note Specific setting of hcryp fields are required only
- * in the case of header phase where no output data DMA
- * transfer is on-going (only input data transfer is enabled
- * in such a case).
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- uint32_t difflength = 0U;
-
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
- if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
-
- if (hcryp->CrypInCount != 0U)
- {
- /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0U;
-
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);
- }
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
- }
- /* CCF flag indicating header phase AES processing completion
- will be checked at the start of the next phase:
- - payload phase (GCM or CCM when applicable)
- - final phase (GMAC or CMAC).
- This allows to avoid the Wait on Flag within the IRQ handling. */
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback
- * for GCM, GMAC or CMAC chainging modes.
- * @note This callback is called only in the payload phase.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- uint32_t difflength = 0U;
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Initiate additional transfer to wrap-up data feeding to the IP */
- if (hcryp->CrypInCount != 0U)
- {
- /* Last block is now entered in polling mode, no actual gain in resorting to DMA */
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0U;
-
- CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback
- * for GCM, GMAC or CMAC chainging modes.
- * @param hdma DMA handle
- * @retval None
- */
-static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hcryp->State= HAL_CRYP_STATE_ERROR;
- hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
- HAL_CRYP_ErrorCallback(hcryp);
- /* Clear Error Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
-}
-
-/**
- * @brief Handle CRYP block input/output data handling under interruption
- * for GCM, GMAC or CMAC chaining modes.
- * @note The function is called under interruption only, once
- * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @retval HAL status
- */
-HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
-{
- uint32_t inputaddr = 0x0U;
- uint32_t outputaddr = 0x0U;
- uint32_t index = 0x0U;
- uint32_t addhoc_process = 0U;
- uint32_t difflength = 0U;
- uint32_t difflengthmod4 = 0U;
- uint32_t mask[3] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
- uint32_t intermediate_data[4U] = {0U};
-
- if(hcryp->State == HAL_CRYP_STATE_BUSY)
- {
- /*===========================*/
- /* GCM/GMAC(/CCM) init phase */
- /*===========================*/
- if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Mark that the initialization phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- return HAL_OK;
- }
- /*=====================================*/
- /* GCM/GMAC or (CCM/)CMAC header phase */
- /*=====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)
- {
- /* Check if all input header data have been entered */
- if (hcryp->CrypInCount == 0U)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
-
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
- {
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else /* Carry on feeding input data to the CRYP hardware block */
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last Input data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;
- /* Increment/decrement instance pointer/counter */
- if (hcryp->CrypInCount < 16U)
- {
- difflength = hcryp->CrypInCount;
- hcryp->CrypInCount = 0U;
- addhoc_process = 1U;
- difflengthmod4 = difflength%4U;
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
- }
+#else /* AES */
-#if defined(AES_CR_NPBLB)
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)
-#else
- if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
- {
- if (hcryp->CrypInCount == hcryp->Init.HeaderSize)
- {
- /* All B blocks will have been entered after the next
- four DINR writing, so point at header buffer for
- the next iteration */
- hcryp->pCrypInBuffPtr = hcryp->Init.Header;
- }
- }
+ /* Select final phase */
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
- /* Write the Input block in the Data Input register */
- if (addhoc_process == 0U)
- {
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- }
- else
- {
- /* Header remainder has size less than 128 bits */
- /* Enter complete words when possible */
- for(index=0U; index < (difflength/4U); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0U)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- hcryp->Instance->DINR = 0U;
- }
- }
+ /* Write the counter block in the IN FIFO, CTR0 information from B0
+ data has to be swapped according to the DATATYPE*/
+ if(hcryp->Init.DataType == CRYP_DATATYPE_8B)
+ {
+ ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0);
+ ctr0[1]=__REV(hcryp->Init.B0[1]);
+ ctr0[2]=__REV(hcryp->Init.B0[2]);
+ ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
- return HAL_OK;
- }
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr));
}
- /*=======================*/
- /* GCM/CCM payload phase */
- /*=======================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
- /* Get the last output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-
- /* Specific handling to manage payload size less than 128 bits
- when GCM (or CCM when applicable) encryption or decryption is selected.
- Check here if the last block output data are read */
-#if defined(AES_CR_NPBLB)
- if ((hcryp->CrypOutCount < 16U) && \
- (hcryp->CrypOutCount > 0U))
-#else
- if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \
- (hcryp->CrypOutCount < 16U) && \
- (hcryp->CrypOutCount > 0U))
-#endif
- {
- addhoc_process = 1U;
- difflength = hcryp->CrypOutCount;
- difflengthmod4 = difflength%4U;
- hcryp->CrypOutCount = 0U; /* mark that no more output data will be needed */
- /* Retrieve intermediate data */
- for(index=0U; index < 4U; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- /* Retrieve last words of cyphered data */
- /* First, retrieve complete output words */
- for(index=0U; index < (difflength/4U); index ++)
- {
- *(uint32_t*)(outputaddr) = intermediate_data[index];
- outputaddr+=4U;
- }
- /* Next, retrieve partial output word if applicable;
- at the same time, start masking intermediate data
- with a mask of zeros of same size than the padding
- applied to the last block of payload */
- if (difflengthmod4 != 0U)
- {
- intermediate_data[difflength/4U] &= mask[difflengthmod4-1U];
- *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U];
- }
-
-#if !defined(AES_CR_NPBLB)
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change again CHMOD configuration to GCM mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
-
- /* Select FINAL phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
-
- /* Before inserting the intermediate data, carry on masking operation
- with a mask of zeros of same size than the padding applied to the last block of payload */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- intermediate_data[(difflength+3U)/4U+index] = 0U;
- }
-
- /* Insert intermediate data to trigger an additional DOUTR reading round */
- /* Clear Computation Complete Flag before entering new block */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- for(index=0U; index < 4U; index ++)
- {
- hcryp->Instance->DINR = intermediate_data[index];
- }
- }
- else
-#endif
- {
- /* Payload phase is now over */
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
+ ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0);
+ ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U);
+ ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U);
+ ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3);
+
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U);
+ }
+ else if(hcryp->Init.DataType == CRYP_DATATYPE_1B)
+ {
+ ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0);
+ ctr0[1]=__RBIT(hcryp->Init.B0[1]);
+ ctr0[2]=__RBIT(hcryp->Init.B0[2]);
+ ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3);
+
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr));
+ }
+ else
+ {
+ ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
+ ctr0[1]=hcryp->Init.B0[1];
+ ctr0[2]=hcryp->Init.B0[2];
+ ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ ctr0addr+=4U;
+ hcryp->Instance->DINR = *(uint32_t*)(ctr0addr);
+ }
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- }
- return HAL_OK;
- }
- else
+ /* Wait for CCF flag to be raised */
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- if (hcryp->CrypOutCount != 0U)
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
- /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */
- /* Retrieve the last block available from the CRYP hardware block:
- read the output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
-
- /* Increment/decrement instance pointer/counter */
- hcryp->pCrypOutBuffPtr += 16U;
- hcryp->CrypOutCount -= 16U;
- }
-#if !defined(AES_CR_NPBLB)
- else
- {
- /* Software work-around: additional DOUTR reading round to discard the data */
- for(index=0U; index < 4U; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- }
-#endif
- }
+ /* Disable the CRYP peripheral Clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Check if all output text has been retrieved */
- if (hcryp->CrypOutCount == 0U)
- {
-#if !defined(AES_CR_NPBLB)
- /* Make sure that software-work around is not running before disabling
- the interruptions (indeed, if software work-around is running, the
- interruptions must not be disabled to allow the additional DOUTR
- reading round */
- if (addhoc_process == 0U)
-#endif
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the payload phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
- /* Process Unlocked */
+ /* Process unlocked */
__HAL_UNLOCK(hcryp);
-
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
- }
-
- return HAL_OK;
- }
- /* If suspension flag has been raised, suspend processing */
- else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
- {
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
-
- return HAL_OK;
- }
- else /* Output data are still expected, carry on feeding the CRYP
- hardware block with input data */
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last Input data address */
- inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-
- /* Usual input data feeding case */
- if (hcryp->CrypInCount < 16U)
- {
- difflength = (uint32_t) (hcryp->CrypInCount);
- difflengthmod4 = difflength%4U;
- hcryp->CrypInCount = 0U;
-
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
- /* Insert the last block (which size is inferior to 128 bits) padded with zeroes
- to have a complete block of 128 bits */
- for(index=0U; index < (difflength/4U); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
- /* If required, manage input data size not multiple of 32 bits */
- if (difflengthmod4 != 0U)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1U]);
- }
- /* Wrap-up in padding with zero-words if applicable */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- hcryp->Instance->DINR = 0U;
- }
- }
- else
- {
- hcryp->pCrypInBuffPtr += 16U;
- hcryp->CrypInCount -= 16U;
-
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
+ return HAL_ERROR;
}
-
- return HAL_OK;
}
}
- /*====================================*/
- /* GCM/GMAC or (CCM/)CMAC final phase */
- /*====================================*/
- else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- /* Get the last output data address */
- outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
+ /* Read the authentication TAG in the output FIFO */
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
+ tagaddr+=4U;
+ *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;
- /* Retrieve the last expected data from the CRYP hardware block:
- read the output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Disable Computation Complete Flag and Errors Interrupts */
- __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_READY;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;
+#endif /* End of AES || CRYP */
- /* Disable the Peripheral */
- __HAL_CRYP_DISABLE();
- /* Process Unlocked */
- __HAL_UNLOCK(hcryp);
+ /* Change the CRYP peripheral state */
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Call computation complete callback */
- HAL_CRYPEx_ComputationCpltCallback(hcryp);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
- return HAL_OK;
- }
- else
- {
- /* Clear Computation Complete Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- hcryp->State = HAL_CRYP_STATE_ERROR;
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ /* Disable CRYP */
+ __HAL_CRYP_DISABLE(hcryp);
}
else
{
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Set the DMA configuration and start the DMA transfer
- * for GCM, GMAC or CMAC chainging modes.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param inputaddr Address of the Input buffer.
- * @param Size Size of the Input buffer un bytes, must be a multiple of 16.
- * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream
- * has to be configured.
- * @retval None
- */
-static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
-
- /* Set the input CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError;
-
- if (outputaddr != 0U)
- {
- /* Set the output CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError;
- }
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-
- /* Enable the DMA input stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4U);
-
- /* Enable the DMA input request */
- SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
-
- if (outputaddr != 0U)
- {
- /* Enable the DMA output stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4U);
-
- /* Enable the DMA output request */
- SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
- }
-}
-
-/**
- * @brief Write/read input/output data in polling mode.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Input Pointer to the Input buffer.
- * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16.
- * @param Output Pointer to the returned buffer.
- * @param Timeout Specify Timeout value.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t index = 0U;
- uint32_t inputaddr = (uint32_t)Input;
- uint32_t outputaddr = (uint32_t)Output;
-
-
- for(index=0U; (index < Ilength); index += 16U)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Read the Output block from the Data Output Register */
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;
- outputaddr+=4U;
-
- /* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16U) < Ilength))
- {
- /* Reset SuspendRequest */
- hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
-
- /* Save current reading and writing locations of Input and Output buffers */
- hcryp->pCrypOutBuffPtr = (uint8_t *)outputaddr;
- hcryp->pCrypInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hcryp->CrypInCount = Ilength - (index+16U);
-
- /* Change the CRYP state */
- hcryp->State = HAL_CRYP_STATE_SUSPENDED;
-
- return HAL_OK;
- }
-
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+ return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
-
}
/**
- * @brief Read derivative key in polling mode when CRYP hardware block is set
- * in key derivation operating mode (mode 2).
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Output Pointer to the returned buffer.
- * @param Timeout Specify Timeout value.
- * @retval HAL status
+ * @}
*/
-static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)
-{
- uint32_t outputaddr = (uint32_t)Output;
-
- /* Wait for CCF flag to be raised */
- if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- return HAL_TIMEOUT;
- }
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR);
-
- /* Read the derivative key from the AES_KEYRx registers */
- if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)
- {
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);
- outputaddr+=4U;
- }
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);
-
- /* Return function status */
- return HAL_OK;
-}
+#if defined (AES)
+/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions
+ * @brief AutoKeyDerivation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Key Derivation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to Enable or Disable the
+ the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
+ These function are allowed only in TinyAES IP.
-/**
- * @brief Set the DMA configuration and start the DMA transfer.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param inputaddr Address of the Input buffer.
- * @param Size Size of the Input buffer in bytes, must be a multiple of 16.
- * @param outputaddr Address of the Output buffer.
- * @retval None
+@endverbatim
+ * @{
*/
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
- /* Set the DMA error callback */
- hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-
- /* Set the CRYP DMA transfer complete callback */
- hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
- /* Set the DMA error callback */
- hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
- /* Enable the DMA input stream */
- HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4U);
-
- /* Enable the DMA output stream */
- HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4U);
-
- /* Enable In and Out DMA requests */
- SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE();
-}
/**
- * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout Timeout duration.
- * @retval HAL status
+ * @brief AES enable key derivation functions
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure.
+ * @retval None
*/
-static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- uint32_t tickstart = 0U;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- return HAL_TIMEOUT;
- }
- }
+ hcryp->AutoKeyDerivation = ENABLE;
}
- return HAL_OK;
-}
-
-/**
- * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param Timeout Timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))
+ else
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- return HAL_TIMEOUT;
- }
- }
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
}
- return HAL_OK;
-}
-
-/**
- * @brief DMA CRYP Input Data process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for input request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
-
- /* Call input data transfer complete callback */
- HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP Output Data process complete callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable the DMA transfer for output request */
- CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
-
- /* Disable CRYP */
- __HAL_CRYP_DISABLE();
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Call output data transfer complete callback */
- HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
- * @brief DMA CRYP communication error callback.
- * @param hdma DMA handle.
- * @retval None
- */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
- CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- hcryp->State= HAL_CRYP_STATE_ERROR;
- hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
- HAL_CRYP_ErrorCallback(hcryp);
- /* Clear Error Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);
}
-
/**
- * @brief Last header or payload block padding when size is not a multiple of 128 bits.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module.
- * @param difflength size remainder after having fed all complete 128-bit blocks.
- * @param polling specifies whether or not polling on CCF must be done after having
- * entered a complete block.
+ * @brief AES disable key derivation functions
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure.
* @retval None
*/
-static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)
+void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
{
- uint32_t index = 0U;
- uint32_t difflengthmod4 = difflength%4U;
- uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
- uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- uint32_t mask[3U] = {0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
- uint32_t intermediate_data[4U] = {0U};
-
-#if defined(AES_CR_NPBLB)
- /* In case of GCM encryption or CCM decryption, specify the number of padding
- bytes in last block of payload */
- if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)
- {
- if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))
- || ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)
- && (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))
- {
- /* Set NPBLB field in writing the number of padding bytes
- for the last block of payload */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16U - difflength);
- }
- }
-#else
- /* Software workaround applied to GCM encryption only */
- if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) &&
- (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))
- {
- /* Change the mode configured in CHMOD bits of CR register to select CTR mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);
- }
-#endif
-
- /* Wrap-up entering header or payload data */
- /* Enter complete words when possible */
- for(index=0U; index < (difflength/4U); index ++)
- {
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t*)(inputaddr);
- inputaddr+=4U;
- }
- /* Enter incomplete word padded with zeroes if applicable
- (case of header length not a multiple of 32-bits) */
- if (difflengthmod4 != 0U)
- {
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
- }
- /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
+ if(hcryp->State == HAL_CRYP_STATE_READY)
{
- hcryp->Instance->DINR = 0U;
+ hcryp->AutoKeyDerivation = DISABLE;
}
-
- if (polling == CRYP_POLLING_ON)
+ else
{
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
+ /* Busy error code field */
+ hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
}
-
- /* if payload */
- if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)
- {
-
- /* Retrieve intermediate data */
- for(index=0U; index < 4U; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
- /* Retrieve last words of cyphered data */
- /* First, retrieve complete output words */
- for(index=0U; index < (difflength/4U); index ++)
- {
- *(uint32_t*)(outputaddr) = intermediate_data[index];
- outputaddr+=4U;
- }
- /* Next, retrieve partial output word if applicable;
- at the same time, start masking intermediate data
- with a mask of zeros of same size than the padding
- applied to the last block of payload */
- if (difflengthmod4 != 0U)
- {
- intermediate_data[difflength/4U] &= mask[difflengthmod4-1U];
- *(uint32_t*)(outputaddr) = intermediate_data[difflength/4U];
- }
-
-#if !defined(AES_CR_NPBLB)
- /* Software workaround applied to GCM encryption only,
- applicable for AES IP v2 version (where NPBLB is not defined) */
- if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)
- {
- /* Change again CHMOD configuration to GCM mode */
- __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);
-
- /* Select FINAL phase */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);
-
- /* Before inserting the intermediate data, carry on masking operation
- with a mask of zeros of same size than the padding applied to the last block of payload */
- for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++)
- {
- intermediate_data[(difflength+3U)/4U+index] = 0U;
- }
- /* Insert intermediate data */
- for(index=0U; index < 4U; index ++)
- {
- hcryp->Instance->DINR = intermediate_data[index];
- }
-
- /* Wait for completion, and read data on DOUT. This data is to discard. */
- if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)
- {
- hcryp->State = HAL_CRYP_STATE_READY;
- __HAL_UNLOCK(hcryp);
- HAL_CRYP_ErrorCallback(hcryp);
- }
-
- /* Read data to discard */
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);
- for(index=0U; index < 4U; index ++)
- {
- intermediate_data[index] = hcryp->Instance->DOUTR;
- }
-
- } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */
-#endif /* !defined(AES_CR_NPBLB) */
- } /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */
-
}
/**
* @}
*/
-
+#endif /* AES or GCM CCM defined*/
#endif /* AES */
-
#endif /* HAL_CRYP_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+#endif /* TinyAES or CRYP*/
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac.c
index 321ab9a61f2d3b3e42015f4059122168a73db76e..03453823d5f6f4d2efbb6b9f9819a4282b04e6b8 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac.c
@@ -122,6 +122,61 @@
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ (+) All Callbacks
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+ and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+ or @ref HAL_DAC_Init function.
+
+ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
[..]
@@ -139,29 +194,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -239,10 +278,32 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
if(hdac->State == HAL_DAC_STATE_RESET)
{
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the DAC Callback settings */
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+ if(hdac->MspInitCallback == NULL)
+ {
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the low level hardware */
+ hdac->MspInitCallback(hdac);
+#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
@@ -278,8 +339,17 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ if(hdac->MspDeInitCallback == NULL)
+ {
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdac->MspDeInitCallback(hdac);
+#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
@@ -656,7 +726,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
/* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh1(hdac);
+#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
@@ -674,7 +748,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
/* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->DMAUnderrunCallbackCh2(hdac);
+#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
@@ -898,6 +976,250 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DAC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ *
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if(hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+
+/**
+ * @brief Unregister a User DAC Callback
+ * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if(hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ break;
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ case HAL_DAC_ALL_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSP_INIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSP_DEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -908,7 +1230,11 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh1(hdac);
+#else
HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
@@ -923,7 +1249,11 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh1(hdac);
+#else
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
@@ -939,7 +1269,11 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh1(hdac);
+#else
HAL_DAC_ErrorCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac_ex.c
index 6fae4d4331e226af03a48260b976b872dbe12d8e..8914ab6276ff1a66ab7b1c4947ec282dd1b3eb8e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dac_ex.c
@@ -23,29 +23,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -331,7 +315,11 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
@@ -346,7 +334,11 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
@@ -362,7 +354,11 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh2(hdac);
+#else
HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State= HAL_DAC_STATE_READY;
}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi.c
index 686d94c44b04a2cb52527867f4e82c6b2c7964f1..a1a3224c0f3a283a96de2ad6f61d54a4125773f5 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi.c
@@ -57,33 +57,67 @@
[..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
+
+ Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
+ (+) FrameEventCallback : DCMI Frame Event.
+ (+) VsyncEventCallback : DCMI Vsync Event.
+ (+) LineEventCallback : DCMI Line Event.
+ (+) ErrorCallback : DCMI error.
+ (+) MspInitCallback : DCMI MspInit.
+ (+) MspDeInitCallback : DCMI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ This function allows to reset following callbacks:
+ (+) FrameEventCallback : DCMI Frame Event.
+ (+) VsyncEventCallback : DCMI Vsync Event.
+ (+) LineEventCallback : DCMI Line Event.
+ (+) ErrorCallback : DCMI error.
+ (+) MspInitCallback : DCMI MspInit.
+ (+) MspDeInitCallback : DCMI MspDeInit.
+
+ By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
+ and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
+ or @ref HAL_DCMI_Init function.
+
+ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -164,6 +198,24 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
/* Allocate lock resource and initialize it */
hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
+ /* Init the DCMI Callback settings */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if(hdcmi->MspInitCallback == NULL)
+ {
+ /* Legacy weak MspInit Callback */
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ }
+ /* Initialize the low level hardware (MSP) */
+ hdcmi->MspInitCallback(hdcmi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_DCMI_MspInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
HAL_DCMI_MspInit(hdcmi);
}
@@ -210,8 +262,17 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
- /* DeInit the low level hardware */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ if(hdcmi->MspDeInitCallback == NULL)
+ {
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ }
+ /* De-Initialize the low level hardware (MSP) */
+ hdcmi->MspDeInitCallback(hdcmi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspDeInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@@ -390,6 +451,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
status = HAL_TIMEOUT;
+ break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
@@ -538,7 +600,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI line event callback*/
+ hdcmi->LineEventCallback(hdcmi);
+#else
HAL_DCMI_LineEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
@@ -547,7 +614,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI vsync event callback*/
+ hdcmi->VsyncEventCallback(hdcmi);
+#else
HAL_DCMI_VsyncEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
@@ -563,7 +635,12 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Frame Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI frame event callback*/
+ hdcmi->FrameEventCallback(hdcmi);
+#else
HAL_DCMI_FrameEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
}
@@ -777,10 +854,175 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
return hdcmi->ErrorCode;
}
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
- * @}
+ * @brief DCMI Callback registering
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+ * the configuration information for DCMI.
+ * @param CallbackID dcmi Callback ID
+ * @param pCallback pointer to DCMI_CallbackTypeDef structure
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief DCMI Callback Unregistering
+ * @param hdcmi dcmi handle
+ * @param CallbackID dcmi Callback ID
+ * @retval status
*/
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(hdcmi->State == HAL_DCMI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_FRAME_EVENT_CB_ID :
+ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
+ break;
+
+ case HAL_DCMI_VSYNC_EVENT_CB_ID :
+ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
+ break;
+
+ case HAL_DCMI_LINE_EVENT_CB_ID :
+ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_DCMI_ERROR_CB_ID :
+ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hdcmi->State == HAL_DCMI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DCMI_MSPINIT_CB_ID :
+ hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+ break;
+
+ case HAL_DCMI_MSPDEINIT_CB_ID :
+ hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+ break;
+
+ default :
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
@@ -860,7 +1102,13 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
}
/* DCMI error Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+ /*Call registered DCMI error callback*/
+ hdcmi->ErrorCallback(hdcmi);
+#else
HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi_ex.c
index 13eb650092bba062241d38b334b6d5e645eeea1c..b6b66b51eee86efdfc6b38c1d09e428b55a2e28b 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dcmi_ex.c
@@ -25,29 +25,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dfsdm.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dfsdm.c
index 94113ca3c5df60756bd21b9a08d2add75fc4d69e..d04c3381b0868961ec4ce16f246f7cc7fc124064 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dfsdm.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dfsdm.c
@@ -155,33 +155,96 @@
[..]
(#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
+ @ref HAL_DFSDM_Filter_RegisterCallback() or
+ @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+
+ Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+ following callbacks:
+ (+) CkabCallback : DFSDM channel clock absence detection callback.
+ (+) ScdCallback : DFSDM channel short circuit detection callback.
+ (+) MspInitCallback : DFSDM channel MSP init callback.
+ (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+ following callbacks:
+ (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
+ (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
+ (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback.
+ (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
+ (+) ErrorCallback : DFSDM filter error callback.
+ (+) MspInitCallback : DFSDM filter MSP init callback.
+ (+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific DFSDM filter analog watchdog callback use dedicated register callback:
+ @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+
+ Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
+ @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+ weak function.
+
+ @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) CkabCallback : DFSDM channel clock absence detection callback.
+ (+) ScdCallback : DFSDM channel short circuit detection callback.
+ (+) MspInitCallback : DFSDM channel MSP init callback.
+ (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+
+ @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
+ (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
+ (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback.
+ (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback.
+ (+) ErrorCallback : DFSDM filter error callback.
+ (+) MspInitCallback : DFSDM filter MSP init callback.
+ (+) MspDeInitCallback : DFSDM filter MSP de-init callback.
+
+ For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
+ @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+
+ By default, after the call of init function and if the state is RESET
+ all callbacks are reset to the corresponding legacy weak functions:
+ examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak functions in the init and de-init only when these
+ callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the init and de-init keep and use
+ the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the init/de-init.
+ In that case first register the MspInit/MspDeInit user callbacks using
+ @ref HAL_DFSDM_Channel_RegisterCallback() or
+ @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+
+ When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -334,8 +397,21 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
return HAL_ERROR;
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+
+ /* Call MSP init function */
+ if(hdfsdm_channel->MspInitCallback == NULL)
+ {
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ }
+ hdfsdm_channel->MspInitCallback(hdfsdm_channel);
+#else
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+#endif
/* Update the channel counter */
(*channelCounterPtr)++;
@@ -400,8 +476,21 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
return HAL_ERROR;
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+
+ /* Call MSP init function */
+ if(hdfsdm_channel->MspInitCallback == NULL)
+ {
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ }
+ hdfsdm_channel->MspInitCallback(hdfsdm_channel);
+#else
/* Call MSP init function */
HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
+#endif
/* Update the channel counter */
v_dfsdm1ChannelCounter++;
@@ -519,7 +608,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
}
/* Call MSP deinit function */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ if(hdfsdm_channel->MspDeInitCallback == NULL)
+ {
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ }
+ hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
+#else
HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+#endif
/* Set DFSDM Channel in reset state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
@@ -546,7 +643,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
}
/* Call MSP deinit function */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ if(hdfsdm_channel->MspDeInitCallback == NULL)
+ {
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ }
+ hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
+#else
HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
+#endif
/* Set DFSDM Channel in reset state */
hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
@@ -586,6 +691,143 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann
*/
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user DFSDM channel callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
+ pDFSDM_Channel_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
+ hdfsdm_channel->CkabCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_SCD_CB_ID :
+ hdfsdm_channel->ScdCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM channel callback.
+ * DFSDM channel callback is redirected to the weak predefined callback.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+ HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
+ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_SCD_CB_ID :
+ hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
+ hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
+ break;
+ case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
+ hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -770,7 +1012,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1124,7 +1366,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
}
/* Clear short circuit detection flag */
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#else
/* Get timeout */
@@ -1136,7 +1378,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1145,7 +1387,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd
}
/* Clear short circuit detection flag */
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#endif /* DFSDM2_Channel0 */
/* Return function status */
@@ -1194,9 +1436,9 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c
filter0Instance = DFSDM2_Filter0;
}
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#else
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
#endif /* DFSDM2_Channel0*/
}
/* Return function status */
@@ -1319,12 +1561,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
filter0Instance = DFSDM2_Filter0;
}
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Disable short circuit detection interrupt */
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
#else
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Disable short circuit detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
@@ -1470,8 +1712,25 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
hdfsdm_filter->InjConvRemaining = 1U;
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
+ hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
+ hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
+ hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
+ hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
+ hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
+
+ /* Call MSP init function */
+ if(hdfsdm_filter->MspInitCallback == NULL)
+ {
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ }
+ hdfsdm_filter->MspInitCallback(hdfsdm_filter);
+#else
/* Call MSP init function */
HAL_DFSDM_FilterMspInit(hdfsdm_filter);
+#endif
/* Set regular parameters */
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
@@ -1561,7 +1820,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
/* Call MSP deinit function */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ if(hdfsdm_filter->MspDeInitCallback == NULL)
+ {
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ }
+ hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
+#endif
/* Set DFSDM filter in reset state */
hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
@@ -1597,6 +1864,241 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
*/
}
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user DFSDM filter callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
+ pDFSDM_Filter_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->RegConvCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->InjConvCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_ERROR_CB_ID :
+ hdfsdm_filter->ErrorCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = pCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM filter callback.
+ * DFSDM filter callback is redirected to the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
+ hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
+ hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
+ break;
+ case HAL_DFSDM_FILTER_ERROR_CB_ID :
+ hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
+ break;
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
+ hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
+ break;
+ case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
+ hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Register a user DFSDM filter analog watchdog callback
+ * to be used instead of the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pCallback pointer to the DFSDM filter analog watchdog callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+ pDFSDM_Filter_AwdCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ hdfsdm_filter->AwdCallback = pCallback;
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user DFSDM filter analog watchdog callback.
+ * DFSDM filter AWD callback is redirected to the weak predefined callback.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
+ {
+ hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
+ }
+ else
+ {
+ /* update the error code */
+ hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -1795,7 +2297,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1807,7 +2309,11 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
/* Clear regular overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
@@ -2199,7 +2705,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if( ((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -2211,7 +2717,11 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
{
/* Update error code and call error callback */
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
/* Clear injected overrun flag */
hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
@@ -2802,7 +3312,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/* Check if overrun occurs during injected conversion */
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
@@ -2815,14 +3329,22 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/* Check if end of regular conversion */
else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
{
/* Call regular conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+#endif
/* End of conversion if mode is not continuous and software trigger */
if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
@@ -2841,7 +3363,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
{
/* Call injected conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+#endif
/* Update remaining injected conversions */
hdfsdm_filter->InjConvRemaining--;
@@ -2888,7 +3414,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
(1U << channel);
/* Call analog watchdog callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
+#else
HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
+#endif
}
/* Check if clock absence occurs */
else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
@@ -2912,7 +3442,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
+#endif
}
}
channel++;
@@ -2942,7 +3476,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm2ChannelHandle[channel]->CkabCallback(a_dfsdm2ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
+#endif
}
}
channel++;
@@ -2967,10 +3505,14 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Call short circuit detection callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
+#endif
}
#if defined (DFSDM2_Channel0)
/* Check if short circuit detection occurs */
@@ -2990,10 +3532,14 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
/* Call short circuit detection callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ a_dfsdm2ChannelHandle[channel]->ScdCallback(a_dfsdm2ChannelHandle[channel]);
+#else
HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
+#endif
}
#endif /* DFSDM2_Channel0 */
}
@@ -3512,7 +4058,11 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular half conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -3526,7 +4076,11 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call regular conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -3540,7 +4094,11 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected half conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -3554,7 +4112,11 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
/* Call injected conversion complete callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
+#endif
}
/**
@@ -3571,7 +4133,11 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
/* Call error callback */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+ hdfsdm_filter->ErrorCallback(hdfsdm_filter);
+#else
HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
+#endif
}
/**
@@ -3640,6 +4206,10 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
{
channel = 7U;
}
+ else
+ {
+ /* channel = 0xFFU;*/
+ }
#else
if(Instance == DFSDM1_Channel0)
{
@@ -3657,6 +4227,10 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
{
channel = 3U;
}
+ else
+ {
+ /* channel = 0xFFU;*/
+ }
#endif /* defined(DFSDM2_Channel0) */
return channel;
@@ -3804,6 +4378,10 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Enable DFSDM filter */
hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma.c
index c2b73362061574ad001cd037d9665596ec37d9b9..4c7e690d47151569d6674ceea418f39133fd4d1f 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma.c
@@ -83,29 +83,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -367,13 +351,21 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ /* Clean all callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
- /* Initialize the error code */
+ /* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Initialize the DMA state */
+ /* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma2d.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma2d.c
index d27f92ddad958a5a676b7d681fbdbeb95ef32419..8ca7ae713a5ceee7075694b7081f9f1d0e878d72 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma2d.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma2d.c
@@ -21,8 +21,8 @@
(#) Program the required configuration through the following parameters:
the input color mode, the input color, the input alpha value, the alpha mode,
- and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
- or/and background layer.
+ the red/blue swap mode, the inverted alpha mode and the input offset using
+ HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
*** Polling mode IO operation ***
=================================
@@ -37,11 +37,11 @@
[..]
(#) Configure pdata parameter, destination and data length and enable
the transfer using HAL_DMA2D_Start_IT().
- (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
+ (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback (member
of DMA2D handle structure).
- (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
+ (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
XferErrorCallback.
-@- In Register-to-Memory transfer mode, pdata parameter is the register
@@ -51,7 +51,7 @@
-@- Configure the foreground source address, the background source address,
the destination and data length then Enable the transfer using
HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
- in interrupt mode
+ in interrupt mode.
-@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
are used if the memory to memory with blending transfer mode is selected.
@@ -59,7 +59,7 @@
(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
- (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
+ (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
@@ -87,7 +87,60 @@
(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
- (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
+
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) XferCpltCallback : callback for transfer complete.
+ (+) XferErrorCallback : callback for transfer error.
+ (+) LineEventCallback : callback for line event.
+ (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
+ (+) MspInitCallback : DMA2D MspInit.
+ (+) MspDeInitCallback : DMA2D MspDeInit.
+
+ (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+ and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
+ as weak (surcharged) functions. They must be defined by the user to be resorted to.
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
+ or @ref HAL_DMA2D_Init function.
+
+ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -96,29 +149,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -126,6 +163,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
@@ -135,10 +175,6 @@
* @{
*/
-#ifdef HAL_DMA2D_MODULE_ENABLED
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
@@ -148,30 +184,8 @@
/** @defgroup DMA2D_TimeOut DMA2D Time Out
* @{
*/
-#define DMA2D_TIMEOUT_ABORT 1000U /*!< 1s */
-#define DMA2D_TIMEOUT_SUSPEND 1000U /*!< 1s */
-/**
- * @}
- */
-
-/** @defgroup DMA2D_Shifts DMA2D Shifts
- * @{
- */
-#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */
-#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */
-
-#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */
-#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */
-
-#define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */
-
-#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */
-#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */
-
-#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */
-#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */
-
-#define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */
+#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
+#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
/**
* @}
*/
@@ -184,7 +198,7 @@
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup DMA2D_Private_Functions_Prototypes
+/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
@@ -234,6 +248,21 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ if (hdma2d->State == HAL_DMA2D_STATE_RESET)
+ {
+ /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ if(hdma2d->MspInitCallback == NULL)
+ {
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hdma2d->MspInitCallback(hdma2d);
+ }
+#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -241,6 +270,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
}
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
@@ -254,6 +284,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
+
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
@@ -273,6 +304,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
{
+
/* Check the DMA2D peripheral state */
if(hdma2d == NULL)
{
@@ -318,16 +350,29 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
}
}
+ /* Reset DMA2D control registers*/
+ hdma2d->Instance->CR = 0U;
+ hdma2d->Instance->IFCR = 0x3FU;
+ hdma2d->Instance->FGOR = 0U;
+ hdma2d->Instance->BGOR = 0U;
+ hdma2d->Instance->FGPFCCR = 0U;
+ hdma2d->Instance->BGPFCCR = 0U;
+ hdma2d->Instance->OPFCCR = 0U;
+
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+
+ if(hdma2d->MspDeInitCallback == NULL)
+ {
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hdma2d->MspDeInitCallback(hdma2d);
+
+#else
/* Carry on with de-initialization of low level hardware */
HAL_DMA2D_MspDeInit(hdma2d);
-
- /* Reset DMA2D control registers*/
- hdma2d->Instance->CR = 0U;
- hdma2d->Instance->FGOR = 0U;
- hdma2d->Instance->BGOR = 0U;
- hdma2d->Instance->FGPFCCR = 0U;
- hdma2d->Instance->BGPFCCR = 0U;
- hdma2d->Instance->OPFCCR = 0U;
+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
@@ -373,10 +418,202 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
*/
}
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DMA2D Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+
+/**
+ * @brief Unregister a DMA2D Callback
+ * DMA2D Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdma2d DMA2D handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
+ * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
+ * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
+ * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
+ * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
+ * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
+ * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
+{
+HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma2d);
+
+ if(HAL_DMA2D_STATE_READY == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
+ hdma2d->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA2D_TRANSFERERROR_CB_ID :
+ hdma2d->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA2D_LINEEVENT_CB_ID :
+ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
+ break;
+
+ case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
+ hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
+ break;
+
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA2D_MSPINIT_CB_ID :
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_DMA2D_MSPDEINIT_CB_ID :
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma2d);
+ return status;
+}
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
/**
* @}
*/
+
/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@@ -407,6 +644,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
(+) Transfer watermark callback.
(+) CLUT Transfer Complete callback.
+
@endverbatim
* @{
*/
@@ -563,7 +801,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
*/
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Abort the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
@@ -575,7 +813,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively disabled */
- while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
{
@@ -612,20 +850,19 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
*/
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Suspend the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
- effect on START bitvalue) */
+ effect on START bitvalue). */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
+ while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
{
@@ -640,7 +877,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
@@ -672,19 +909,20 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
/* Resume the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
- effect on START bitvalue) */
+ effect on START bitvalue). */
CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
return HAL_OK;
}
+
/**
* @brief Enable the DMA2D CLUT Transfer.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
@@ -698,7 +936,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- if(LayerIdx == 0U)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Enable the background CLUT loading */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -712,6 +950,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
return HAL_OK;
}
+
/**
* @brief Start DMA2D CLUT Loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
@@ -720,7 +959,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
* @retval HAL status
*/
@@ -738,14 +977,14 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0U)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -758,7 +997,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -775,7 +1014,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -792,14 +1031,14 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0U)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
@@ -815,7 +1054,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
@@ -833,28 +1072,29 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- uint32_t tickstart = 0U;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ uint32_t tickstart;
+ const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Abort the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1)
+ if(LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
+
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the CLUT loading is aborted */
- while((*reg & DMA2D_BGPFCCR_START) != RESET)
+ while((*reg & DMA2D_BGPFCCR_START) != 0U)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
{
@@ -889,19 +1129,20 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- uint32_t tickstart = 0U;
- __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
+ uint32_t tickstart;
+ uint32_t loadsuspended;
+ const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Suspend the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
/* If foreground CLUT loading is considered, update local variables */
- if(LayerIdx == 1U)
+ if(LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
@@ -910,8 +1151,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
tickstart = HAL_GetTick();
/* Check if the CLUT loading is suspended */
- while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
- && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
+ while (loadsuspended == 0UL)
{
if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
{
@@ -923,10 +1165,12 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
return HAL_TIMEOUT;
}
+ loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
+ loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
- if ((*reg & DMA2D_BGPFCCR_START) != RESET)
+ if ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
@@ -946,32 +1190,36 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the SUSP and START bits for background or foreground CLUT loading */
- if(LayerIdx == 0U)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Background CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
+ if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
+ {
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
+ }
else
{
/* Foreground CLUT loading suspension check */
- if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
- && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
+ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
+ if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
+ {
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
+ }
/* Resume the CLUT loading */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
@@ -979,7 +1227,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint
return HAL_OK;
}
+
/**
+
* @brief Polling for transfer complete or CLUT loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
@@ -988,25 +1238,26 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+ uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
/* Polling for DMA2D transfer */
- if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
+ if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
{
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
@@ -1024,7 +1275,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1041,26 +1292,27 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
}
}
/* Polling for CLUT loading (foreground or background) */
- if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
- ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
+ layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
+ layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
+ if (layer_start != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
+ while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
- if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
+ if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
{
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
}
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
@@ -1078,7 +1330,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
@@ -1118,9 +1370,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
/* Transfer Error Interrupt management ***************************************/
- if ((isrflags & DMA2D_FLAG_TE) != RESET)
+ if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
- if ((crflags & DMA2D_IT_TE) != RESET)
+ if ((crflags & DMA2D_IT_TE) != 0U)
{
/* Disable the transfer Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
@@ -1145,9 +1397,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* Configuration Error Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_CE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
- if ((crflags & DMA2D_IT_CE) != RESET)
+ if ((crflags & DMA2D_IT_CE) != 0U)
{
/* Disable the Configuration Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
@@ -1172,9 +1424,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* CLUT access Error Interrupt management ***********************************/
- if ((isrflags & DMA2D_FLAG_CAE) != RESET)
+ if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
- if ((crflags & DMA2D_IT_CAE) != RESET)
+ if ((crflags & DMA2D_IT_CAE) != 0U)
{
/* Disable the CLUT access error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
@@ -1199,9 +1451,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* Transfer watermark Interrupt management **********************************/
- if ((isrflags & DMA2D_FLAG_TW) != RESET)
+ if ((isrflags & DMA2D_FLAG_TW) != 0U)
{
- if ((crflags & DMA2D_IT_TW) != RESET)
+ if ((crflags & DMA2D_IT_TW) != 0U)
{
/* Disable the transfer watermark interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
@@ -1210,13 +1462,18 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
/* Transfer watermark Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->LineEventCallback(hdma2d);
+#else
HAL_DMA2D_LineEventCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
+
}
}
/* Transfer Complete Interrupt management ************************************/
- if ((isrflags & DMA2D_FLAG_TC) != RESET)
+ if ((isrflags & DMA2D_FLAG_TC) != 0U)
{
- if ((crflags & DMA2D_IT_TC) != RESET)
+ if ((crflags & DMA2D_IT_TC) != 0U)
{
/* Disable the transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
@@ -1241,9 +1498,9 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
}
}
/* CLUT Transfer Complete Interrupt management ******************************/
- if ((isrflags & DMA2D_FLAG_CTC) != RESET)
+ if ((isrflags & DMA2D_FLAG_CTC) != 0U)
{
- if ((crflags & DMA2D_IT_CTC) != RESET)
+ if ((crflags & DMA2D_IT_CTC) != 0U)
{
/* Disable the CLUT transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
@@ -1261,9 +1518,14 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
__HAL_UNLOCK(hdma2d);
/* CLUT Transfer complete Callback */
+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
+ hdma2d->CLUTLoadingCpltCallback(hdma2d);
+#else
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
+
}
/**
@@ -1316,34 +1578,35 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
(+) Configure the dead time value.
(+) Enable or disable the dead time value functionality.
+
@endverbatim
* @{
*/
/**
* @brief Configure the DMA2D Layer according to the specified
- * parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
+ * parameters in the DMA2D_HandleTypeDef.
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
- DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
- uint32_t regValue = 0U;
+ DMA2D_LayerCfgTypeDef *pLayerCfg;
+ uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
- assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
+ assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
{
- assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
+ assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
if(hdma2d->Init.Mode != DMA2D_M2M)
{
- assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
+ assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
}
@@ -1353,23 +1616,27 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
- /* DMA2D BGPFCR register configuration -----------------------------------*/
- /* Prepare the value to be written to the BGPFCCR register */
+ pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
+
+ /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
+ regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
+
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
+ regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
}
else
{
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
}
/* Configure the background DMA2D layer */
- if(LayerIdx == 0)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write DMA2D BGPFCCR register */
- MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
@@ -1383,8 +1650,10 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
/* Configure the foreground DMA2D layer */
else
{
+
+
/* Write DMA2D FGPFCCR register */
- MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
+ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
@@ -1412,7 +1681,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
- * 0(background) / 1(foreground)
+ * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -1429,14 +1698,14 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
- if(LayerIdx == 0U)
+ if(LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
}
/* Configure the CLUT of the foreground DMA2D layer */
else
@@ -1446,10 +1715,10 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
- /* Set the DMA2D state to Ready */
+ /* Set the DMA2D state to Ready*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
@@ -1458,6 +1727,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf
return HAL_OK;
}
+
/**
* @brief Configure the line watermark.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
@@ -1491,7 +1761,7 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32
/* Enable the Line interrupt */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
- /* Initialize the DMA2D state */
+ /* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
@@ -1563,7 +1833,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Set DMA2D_AMTCR DT field */
- MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
+ MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1577,6 +1847,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
* @}
*/
+
/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @brief Peripheral State functions
*
@@ -1585,7 +1856,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection provides functions allowing to :
+ This subsection provides functions allowing to:
(+) Get the DMA2D state
(+) Get the DMA2D error code
@@ -1623,6 +1894,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
* @}
*/
+
/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
@@ -1639,14 +1911,14 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
- uint32_t tmp = 0U;
- uint32_t tmp1 = 0U;
- uint32_t tmp2 = 0U;
- uint32_t tmp3 = 0U;
- uint32_t tmp4 = 0U;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
+ uint32_t tmp3;
+ uint32_t tmp4;
/* Configure DMA2D data size */
- MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
@@ -1672,7 +1944,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
{
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 10U);
- tmp4 = (tmp4 >> 3U);
+ tmp4 = (tmp4 >> 3U );
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
@@ -1680,7 +1952,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
tmp1 = (tmp1 >> 31U);
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 11U);
- tmp4 = (tmp4 >> 3U);
+ tmp4 = (tmp4 >> 3U );
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
@@ -1688,7 +1960,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
tmp1 = (tmp1 >> 28U);
tmp2 = (tmp2 >> 20U);
tmp3 = (tmp3 >> 12U);
- tmp4 = (tmp4 >> 4U);
+ tmp4 = (tmp4 >> 4U );
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
}
/* Write to DMA2D OCOLR register */
@@ -1704,8 +1976,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/**
* @}
*/
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#endif /* HAL_DMA2D_MODULE_ENABLED */
+
/**
* @}
*/
@@ -1713,5 +1984,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
/**
* @}
*/
+#endif /* DMA2D */
+#endif /* HAL_DMA2D_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma_ex.c
index 59ef36768eee24ad2c6737da24077b1a489fe069..7c822046db158d46c0bd827145520866cae15c7d 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dma_ex.c
@@ -25,29 +25,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dsi.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dsi.c
index ddbb0c52ebabbef6d33db9aa719e0ffe5aadf74e..be4da6d8d3afbc56d140c8b4a9eb936c82ee5ec4 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dsi.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_dsi.c
@@ -9,32 +9,120 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required
+ PLL parameters, number of lanes and TX Escape clock divider.
+ (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
+ command mode.
+ (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host.
+ (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
+ (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer().
+ (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop().
+ Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively
+ to write DSI short packets, long packets and to read DSI packets.
+
+ (#) The DSI Host Offers two Low power modes :
+ (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
+ It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData()
+ and @ref HAL_DSI_ExitULPMData()
+
+ (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
+ It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM()
+ and @ref HAL_DSI_ExitULPM()
+
+ (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor()
+ When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve
+ the error code by calling function @ref HAL_DSI_GetError()
+
+ (#) To control DSI state you can use the following function: HAL_DSI_GetState()
+
+ *** DSI HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DSI HAL driver.
+
+ (+) __HAL_DSI_ENABLE: Enable the DSI Host.
+ (+) __HAL_DSI_DISABLE: Disable the DSI Host.
+ (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
+ (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
+ (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
+ (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
+ (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
+ (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
+ (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
+ (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
+ (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
+ (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
+ (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
+
+
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_DSI_RegisterCallback() to register a callback.
+
+ Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TearingEffectCallback : DSI Tearing Effect Callback.
+ (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
+ (+) ErrorCallback : DSI Error Callback
+ (+) MspInitCallback : DSI MspInit.
+ (+) MspDeInitCallback : DSI MspDeInit.
+
+ By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit
+ or HAL_DSI_Init function.
+
+ When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ [..]
+ (@) You can refer to the DSI HAL driver header file for more useful macros
+
+ @endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -82,7 +170,14 @@
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
+static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
+ uint32_t Data1);
+
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2);
/* Private functions ---------------------------------------------------------*/
/**
@@ -106,7 +201,48 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
uint32_t Data1)
{
/* Update the DSI packet header with new information */
- DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
+ DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
+}
+
+/**
+ * @brief write short DCS or short Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI short packet data type.
+ * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
+ * @param Param1 DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
+ * generic command code.
+ * @param Param2 DSC parameter or second generic parameter.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
+ uint32_t ChannelID,
+ uint32_t Mode,
+ uint32_t Param1,
+ uint32_t Param2)
+{
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for Command FIFO Empty */
+ while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the packet to send a short DCS command with 0 or 1 parameter */
+ /* Update the DSI packet header with new information */
+ hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
+
+ return HAL_OK;
}
/* Exported functions --------------------------------------------------------*/
@@ -115,8 +251,8 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
*/
/** @defgroup DSI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -145,7 +281,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
uint32_t tempIDF;
/* Check the DSI handle allocation */
- if(hdsi == NULL)
+ if (hdsi == NULL)
{
return HAL_ERROR;
}
@@ -157,11 +293,28 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
- if(hdsi->State == HAL_DSI_STATE_RESET)
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ /* Reset the DSI callback to the legacy weak callbacks */
+ hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+ hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
+ hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hdsi->MspInitCallback == NULL)
+ {
+ hdsi->MspInitCallback = HAL_DSI_MspInit;
+ }
+ /* Initialize the low level hardware */
+ hdsi->MspInitCallback(hdsi);
+ }
+#else
+ if (hdsi->State == HAL_DSI_STATE_RESET)
{
/* Initialize the low level hardware */
HAL_DSI_MspInit(hdsi);
}
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
@@ -175,10 +328,10 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
tickstart = HAL_GetTick();
/* Wait until the regulator is ready */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -186,7 +339,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
/* Set the PLL division factors */
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
/* Enable the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
@@ -195,10 +348,10 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -227,7 +380,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
/* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
- unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
+ unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
/* Set the bit period in high-speed mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
@@ -259,7 +412,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
{
/* Check the DSI handle allocation */
- if(hdsi == NULL)
+ if (hdsi == NULL)
{
return HAL_ERROR;
}
@@ -282,8 +435,17 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
/* Disable the regulator */
__HAL_DSI_REG_DISABLE(hdsi);
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ if (hdsi->MspDeInitCallback == NULL)
+ {
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdsi->MspDeInitCallback(hdsi);
+#else
/* DeInit the low level hardware */
HAL_DSI_MspDeInit(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Initialise the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
@@ -316,61 +478,61 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A
/* Store active errors to the handle */
hdsi->ErrorMsk = ActiveErrors;
- if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
}
- if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
+ if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
@@ -388,7 +550,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A
* the configuration information for the DSI.
* @retval None
*/
-__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
+__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
@@ -403,7 +565,7 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
* the configuration information for the DSI.
* @retval None
*/
-__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
+__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
@@ -412,13 +574,196 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
*/
}
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DSI Callback
+ * To be used instead of the weak predefined callback
+ * @param hdsi dsi handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
+ pDSI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ if (hdsi->State == HAL_DSI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_TEARING_EFFECT_CB_ID :
+ hdsi->TearingEffectCallback = pCallback;
+ break;
+
+ case HAL_DSI_ENDOF_REFRESH_CB_ID :
+ hdsi->EndOfRefreshCallback = pCallback;
+ break;
+
+ case HAL_DSI_ERROR_CB_ID :
+ hdsi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a DSI Callback
+ * DSI callabck is redirected to the weak predefined callback
+ * @param hdsi dsi handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
+ * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
+ * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdsi);
+
+ if (hdsi->State == HAL_DSI_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_TEARING_EFFECT_CB_ID :
+ hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
+ break;
+
+ case HAL_DSI_ENDOF_REFRESH_CB_ID :
+ hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
+ break;
+
+ case HAL_DSI_ERROR_CB_ID :
+ hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdsi->State == HAL_DSI_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DSI_MSPINIT_CB_ID :
+ hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_DSI_MSPDEINIT_CB_ID :
+ hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdsi);
+
+ return status;
+}
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup DSI_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -440,94 +785,112 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
uint32_t ErrorStatus0, ErrorStatus1;
/* Tearing Effect Interrupt management ***************************************/
- if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
+ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
{
- if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
+ if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
{
/* Clear the Tearing Effect Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
/* Tearing Effect Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered Tearing Effect callback */
+ hdsi->TearingEffectCallback(hdsi);
+#else
+ /*Call legacy Tearing Effect callback*/
HAL_DSI_TearingEffectCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* End of Refresh Interrupt management ***************************************/
- if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
+ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
{
- if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
+ if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
{
/* Clear the End of Refresh Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
/* End of Refresh Callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered End of refresh callback */
+ hdsi->EndOfRefreshCallback(hdsi);
+#else
+ /*Call Legacy End of refresh callback */
HAL_DSI_EndOfRefreshCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* Error Interrupts management ***********************************************/
- if(hdsi->ErrorMsk != 0U)
+ if (hdsi->ErrorMsk != 0U)
{
ErrorStatus0 = hdsi->Instance->ISR[0U];
ErrorStatus0 &= hdsi->Instance->IER[0U];
ErrorStatus1 = hdsi->Instance->ISR[1U];
ErrorStatus1 &= hdsi->Instance->IER[1U];
- if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
+ if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
}
- if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
+ if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
}
- if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
}
- if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
}
- if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
}
- if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
}
- if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
}
- if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
}
- if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
}
- if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
+ if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
}
/* Check only selected errors */
- if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
+ if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
{
- /* DSI error interrupt user callback */
+ /* DSI error interrupt callback */
+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
+ /*Call registered Error callback */
+ hdsi->ErrorCallback(hdsi);
+#else
+ /*Call Legacy Error callback */
HAL_DSI_ErrorCallback(hdsi);
+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
}
@@ -582,8 +945,8 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
*/
/** @defgroup DSI_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -671,7 +1034,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
/* Check the LooselyPacked variant only in 18-bit mode */
- if(VidCfg->ColorCoding == DSI_RGB666)
+ if (VidCfg->ColorCoding == DSI_RGB666)
{
assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
}
@@ -710,10 +1073,10 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
- hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
+ hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
/* Enable/disable the loosely packed variant to 18-bit configuration */
- if(VidCfg->ColorCoding == DSI_RGB666)
+ if (VidCfg->ColorCoding == DSI_RGB666)
{
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
@@ -753,7 +1116,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp
/* Low power largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
- hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
+ hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
/* Low power VACT largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
@@ -836,7 +1199,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
- hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
+ hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
/* Configure the maximum allowed size for write memory command */
hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
@@ -844,7 +1207,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_
/* Configure the tearing effect source and polarity and select the refresh mode */
hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
- hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
+ hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
+ CmdCfg->VSyncPol);
/* Configure the tearing effect acknowledge request */
hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
@@ -891,29 +1255,29 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe
assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
/* Select High-speed or Low-power for command transmission */
- hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
- DSI_CMCR_GSW1TX |\
- DSI_CMCR_GSW2TX |\
- DSI_CMCR_GSR0TX |\
- DSI_CMCR_GSR1TX |\
- DSI_CMCR_GSR2TX |\
- DSI_CMCR_GLWTX |\
- DSI_CMCR_DSW0TX |\
- DSI_CMCR_DSW1TX |\
- DSI_CMCR_DSR0TX |\
- DSI_CMCR_DLWTX |\
+ hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
+ DSI_CMCR_GSW1TX | \
+ DSI_CMCR_GSW2TX | \
+ DSI_CMCR_GSR0TX | \
+ DSI_CMCR_GSR1TX | \
+ DSI_CMCR_GSR2TX | \
+ DSI_CMCR_GLWTX | \
+ DSI_CMCR_DSW0TX | \
+ DSI_CMCR_DSW1TX | \
+ DSI_CMCR_DSR0TX | \
+ DSI_CMCR_DLWTX | \
DSI_CMCR_MRDPS);
- hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
- LPCmd->LPGenShortWriteOneP |\
- LPCmd->LPGenShortWriteTwoP |\
- LPCmd->LPGenShortReadNoP |\
- LPCmd->LPGenShortReadOneP |\
- LPCmd->LPGenShortReadTwoP |\
- LPCmd->LPGenLongWrite |\
- LPCmd->LPDcsShortWriteNoP |\
- LPCmd->LPDcsShortWriteOneP |\
- LPCmd->LPDcsShortReadNoP |\
- LPCmd->LPDcsLongWrite |\
+ hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \
+ LPCmd->LPGenShortWriteOneP | \
+ LPCmd->LPGenShortWriteTwoP | \
+ LPCmd->LPGenShortReadNoP | \
+ LPCmd->LPGenShortReadOneP | \
+ LPCmd->LPGenShortReadTwoP | \
+ LPCmd->LPGenLongWrite | \
+ LPCmd->LPDcsShortWriteNoP | \
+ LPCmd->LPDcsShortWriteOneP | \
+ LPCmd->LPDcsShortReadNoP | \
+ LPCmd->LPDcsLongWrite | \
LPCmd->LPMaxReadPacket);
/* Configure the acknowledge request after each packet transmission */
@@ -966,7 +1330,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
/* Process locked */
__HAL_LOCK(hdsi);
- maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
+ maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
+ PhyTimers->ClockLaneHS2LPTime;
/* Clock lane timer configuration */
@@ -978,17 +1343,18 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
- */
+ */
hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
- hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
+ hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
/* Data lane timer configuration */
hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
- hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
+ hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
+ PhyTimers->DataLaneHS2LPTime) << 24U));
/* Configure the wait period to request HS transmission after a stop state */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
- hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
+ hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1011,11 +1377,11 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T
/* Set the timeout clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
- hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
+ hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
/* High-speed transmission timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
- hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
+ hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
/* Low-power reception timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
@@ -1188,41 +1554,19 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
uint32_t Param1,
uint32_t Param2)
{
- uint32_t tickstart;
-
- /* Process locked */
- __HAL_LOCK(hdsi);
-
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hdsi);
-
- return HAL_TIMEOUT;
- }
- }
+ /* Process locked */
+ __HAL_LOCK(hdsi);
- /* Configure the packet to send a short DCS command with 0 or 1 parameter */
- DSI_ConfigPacketHeader(hdsi->Instance,
- ChannelID,
- Mode,
- Param1,
- Param2);
+ status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
- return HAL_OK;
+ return status;
}
/**
@@ -1244,12 +1588,12 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t* ParametersTable)
+ uint8_t *ParametersTable)
{
uint32_t uicounter, nbBytes, count;
uint32_t tickstart;
uint32_t fifoword;
- uint8_t* pparams = ParametersTable;
+ uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1261,10 +1605,10 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
+ while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1277,22 +1621,22 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
fifoword = Param1;
nbBytes = (NbParams < 3U) ? NbParams : 3U;
- for(count = 0U; count < nbBytes; count++)
+ for (count = 0U; count < nbBytes; count++)
{
- fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count)));
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
}
hdsi->Instance->GPDR = fifoword;
uicounter = NbParams - nbBytes;
pparams += nbBytes;
/* Set the Next parameters on the write FIFO command*/
- while(uicounter != 0U)
+ while (uicounter != 0U)
{
nbBytes = (uicounter < 4U) ? uicounter : 4U;
fifoword = 0U;
- for(count = 0U; count < nbBytes; count++)
+ for (count = 0U; count < nbBytes; count++)
{
- fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count));
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
}
hdsi->Instance->GPDR = fifoword;
@@ -1304,8 +1648,8 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
DSI_ConfigPacketHeader(hdsi->Instance,
ChannelID,
Mode,
- ((NbParams+1U)&0x00FFU),
- (((NbParams+1U)&0xFF00U)>>8U));
+ ((NbParams + 1U) & 0x00FFU),
+ (((NbParams + 1U) & 0xFF00U) >> 8U));
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1328,15 +1672,18 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
*/
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
- uint8_t* Array,
+ uint8_t *Array,
uint32_t Size,
uint32_t Mode,
uint32_t DCSCmd,
- uint8_t* ParametersTable)
+ uint8_t *ParametersTable)
{
uint32_t tickstart;
- uint8_t* pdata = Array;
+ uint8_t *pdata = Array;
uint32_t datasize = Size;
+ uint32_t fifoword;
+ uint32_t nbbytes;
+ uint32_t count;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1344,10 +1691,11 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
/* Check the parameters */
assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
- if(datasize > 2U)
+ if (datasize > 2U)
{
/* set max return packet size */
- if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK)
+ if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
+ (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1384,49 +1732,24 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
/* Get tick */
tickstart = HAL_GetTick();
- /* Check that the payload read FIFO is not empty */
- while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
+ /* If DSI fifo is not empty, read requested bytes */
+ while (((int32_t)(datasize)) > 0)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hdsi);
+ fifoword = hdsi->Instance->GPDR;
+ nbbytes = (datasize < 4U) ? datasize : 4U;
- return HAL_TIMEOUT;
- }
- }
-
- /* Get the first byte */
- *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
- if (datasize > 4U)
- {
- datasize -= 4U;
- pdata += 4U;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
-
- return HAL_OK;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Get the remaining bytes if any */
- while(((int)(datasize)) > 0)
- {
- if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
- {
- *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
- datasize -= 4U;
- pdata += 4U;
+ for (count = 0U; count < nbbytes; count++)
+ {
+ *pdata = (uint8_t)(fifoword >> (8U * count));
+ pdata++;
+ datasize--;
+ }
}
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1462,12 +1785,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until the D-PHY active lanes enter into ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
+ while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1478,10 +1801,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1525,12 +1848,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+ while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1541,10 +1864,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1600,12 +1923,12 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1616,10 +1939,10 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1666,10 +1989,10 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1685,12 +2008,12 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
- if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1701,10 +2024,11 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
+ while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
+ DSI_PSR_UANC))
{
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
@@ -1760,7 +2084,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_
/* Configure pattern generator mode and orientation */
hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
- hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
+ hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
/* Enable pattern generator by setting PGE bit */
hdsi->Instance->VMCR |= DSI_VMCR_PGE;
@@ -1802,7 +2126,8 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
* @param Value Custom value of the slew-rate or delay
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
+ uint32_t Value)
{
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1811,73 +2136,73 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin
assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
assert_param(IS_DSI_LANE_GROUP(Lane));
- switch(CommDelay)
+ switch (CommDelay)
{
- case DSI_SLEW_RATE_HSTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Slew Rate Control on Clock Lane */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
- hdsi->Instance->WPCR[1U] |= Value<<16U;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* High-Speed Transmission Slew Rate Control on Data Lanes */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
- hdsi->Instance->WPCR[1U] |= Value<<18U;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
+ case DSI_SLEW_RATE_HSTX:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Slew Rate Control on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value << 16U;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Slew Rate Control on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value << 18U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
- return HAL_ERROR;
- }
- break;
- case DSI_SLEW_RATE_LPTX:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* Low-Power transmission Slew Rate Compensation on Clock Lane */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
- hdsi->Instance->WPCR[1U] |= Value<<6U;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* Low-Power transmission Slew Rate Compensation on Data Lanes */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
- hdsi->Instance->WPCR[1U] |= Value<<8U;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_SLEW_RATE_LPTX:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
+ hdsi->Instance->WPCR[1U] |= Value << 6U;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* Low-Power transmission Slew Rate Compensation on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
+ hdsi->Instance->WPCR[1U] |= Value << 8U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
- return HAL_ERROR;
- }
- break;
- case DSI_HS_DELAY:
- if(Lane == DSI_CLOCK_LANE)
- {
- /* High-Speed Transmission Delay on Clock Lane */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
- hdsi->Instance->WPCR[1U] |= Value;
- }
- else if(Lane == DSI_DATA_LANES)
- {
- /* High-Speed Transmission Delay on Data Lanes */
- hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
- hdsi->Instance->WPCR[1U] |= Value<<2U;
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_HS_DELAY:
+ if (Lane == DSI_CLOCK_LANE)
+ {
+ /* High-Speed Transmission Delay on Clock Lane */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
+ hdsi->Instance->WPCR[1U] |= Value;
+ }
+ else if (Lane == DSI_DATA_LANES)
+ {
+ /* High-Speed Transmission Delay on Data Lanes */
+ hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
+ hdsi->Instance->WPCR[1U] |= Value << 2U;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
- return HAL_ERROR;
- }
- break;
- default:
- break;
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -1900,7 +2225,7 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t
/* Low-Power RX low-pass Filtering Tuning */
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
- hdsi->Instance->WPCR[1U] |= Frequency<<25U;
+ hdsi->Instance->WPCR[1U] |= Frequency << 25U;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
@@ -1945,7 +2270,8 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
* @param State ENABLE or DISABLE
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
+ FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1955,64 +2281,64 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint
assert_param(IS_DSI_LANE(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
- switch(CustomLane)
+ switch (CustomLane)
{
- case DSI_SWAP_LANE_PINS:
- if(Lane == DSI_CLK_LANE)
- {
- /* Swap pins on clock lane */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Swap pins on data lane 0 */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
- }
- else if(Lane == DSI_DATA_LANE1)
- {
- /* Swap pins on data lane 1 */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
+ case DSI_SWAP_LANE_PINS:
+ if (Lane == DSI_CLK_LANE)
+ {
+ /* Swap pins on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
+ }
+ else if (Lane == DSI_DATA_LANE0)
+ {
+ /* Swap pins on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
+ }
+ else if (Lane == DSI_DATA_LANE1)
+ {
+ /* Swap pins on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
- return HAL_ERROR;
- }
- break;
- case DSI_INVERT_HS_SIGNAL:
- if(Lane == DSI_CLK_LANE)
- {
- /* Invert HS signal on clock lane */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
- }
- else if(Lane == DSI_DATA_LANE0)
- {
- /* Invert HS signal on data lane 0 */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
- }
- else if(Lane == DSI_DATA_LANE1)
- {
- /* Invert HS signal on data lane 1 */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
- }
- else
- {
- /* Process unlocked */
- __HAL_UNLOCK(hdsi);
+ return HAL_ERROR;
+ }
+ break;
+ case DSI_INVERT_HS_SIGNAL:
+ if (Lane == DSI_CLK_LANE)
+ {
+ /* Invert HS signal on clock lane */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
+ }
+ else if (Lane == DSI_DATA_LANE0)
+ {
+ /* Invert HS signal on data lane 0 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
+ }
+ else if (Lane == DSI_DATA_LANE1)
+ {
+ /* Invert HS signal on data lane 1 */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
- return HAL_ERROR;
- }
- break;
- default:
- break;
+ return HAL_ERROR;
+ }
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -2040,127 +2366,127 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing
assert_param(IS_DSI_PHY_TIMING(Timing));
assert_param(IS_FUNCTIONAL_STATE(State));
- switch(Timing)
+ switch (Timing)
{
- case DSI_TCLK_POST:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
+ case DSI_TCLK_POST:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
- hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
+ hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
+ }
- break;
- case DSI_TLPX_CLK:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
+ break;
+ case DSI_TLPX_CLK:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
- hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
+ hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
+ }
- break;
- case DSI_THS_EXIT:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
+ break;
+ case DSI_THS_EXIT:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
- hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
+ hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
+ }
- break;
- case DSI_TLPX_DATA:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
+ break;
+ case DSI_TLPX_DATA:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
- hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
+ hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
+ }
- break;
- case DSI_THS_ZERO:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
+ break;
+ case DSI_THS_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
- hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
+ hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
+ }
- break;
- case DSI_THS_TRAIL:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
+ break;
+ case DSI_THS_TRAIL:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
- hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
+ hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
+ }
- break;
- case DSI_THS_PREPARE:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
+ break;
+ case DSI_THS_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
- hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
+ hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
+ }
- break;
- case DSI_TCLK_ZERO:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
+ break;
+ case DSI_TCLK_ZERO:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
- hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
+ hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
+ }
- break;
- case DSI_TCLK_PREPARE:
- /* Enable/Disable custom timing setting */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
- hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
+ break;
+ case DSI_TCLK_PREPARE:
+ /* Enable/Disable custom timing setting */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
+ hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
- if(State != DISABLE)
- {
- /* Set custom value */
- hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
- hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
- }
+ if (State != DISABLE)
+ {
+ /* Set custom value */
+ hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
+ hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
+ }
- break;
- default:
- break;
+ break;
+ default:
+ break;
}
/* Process unlocked */
@@ -2187,13 +2513,13 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane
assert_param(IS_DSI_LANE_GROUP(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
- if(Lane == DSI_CLOCK_LANE)
+ if (Lane == DSI_CLOCK_LANE)
{
/* Force/Unforce the Clock Lane in TX Stop Mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
}
- else if(Lane == DSI_DATA_LANES)
+ else if (Lane == DSI_DATA_LANES)
{
/* Force/Unforce the Data Lanes in TX Stop Mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
@@ -2318,8 +2644,8 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
*/
/** @defgroup DSI_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
index 7bff74797d944043866406eb37ad378ff6ef7e5d..2b6567b1a4f3d6c84f889b67270edd4227dee190 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_eth.c
@@ -64,34 +64,66 @@
-@- The PTP protocol and the DMA descriptors ring mode are not supported
in this driver
+*** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+ or HAL_ETH_Init function.
+
+ When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -143,6 +175,9 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
static void ETH_Delay(uint32_t mdelay);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
@@ -198,8 +233,20 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ ETH_InitCallbacksToDefault(heth);
+
+ if(heth->MspInitCallback == NULL)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ }
+ heth->MspInitCallback(heth);
+
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Enable SYSCFG Clock */
@@ -452,8 +499,17 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ if(heth->MspDeInitCallback == NULL)
+ {
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ }
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+ heth->MspDeInitCallback(heth);
+#else
/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspDeInit(heth);
+#endif
/* Set ETH HAL state to Disabled */
heth->State= HAL_ETH_STATE_RESET;
@@ -632,6 +688,173 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
*/
}
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ETH Callback
+ * To be used instead of the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->State == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an ETH Callback
+ * ETH callabck is redirected to the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->State == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->State == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -949,8 +1172,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Receive complete callback*/
+ heth->RxCpltCallback(heth);
+#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
@@ -965,8 +1193,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call resgistered Transfer complete callback*/
+ heth->TxCpltCallback(heth);
+#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
@@ -984,8 +1217,12 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
{
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ heth->DMAErrorCallback(heth);
+#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
@@ -2044,6 +2281,16 @@ static void ETH_Delay(uint32_t mdelay)
while (Delay --);
}
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+ /* Init the ETH Callback settings */
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_exti.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_exti.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8699066debabe68bd9b2f07018366766f2837cb
--- /dev/null
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_exti.c
@@ -0,0 +1,440 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two different
+ interrupts pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ uint32_t regval;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~pExtiConfig->Line;
+ EXTI->EMR &= ~pExtiConfig->Line;
+
+ /* Select the Mode for the selected external interrupts */
+ regval = (uint32_t)EXTI_BASE;
+ regval += pExtiConfig->Mode;
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~pExtiConfig->Line;
+ EXTI->FTSR &= ~pExtiConfig->Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= pExtiConfig->Line;
+ EXTI->FTSR |= pExtiConfig->Line;
+ }
+ else
+ {
+ regval = (uint32_t)EXTI_BASE;
+ regval += pExtiConfig->Trigger;
+ *(__IO uint32_t *) regval |= pExtiConfig->Line;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configuration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* Get EXTI mode to configiguration structure */
+ if ((EXTI->IMR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ }
+ else if ((EXTI->EMR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Mode = EXTI_MODE_EVENT;
+ }
+ else
+ {
+ /* No MODE selected */
+ pExtiConfig->Mode = 0x0Bu;
+ }
+
+ /* Get EXTI Trigger to configiguration structure */
+ if ((EXTI->RTSR & hexti->Line) == hexti->Line)
+ {
+ if ((EXTI->FTSR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING;
+ }
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+ }
+ else if ((EXTI->FTSR & hexti->Line) == hexti->Line)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_FALLING;
+ }
+ else
+ {
+ /* No Trigger selected */
+ pExtiConfig->Trigger = 0x00u;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* 1] Clear interrupt mode */
+ EXTI->IMR = (EXTI->IMR & ~hexti->Line);
+
+ /* 2] Clear event mode */
+ EXTI->EMR = (EXTI->EMR & ~hexti->Line);
+
+ /* 3] Clear triggers */
+ EXTI->RTSR = (EXTI->RTSR & ~hexti->Line);
+ EXTI->FTSR = (EXTI->FTSR & ~hexti->Line);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Register callback for a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ if (EXTI->PR != 0x00u)
+ {
+ /* Clear pending bit */
+ EXTI->PR = hexti->Line;
+
+ /* Call callback */
+ if (hexti->RisingCallback != NULL)
+ {
+ hexti->RisingCallback();
+ }
+ }
+}
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* Get pending bit */
+ regaddr = &EXTI->PR;
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line));
+
+ return regval;
+}
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ EXTI->PR = hexti->Line;
+}
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ EXTI->SWIER = hexti->Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash.c
index 538e17e219b169bafa2351a6a0603a6d32e3bef4..92bb37424614aa3dea4dbbb5b0dc19fd7899bd35 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash.c
@@ -63,29 +63,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ex.c
index e709dd74d777a58d402c86310a4c1b66b934d300..edb8b150e82e28ae96d6e55676ba1fd6ce2ae6a1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ex.c
@@ -49,29 +49,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1294,13 +1278,13 @@ static uint8_t FLASH_OB_GetRDP(void)
{
readstatus = OB_RDP_LEVEL_2;
}
- else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
+ else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))
{
- readstatus = OB_RDP_LEVEL_1;
+ readstatus = OB_RDP_LEVEL_0;
}
else
{
- readstatus = OB_RDP_LEVEL_0;
+ readstatus = OB_RDP_LEVEL_1;
}
return readstatus;
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ramfunc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ramfunc.c
index 5a495cc85b99772ef8d87c68b1a5f3e5a15bdd95..2931b20f766f5e6b78dfaf4a78dc385db268af27 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ramfunc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_flash_ramfunc.c
@@ -34,29 +34,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c.c
index 6e7a5c85ce3ec3a39182720f3016a9fb4d4fc49f..f60c0df235c32b8ddc404c34df75a2ebcabd7e21 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c.c
@@ -19,7 +19,7 @@
(#) Declare a FMPI2C_HandleTypeDef handle structure, for example:
FMPI2C_HandleTypeDef hfmpi2c;
- (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API:
+ (#)Initialize the FMPI2C low level resources by implementing the @ref HAL_FMPI2C_MspInit() API:
(##) Enable the FMPI2Cx interface clock
(##) FMPI2C pins configuration
(+++) Enable the clock for the FMPI2C GPIOs
@@ -39,54 +39,54 @@
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
- (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API.
+ (#) Initialize the FMPI2C registers by calling the @ref HAL_FMPI2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_FMPI2C_MspInit(&hfmpi2c) API.
- (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_FMPI2C_IsDeviceReady()
(#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_FMPI2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_FMPI2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
- (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
- (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback()
+ (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback()
+ (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
- *** Interrupt mode IO sequential operation ***
- ==============================================
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
@@ -98,7 +98,8 @@
and data to transfer without a final stop condition
(++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like HAL_FMPI2C_Master_Sequential_Transmit_IT() then HAL_FMPI2C_Master_Sequential_Transmit_IT())
+ several times (like @ref HAL_FMPI2C_Master_Seq_Transmit_IT() then @ref HAL_FMPI2C_Master_Seq_Transmit_IT()
+ or @ref HAL_FMPI2C_Master_Seq_Transmit_DMA() then @ref HAL_FMPI2C_Master_Seq_Transmit_DMA())
(++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
@@ -107,94 +108,104 @@
if no direction change and with a final stop condition in both cases
(++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME).
- Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Sequential_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
- or HAL_FMPI2C_Master_Sequential_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
+ or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
+ or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
+ or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME).
Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
- without stopping the communication and so generate a restart condition.
+ without stopping the communication and so generate a restart condition.
+ (++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME)
+ or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME)
+ or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME)
+ or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME).
+ Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential FMPI2C interfaces are listed below:
- (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
- (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
- (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
- (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
+ (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Transmit_IT()
+ or using @ref HAL_FMPI2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback()
+ (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Receive_IT()
+ or using @ref HAL_FMPI2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT()
+ (+++) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave FMPI2C mode using @ref HAL_FMPI2C_EnableListen_IT() @ref HAL_FMPI2C_DisableListen_IT()
+ (+++) When address slave FMPI2C match, @ref HAL_FMPI2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback()
- (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
- (++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
- (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ (+++) At Listen mode end @ref HAL_FMPI2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ListenCpltCallback()
+ (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Transmit_IT()
+ or using @ref HAL_FMPI2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Receive_IT()
+ or using @ref HAL_FMPI2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback()
+ (++) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_FMPI2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
+ @ref HAL_FMPI2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_FMPI2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+ @ref HAL_FMPI2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_FMPI2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback()
+ @ref HAL_FMPI2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_FMPI2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback()
+ @ref HAL_FMPI2C_Master_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_FMPI2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback()
+ @ref HAL_FMPI2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_FMPI2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
- (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
- (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
+ @ref HAL_FMPI2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback()
+ (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback()
+ (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_FMPI2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback()
+ @ref HAL_FMPI2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_FMPI2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
+ @ref HAL_FMPI2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback()
*** FMPI2C HAL driver macros list ***
@@ -202,13 +213,78 @@
[..]
Below the list of most used macros in FMPI2C HAL driver.
- (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
- (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
- (+) __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode
- (+) __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not
- (+) __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag
- (+) __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt
- (+) __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt
+ (+) @ref __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral
+ (+) @ref __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral
+ (+) @ref __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode
+ (+) @ref __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not
+ (+) @ref __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag
+ (+) @ref __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt
+ (+) @ref __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_FMPI2C_RegisterCallback() or @ref HAL_FMPI2C_RegisterAddrCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_FMPI2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_RegisterAddrCallback().
+
+ Use function @ref HAL_FMPI2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_UnRegisterAddrCallback().
+
+ By default, after the @ref HAL_FMPI2C_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_FMPI2C_MasterTxCpltCallback(), @ref HAL_FMPI2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_FMPI2C_RegisterCallback() before calling @ref HAL_FMPI2C_DeInit()
+ or @ref HAL_FMPI2C_Init() function.
+
+ When the compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the FMPI2C HAL driver header file for more useful macros
@@ -217,29 +293,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -257,9 +317,7 @@
*/
#ifdef HAL_FMPI2C_MODULE_ENABLED
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(FMPI2C_CR1_PE)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -267,7 +325,7 @@
/** @defgroup FMPI2C_Private_Define FMPI2C Private Define
* @{
*/
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< FMPI2C TIMING clear register Mask */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< FMPI2C TIMING clear register Mask */
#define FMPI2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
#define FMPI2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
#define FMPI2C_TIMEOUT_DIR (25U) /*!< 25 ms */
@@ -283,14 +341,14 @@
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
+#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */
-#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
@@ -309,10 +367,6 @@
*/
/* Private macro -------------------------------------------------------------*/
-#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_FMPI2C_STATE_BUSY_TX) ? \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
- ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -329,8 +383,8 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
-static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
-static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITSlaveSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c);
static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
@@ -354,14 +408,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef
static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
-/* Private functions to flush TXDR register */
+/* Private function to flush TXDR register */
static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
-/* Private functions to handle start, restart or stop a transfer */
-static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/* Private function to handle start, restart or stop a transfer */
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c);
/**
* @}
*/
@@ -433,8 +490,30 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
/* Allocate lock resource and initialize it */
hfmpi2c->Lock = HAL_UNLOCKED;
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ /* Init the FMPI2C Callback settings */
+ hfmpi2c->MasterTxCpltCallback = HAL_FMPI2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hfmpi2c->MasterRxCpltCallback = HAL_FMPI2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hfmpi2c->SlaveTxCpltCallback = HAL_FMPI2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hfmpi2c->SlaveRxCpltCallback = HAL_FMPI2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hfmpi2c->ListenCpltCallback = HAL_FMPI2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hfmpi2c->MemTxCpltCallback = HAL_FMPI2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hfmpi2c->MemRxCpltCallback = HAL_FMPI2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hfmpi2c->ErrorCallback = HAL_FMPI2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfmpi2c->AbortCpltCallback = HAL_FMPI2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hfmpi2c->AddrCallback = HAL_FMPI2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hfmpi2c->MspInitCallback == NULL)
+ {
+ hfmpi2c->MspInitCallback = HAL_FMPI2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hfmpi2c->MspInitCallback(hfmpi2c);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_FMPI2C_MspInit(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY;
@@ -513,8 +592,18 @@ HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
/* Disable the FMPI2C Peripheral Clock */
__HAL_FMPI2C_DISABLE(hfmpi2c);
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ if (hfmpi2c->MspDeInitCallback == NULL)
+ {
+ hfmpi2c->MspDeInitCallback = HAL_FMPI2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hfmpi2c->MspDeInitCallback(hfmpi2c);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_FMPI2C_MspDeInit(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
hfmpi2c->State = HAL_FMPI2C_STATE_RESET;
@@ -559,6 +648,328 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
*/
}
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User FMPI2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_FMPI2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_FMPI2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FMPI2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, pFMPI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID :
+ hfmpi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID :
+ hfmpi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID :
+ hfmpi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID :
+ hfmpi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_LISTEN_COMPLETE_CB_ID :
+ hfmpi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID :
+ hfmpi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID :
+ hfmpi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_ERROR_CB_ID :
+ hfmpi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_ABORT_CB_ID :
+ hfmpi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MSPINIT_CB_ID :
+ hfmpi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MSPDEINIT_CB_ID :
+ hfmpi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMPI2C_STATE_RESET == hfmpi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPI2C_MSPINIT_CB_ID :
+ hfmpi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_FMPI2C_MSPDEINIT_CB_ID :
+ hfmpi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an FMPI2C Callback
+ * FMPI2C callback is redirected to the weak predefined callback
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_FMPI2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_FMPI2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_FMPI2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_FMPI2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID :
+ hfmpi2c->MasterTxCpltCallback = HAL_FMPI2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID :
+ hfmpi2c->MasterRxCpltCallback = HAL_FMPI2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID :
+ hfmpi2c->SlaveTxCpltCallback = HAL_FMPI2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID :
+ hfmpi2c->SlaveRxCpltCallback = HAL_FMPI2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_LISTEN_COMPLETE_CB_ID :
+ hfmpi2c->ListenCpltCallback = HAL_FMPI2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID :
+ hfmpi2c->MemTxCpltCallback = HAL_FMPI2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID :
+ hfmpi2c->MemRxCpltCallback = HAL_FMPI2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_FMPI2C_ERROR_CB_ID :
+ hfmpi2c->ErrorCallback = HAL_FMPI2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_FMPI2C_ABORT_CB_ID :
+ hfmpi2c->AbortCpltCallback = HAL_FMPI2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_FMPI2C_MSPINIT_CB_ID :
+ hfmpi2c->MspInitCallback = HAL_FMPI2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_FMPI2C_MSPDEINIT_CB_ID :
+ hfmpi2c->MspDeInitCallback = HAL_FMPI2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_FMPI2C_STATE_RESET == hfmpi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_FMPI2C_MSPINIT_CB_ID :
+ hfmpi2c->MspInitCallback = HAL_FMPI2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_FMPI2C_MSPDEINIT_CB_ID :
+ hfmpi2c->MspDeInitCallback = HAL_FMPI2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match FMPI2C Callback
+ * To be used instead of the weak HAL_FMPI2C_AddrCallback() predefined callback
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
+ {
+ hfmpi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match FMPI2C Callback
+ * Info Ready FMPI2C Callback is redirected to the weak HAL_FMPI2C_AddrCallback() predefined callback
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hfmpi2c);
+
+ if (HAL_FMPI2C_STATE_READY == hfmpi2c->State)
+ {
+ hfmpi2c->AddrCallback = HAL_FMPI2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hfmpi2c);
+ return status;
+}
+
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -598,12 +1009,15 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
(++) HAL_FMPI2C_Master_Receive_IT()
(++) HAL_FMPI2C_Slave_Transmit_IT()
(++) HAL_FMPI2C_Slave_Receive_IT()
- (++) HAL_FMPI2C_Master_Sequential_Transmit_IT()
- (++) HAL_FMPI2C_Master_Sequential_Receive_IT()
- (++) HAL_FMPI2C_Slave_Sequential_Transmit_IT()
- (++) HAL_FMPI2C_Slave_Sequential_Receive_IT()
(++) HAL_FMPI2C_Mem_Write_IT()
(++) HAL_FMPI2C_Mem_Read_IT()
+ (++) HAL_FMPI2C_Master_Seq_Transmit_IT()
+ (++) HAL_FMPI2C_Master_Seq_Receive_IT()
+ (++) HAL_FMPI2C_Slave_Seq_Transmit_IT()
+ (++) HAL_FMPI2C_Slave_Seq_Receive_IT()
+ (++) HAL_FMPI2C_EnableListen_IT()
+ (++) HAL_FMPI2C_DisableListen_IT()
+ (++) HAL_FMPI2C_Master_Abort_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_FMPI2C_Master_Transmit_DMA()
@@ -612,15 +1026,22 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
(++) HAL_FMPI2C_Slave_Receive_DMA()
(++) HAL_FMPI2C_Mem_Write_DMA()
(++) HAL_FMPI2C_Mem_Read_DMA()
+ (++) HAL_FMPI2C_Master_Seq_Transmit_DMA()
+ (++) HAL_FMPI2C_Master_Seq_Receive_DMA()
+ (++) HAL_FMPI2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_FMPI2C_Slave_Seq_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_FMPI2C_MemTxCpltCallback()
- (++) HAL_FMPI2C_MemRxCpltCallback()
(++) HAL_FMPI2C_MasterTxCpltCallback()
(++) HAL_FMPI2C_MasterRxCpltCallback()
(++) HAL_FMPI2C_SlaveTxCpltCallback()
(++) HAL_FMPI2C_SlaveRxCpltCallback()
+ (++) HAL_FMPI2C_MemTxCpltCallback()
+ (++) HAL_FMPI2C_MemRxCpltCallback()
+ (++) HAL_FMPI2C_AddrCallback()
+ (++) HAL_FMPI2C_ListenCpltCallback()
(++) HAL_FMPI2C_ErrorCallback()
+ (++) HAL_FMPI2C_AbortCpltCallback()
@endverbatim
* @{
@@ -630,7 +1051,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -639,7 +1060,7 @@ __weak void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c)
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -651,7 +1072,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
@@ -668,12 +1089,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
}
while (hfmpi2c->XferCount > 0U)
@@ -681,37 +1102,34 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
- if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
}
@@ -720,14 +1138,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
/* Wait until STOPF flag is set */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -754,7 +1165,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
* @brief Receives in master mode an amount of data in blocking mode.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -763,7 +1174,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -775,7 +1186,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
@@ -792,12 +1203,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
}
while (hfmpi2c->XferCount > 0U)
@@ -805,38 +1216,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* Wait until RXNE flag is set */
if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
- if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
}
@@ -845,14 +1253,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* Wait until STOPF flag is set */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -886,12 +1287,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -917,7 +1319,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -931,7 +1333,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -943,7 +1345,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hfmpi2c->XferCount > 0U)
@@ -953,19 +1355,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
}
@@ -983,7 +1381,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
}
else
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -995,7 +1393,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1026,12 +1424,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1057,7 +1456,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -1068,7 +1467,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hfmpi2c->XferCount > 0U)
@@ -1083,22 +1482,23 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
}
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
}
@@ -1107,15 +1507,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
-
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1126,7 +1518,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1150,7 +1542,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1158,7 +1550,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1193,7 +1585,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1219,7 +1611,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1227,7 +1619,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1262,7 +1654,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1386,7 +1778,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1394,7 +1786,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1429,37 +1822,71 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
if (hfmpi2c->XferSize > 0U)
{
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1468,7 +1895,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1494,7 +1921,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1502,7 +1929,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c,
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -1537,37 +1965,71 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
if (hfmpi2c->XferSize > 0U)
{
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1576,7 +2038,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1589,6 +2051,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
/* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
}
+
return HAL_OK;
}
else
@@ -1607,10 +2070,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1627,33 +2093,67 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1673,10 +2173,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1693,33 +2196,67 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1732,7 +2269,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -1743,7 +2280,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -1752,6 +2289,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1763,7 +2301,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
@@ -1778,30 +2316,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
do
@@ -1809,38 +2338,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
- if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
@@ -1851,14 +2377,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -1885,7 +2404,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -1896,7 +2415,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -1905,6 +2424,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1916,7 +2436,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
@@ -1931,18 +2451,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
/* Send Slave Address */
@@ -1950,12 +2461,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
}
do
@@ -1963,31 +2474,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
/* Wait until RXNE flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
- if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
}
@@ -1997,14 +2512,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2030,7 +2538,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2040,8 +2548,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2050,6 +2558,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2088,22 +2597,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2129,7 +2629,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2139,8 +2639,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2149,6 +2649,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2187,22 +2688,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2227,7 +2719,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2237,8 +2729,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2247,6 +2740,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2285,51 +2779,77 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Update XferCount value */
- hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2343,7 +2863,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -2353,8 +2873,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16
*/
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
@@ -2363,6 +2884,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2401,50 +2923,75 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
/* Send Slave Address and Memory Address */
if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
}
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hfmpi2c->XferCount -= hfmpi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2459,7 +3006,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
* @note This function is used with Memory devices
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
@@ -2467,9 +3014,12 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_
*/
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+
+ __IO uint32_t FMPI2C_Trials = 0UL;
- __IO uint32_t FMPI2C_Trials = 0U;
+ FlagStatus tmp1;
+ FlagStatus tmp2;
if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
@@ -2492,19 +3042,31 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
+
+ tmp1 = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ tmp2 = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- /* Device is ready */
+ /* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
+
+ tmp1 = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+ tmp2 = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
@@ -2513,7 +3075,7 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2532,7 +3094,7 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear NACK Flag */
@@ -2543,7 +3105,7 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
}
/* Check if the maximum allowed number of trials has been reached */
- if (FMPI2C_Trials++ == Trials)
+ if (FMPI2C_Trials == Trials)
{
/* Generate Stop */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
@@ -2551,21 +3113,28 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* Wait until STOPF flag is reset */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
+
+ /* Increment Trials */
+ FMPI2C_Trials++;
}
while (FMPI2C_Trials < Trials);
+ /* Update FMPI2C state */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
else
{
@@ -2578,16 +3147,16 @@ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
/* Check the parameters */
@@ -2608,7 +3177,92 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
- /* If size > MAX_NBYTE_SIZE, use reload mode */
+ /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = hfmpi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPI2C_ConvertOtherXferOptions(hfmpi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hfmpi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to write */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode with DMA.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
@@ -2620,107 +3274,642 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef
xfermode = hfmpi2c->XferOptions;
}
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX)
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPI2C_ConvertOtherXferOptions(hfmpi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hfmpi2c->XferOptions;
+ }
+ }
+
+ if (hfmpi2c->XferSize > 0U)
+ {
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to write */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = hfmpi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPI2C_ConvertOtherXferOptions(hfmpi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hfmpi2c->XferOptions;
+ }
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master FMPI2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
+
+ /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hfmpi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = FMPI2C_RELOAD_MODE;
+ }
+ else
+ {
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ xfermode = hfmpi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = FMPI2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ FMPI2C_ConvertOtherXferOptions(hfmpi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hfmpi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hfmpi2c->XferOptions;
+ }
+ }
+
+ if (hfmpi2c->XferSize > 0U)
+ {
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to read */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential transmit in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
+ * the configuration information for the specified FMPI2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) == (uint32_t)HAL_FMPI2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hfmpi2c);
+
+ /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ /* Abort DMA Xfer if any */
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ }
+ }
+ }
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hfmpi2c->pBuffPtr = pData;
+ hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
+ hfmpi2c->XferOptions = XferOptions;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
- xferrequest = FMPI2C_NO_STARTSTOP;
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
}
- /* Send Slave Address and set NBYTES to write */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
-
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
}
/**
- * @brief Sequential receive in master FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential transmit in slave/device FMPI2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
- uint32_t xferrequest = FMPI2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) == (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX;
- hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
+
+ /* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ /* Enable Address Acknowledge */
+ hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
+
/* Prepare transfer parameters */
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
+ hfmpi2c->XferSize = hfmpi2c->XferCount;
hfmpi2c->XferOptions = XferOptions;
- hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
- /* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->hdmatx != NULL)
{
- hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = FMPI2C_RELOAD_MODE;
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
}
else
{
- hfmpi2c->XferSize = hfmpi2c->XferCount;
- xfermode = hfmpi2c->XferOptions;
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
}
- /* If transfer direction not change, do not generate Restart Condition */
- /* Mean Previous state is same as current state */
- if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
+ if (dmaxferstatus == HAL_OK)
{
- xferrequest = FMPI2C_NO_STARTSTOP;
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Reset XferSize */
+ hfmpi2c->XferSize = 0;
}
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
- /* Send Slave Address and set NBYTES to read */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_ERROR;
}
}
/**
- * @brief Sequential transmit in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential receive in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
@@ -2729,33 +3918,54 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) == (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT);
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT);
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
- /* and then toggle the HAL slave RX state to TX state */
- if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ }
+ }
+ }
}
- hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
+ hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -2769,7 +3979,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
- if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -2783,7 +3993,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT);
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
return HAL_OK;
}
@@ -2794,7 +4004,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
}
/**
- * @brief Sequential receive in slave/device FMPI2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential receive in slave/device FMPI2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
@@ -2803,15 +4013,18 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) == (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2827,6 +4040,52 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h
{
/* Disable associated Interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
+
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ {
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ {
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
}
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
@@ -2841,7 +4100,60 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h
hfmpi2c->XferCount = Size;
hfmpi2c->XferSize = hfmpi2c->XferCount;
hfmpi2c->XferOptions = XferOptions;
- hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
+ hfmpi2c->XferISR = FMPI2C_Slave_ISR_DMA;
+
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmarx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Reset XferSize */
+ hfmpi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update FMPI2C state */
+ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Update FMPI2C error code */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
{
@@ -2859,6 +4171,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *h
/* REnable ADDR interrupt */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT);
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+
return HAL_OK;
}
else
@@ -2926,7 +4241,7 @@ HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
* @brief Abort a master FMPI2C IT or DMA process communication with Interrupt.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
@@ -3003,9 +4318,10 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
{
uint32_t itflags = READ_REG(hfmpi2c->Instance->ISR);
uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
+ uint32_t tmperror;
/* FMPI2C Bus error interrupt occurred ------------------------------------*/
- if (((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
@@ -3014,7 +4330,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
}
/* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
@@ -3023,7 +4339,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
}
/* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if (((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
@@ -3031,10 +4347,13 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c)
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO);
}
+ /* Store current volatile hfmpi2c->ErrorCode, misra rule */
+ tmperror = hfmpi2c->ErrorCode;
+
/* Call the Error Callback in case of Error detected */
- if ((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE)
+ if ((tmperror & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE)
{
- FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+ FMPI2C_ITError(hfmpi2c, tmperror);
}
}
@@ -3276,12 +4595,13 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c)
*/
static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
+ uint16_t devaddress;
+ uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3294,41 +4614,52 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
- else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET))
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~FMPI2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
- else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
- hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
- else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
- if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U))
{
- devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+ devaddress = (uint16_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
- FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
}
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
{
- FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
}
else
{
- FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
}
@@ -3338,7 +4669,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
{
/* Call FMPI2C Master Sequential complete process */
- FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ FMPI2C_ITMasterSeqCplt(hfmpi2c);
}
else
{
@@ -3348,7 +4679,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
}
}
}
- else if (((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
if (hfmpi2c->XferCount == 0U)
{
@@ -3363,7 +4694,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
else
{
/* Call FMPI2C Master Sequential complete process */
- FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ FMPI2C_ITMasterSeqCplt(hfmpi2c);
}
}
}
@@ -3374,11 +4705,15 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
- if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
- FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
+ FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags);
}
/* Process Unlocked */
@@ -3397,10 +4732,13 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm
*/
static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hfmpi2c->XferOptions;
+ uint32_t tmpITFlags = ITFlags;
+
/* Process locked */
__HAL_LOCK(hfmpi2c);
- if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -3408,13 +4746,12 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
/* So clear Flag NACKF only */
if (hfmpi2c->XferCount == 0U)
{
- if (((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
- (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
{
/* Call FMPI2C Listen complete process */
- FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+ FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags);
}
- else if ((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+ else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3424,7 +4761,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
/* Last Byte is Transmitted */
/* Call FMPI2C Slave Sequential complete process */
- FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
}
else
{
@@ -3440,30 +4777,43 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+ }
}
}
- else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET))
{
if (hfmpi2c->XferCount > 0U)
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~FMPI2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
if ((hfmpi2c->XferCount == 0U) && \
- (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME))
+ (tmpoptions != FMPI2C_NO_OPTION_FRAME))
{
/* Call FMPI2C Slave Sequential complete process */
- FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
}
}
- else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_ADDR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET))
{
- FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
+ FMPI2C_ITAddrCplt(hfmpi2c, tmpITFlags);
}
- else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@@ -3472,26 +4822,34 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
if (hfmpi2c->XferCount > 0U)
{
/* Write data to TXDR */
- hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
+ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
+
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
}
else
{
- if ((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME))
+ if ((tmpoptions == FMPI2C_NEXT_FRAME) || (tmpoptions == FMPI2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call FMPI2C Slave Sequential complete process */
- FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if STOPF is set */
- if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Slave complete process */
- FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
+ FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags);
}
/* Process Unlocked */
@@ -3510,13 +4868,13 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp
*/
static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
- uint32_t xfermode = 0U;
+ uint16_t devaddress;
+ uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3532,7 +4890,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
- else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI);
@@ -3540,7 +4898,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
if (hfmpi2c->XferCount != 0U)
{
/* Recover Slave address */
- devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
+ devaddress = (uint16_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
/* Prepare the new XferSize to transfer */
if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
@@ -3551,11 +4909,18 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- xfermode = FMPI2C_AUTOEND_MODE;
+ if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+ {
+ xfermode = hfmpi2c->XferOptions;
+ }
+ else
+ {
+ xfermode = FMPI2C_AUTOEND_MODE;
+ }
}
/* Set the new XferSize in Nbytes register */
- FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
@@ -3563,25 +4928,64 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
/* Enable DMA Request */
if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Call FMPI2C Master Sequential complete process */
+ FMPI2C_ITMasterSeqCplt(hfmpi2c);
}
else
{
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET))
+ {
+ if (hfmpi2c->XferCount == 0U)
+ {
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hfmpi2c->XferOptions == FMPI2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call FMPI2C Master Sequential complete process */
+ FMPI2C_ITMasterSeqCplt(hfmpi2c);
+ }
}
}
else
{
- /* Wrong size Status regarding TCR flag event */
+ /* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
}
}
- else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3599,40 +5003,105 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf
*/
static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hfmpi2c->XferOptions;
+ uint32_t treatdmanack = 0U;
+
/* Process locked */
__HAL_LOCK(hfmpi2c);
- if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U)
+ if ((FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET) ||
+ (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET))
{
- /* Clear NACK Flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+ /* Split check of hdmarx, for MISRA compliance */
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ /* Split check of hdmatx, for MISRA compliance */
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ if (treatdmanack == 1U)
+ {
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call FMPI2C Listen complete process */
+ FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+ }
+ else if ((hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != FMPI2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Flush TX register */
+ FMPI2C_Flush_TXDR(hfmpi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+
+ if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
+ }
+ }
}
else
{
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
+ /* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
}
- else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET))
{
- /* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
+ FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
}
- else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Slave complete process */
FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3644,7 +5113,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
* @brief Master sends target device address followed by internal memory address for write request.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -3654,19 +5123,12 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3684,14 +5146,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3701,7 +5156,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
/* Wait until TCR flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3711,7 +5166,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
* @brief Master sends target device address followed by internal memory address for read request.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
@@ -3721,19 +5176,12 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3751,14 +5199,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
/* Wait until TXIS flag is set */
if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3768,7 +5209,7 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
/* Wait until TC flag is set */
if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3782,16 +5223,16 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c,
*/
static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
{
- uint8_t transferdirection = 0;
- uint16_t slaveaddrcode = 0;
- uint16_t ownadd1code = 0;
- uint16_t ownadd2code = 0;
+ uint8_t transferdirection;
+ uint16_t slaveaddrcode;
+ uint16_t ownadd1code;
+ uint16_t ownadd2code;
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
- if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) == (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
transferdirection = FMPI2C_GET_DIR(hfmpi2c);
slaveaddrcode = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
@@ -3817,7 +5258,11 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#else
HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
else
@@ -3831,7 +5276,11 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#else
HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
/* else 7 bits addressing mode is selected */
@@ -3844,7 +5293,11 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#else
HAL_FMPI2C_AddrCallback(hfmpi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
/* Else clear address flag only */
@@ -3863,7 +5316,7 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
* @param hfmpi2c FMPI2C handle.
* @retval None
*/
-static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c)
{
/* Reset FMPI2C handle mode */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -3883,7 +5336,11 @@ static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MasterTxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
/* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
else
@@ -3899,7 +5356,11 @@ static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MasterRxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
@@ -3908,7 +5369,7 @@ static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
* @param hfmpi2c FMPI2C handle.
* @retval None
*/
-static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
+static void FMPI2C_ITSlaveSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c)
{
/* Reset FMPI2C handle mode */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -3925,8 +5386,12 @@ static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->SlaveTxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
@@ -3941,8 +5406,16 @@ static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->SlaveRxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
@@ -3954,6 +5427,8 @@ static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c)
*/
static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
{
+ uint32_t tmperror;
+
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
@@ -3965,7 +5440,7 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
hfmpi2c->XferISR = NULL;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
- if ((ITFlags & FMPI2C_FLAG_AF) != RESET)
+ if (FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3980,8 +5455,11 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
/* Disable Interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
+ /* Store current volatile hfmpi2c->ErrorCode, misra rule */
+ tmperror = hfmpi2c->ErrorCode;
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT))
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) || (tmperror != HAL_FMPI2C_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
@@ -3999,7 +5477,11 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MemTxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MemTxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else
{
@@ -4009,7 +5491,11 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MasterTxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MasterTxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
/* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
@@ -4024,7 +5510,12 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MemRxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MemRxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else
{
@@ -4033,9 +5524,18 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->MasterRxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_MasterRxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
@@ -4046,12 +5546,12 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
*/
static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
{
+ uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1);
+ uint32_t tmpITFlags = ITFlags;
+
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
- /* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
-
/* Disable all interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
@@ -4065,35 +5565,51 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
FMPI2C_Flush_TXDR(hfmpi2c);
/* If a DMA is ongoing, Update handle size context */
- if (((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) ||
- ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN))
+ if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_TXDMAEN) != RESET)
{
- hfmpi2c->XferCount = FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c);
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx);
+ }
}
-
- /* All data are not transferred, so set error code accordingly */
- if (hfmpi2c->XferCount != 0U)
+ else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET)
{
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx);
+ }
+ }
+ else
+ {
+ /* Do nothing */
}
/* Store Last receive data if any */
- if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ if (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET)
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~FMPI2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
if ((hfmpi2c->XferSize > 0U))
{
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
}
+ /* All data are not transferred, so set error code accordingly */
+ if (hfmpi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
+ }
+
hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferISR = NULL;
@@ -4107,11 +5623,14 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
{
/* Call FMPI2C Listen complete process */
- FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
+ FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags);
}
}
else if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
{
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
+
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4119,7 +5638,11 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->ListenCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
@@ -4129,8 +5652,12 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- /* Call the Slave Rx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->SlaveRxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_SlaveRxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else
{
@@ -4139,8 +5666,12 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- /* Call the Slave Tx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->SlaveTxCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
@@ -4160,10 +5691,13 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
hfmpi2c->XferISR = NULL;
/* Store Last receive data if any */
- if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ if (FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
+ *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hfmpi2c->pBuffPtr++;
if ((hfmpi2c->XferSize > 0U))
{
@@ -4185,7 +5719,11 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
__HAL_UNLOCK(hfmpi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->ListenCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
/**
@@ -4196,6 +5734,8 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags)
*/
static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
{
+ HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State;
+
/* Reset handle parameters */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
@@ -4205,9 +5745,9 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
hfmpi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) ||
- (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
- (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+ if ((tmpstate == HAL_FMPI2C_STATE_LISTEN) ||
+ (tmpstate == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
@@ -4238,18 +5778,21 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
{
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
- /* Set the FMPI2C DMA Abort callback :
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
- hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
+ hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
- {
- /* Call Directly XferAbortCallback function in case of error */
- hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
+ }
}
}
/* Abort DMA RX transfer if any */
@@ -4257,18 +5800,21 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
{
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
- /* Set the FMPI2C DMA Abort callback :
- will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
- hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ /* Set the FMPI2C DMA Abort callback :
+ will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
+ hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
- {
- /* Call Directly hfmpi2c->hdmarx->XferAbortCallback function in case of error */
- hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hfmpi2c->hdmarx->XferAbortCallback function in case of error */
+ hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
+ }
}
}
else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
@@ -4279,7 +5825,11 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->AbortCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else
{
@@ -4287,7 +5837,11 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hfmpi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->ErrorCallback(hfmpi2c);
+#else
HAL_FMPI2C_ErrorCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
@@ -4319,7 +5873,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c)
*/
static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
@@ -4347,10 +5901,16 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
}
/* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
-
- /* Enable TC interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4361,12 +5921,24 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hfmpi2c->XferOptions;
+
+ if ((tmpoptions == FMPI2C_NEXT_FRAME) || (tmpoptions == FMPI2C_FIRST_FRAME))
+ {
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ /* Last Byte is Transmitted */
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4376,7 +5948,7 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
@@ -4404,10 +5976,16 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
}
/* Enable the DMA stream */
- HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
-
- /* Enable TC interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4418,12 +5996,24 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hfmpi2c->XferOptions;
+
+ if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \
+ (tmpoptions != FMPI2C_NO_OPTION_FRAME))
+ {
+ /* Disable DMA Request */
+ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ /* Call FMPI2C Slave Sequential complete process */
+ FMPI2C_ITSlaveSeqCplt(hfmpi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4433,13 +6023,34 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t treatdmaerror = 0U;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
- /* Disable Acknowledge */
- hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ if (hfmpi2c->hdmatx != NULL)
+ {
+ if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U)
+ {
+ treatdmaerror = 1U;
+ }
+ }
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+ if (hfmpi2c->hdmarx != NULL)
+ {
+ if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U)
+ {
+ treatdmaerror = 1U;
+ }
+ }
+
+ /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+ if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+ {
+ /* Disable Acknowledge */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA);
+ }
}
/**
@@ -4450,10 +6061,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
*/
static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Acknowledge */
- hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hfmpi2c->hdmatx->XferAbortCallback = NULL;
@@ -4465,12 +6073,20 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->AbortCpltCallback(hfmpi2c);
+#else
HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1)
+ hfmpi2c->ErrorCallback(hfmpi2c);
+#else
HAL_FMPI2C_ErrorCallback(hfmpi2c);
+#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
}
}
@@ -4491,14 +6107,15 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4526,7 +6143,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4535,7 +6152,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4561,7 +6178,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4570,7 +6187,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4625,7 +6242,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4633,7 +6250,7 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4658,14 +6275,16 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
}
@@ -4682,7 +6301,7 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
/* Clear Configuration Register 2 */
FMPI2C_RESET_CR2(hfmpi2c);
- hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
+ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -4713,7 +6332,7 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2
* @arg @ref FMPI2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* Check the parameters */
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
@@ -4730,9 +6349,9 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAd
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
+static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4794,8 +6413,6 @@ static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16
/* to avoid the risk of FMPI2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_FMPI2C_ENABLE_IT(hfmpi2c, tmpisr);
-
- return HAL_OK;
}
/**
@@ -4803,9 +6420,9 @@ static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param InterruptRequest Value of @ref FMPI2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
+static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4814,7 +6431,7 @@ static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* Disable TC and TXI interrupts */
tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI;
- if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) != (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
@@ -4826,7 +6443,7 @@ static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* Disable TC and RXI interrupts */
tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI;
- if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ if (((uint32_t)hfmpi2c->State & (uint32_t)HAL_FMPI2C_STATE_LISTEN) != (uint32_t)HAL_FMPI2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
@@ -4861,14 +6478,41 @@ static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint1
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_FMPI2C_DISABLE_IT(hfmpi2c, tmpisr);
+}
- return HAL_OK;
+/**
+ * @brief Convert FMPI2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hfmpi2c FMPI2C handle.
+ * @retval None
+ */
+static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c)
+{
+ /* if user set XferOptions to FMPI2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to FMPI2C_FIRST_FRAME */
+ if (hfmpi2c->XferOptions == FMPI2C_OTHER_FRAME)
+ {
+ hfmpi2c->XferOptions = FMPI2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to FMPI2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to FMPI2C_FIRST_AND_LAST_FRAME */
+ else if (hfmpi2c->XferOptions == FMPI2C_OTHER_AND_LAST_FRAME)
+ {
+ hfmpi2c->XferOptions = FMPI2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @}
*/
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* FMPI2C_CR1_PE */
#endif /* HAL_FMPI2C_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c_ex.c
index f3846da12bfb65601494456aedc49aea61d5e4ee..ff996e7eb57ecffa9a75856553e365355be93bc5 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_fmpi2c_ex.c
@@ -21,7 +21,7 @@
##### How to use this driver #####
==============================================================================
- [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ [..] This driver provides functions to:
(#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter()
(#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
@@ -31,29 +31,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -71,9 +55,7 @@
*/
#ifdef HAL_FMPI2C_MODULE_ENABLED
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(FMPI2C_CR1_PE)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -154,7 +136,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigAnalogFilter(FMPI2C_HandleTypeDef *hfmpi2c,
*/
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
@@ -174,7 +156,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c
tmpreg = hfmpi2c->Instance->CR1;
/* Reset FMPI2Cx DNF bits [11:8] */
- tmpreg &= ~(FMPI2C_CR1_DFN);
+ tmpreg &= ~(FMPI2C_CR1_DNF);
/* Set FMPI2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
@@ -201,6 +183,11 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c
* @brief Enable the FMPI2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @note For FMPI2C1, fast mode plus driving capability can be enabled on all selected
+ * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter.
* @retval None
*/
void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
@@ -219,6 +206,11 @@ void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
* @brief Disable the FMPI2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref FMPI2CEx_FastModePlus values
+ * @note For FMPI2C1, fast mode plus driving capability can be disabled on all selected
+ * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter.
* @retval None
*/
void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
@@ -240,8 +232,8 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
/**
* @}
*/
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\
- STM32F413xx || STM32F423xx */
+
+#endif /* FMPI2C_CR1_PE */
#endif /* HAL_FMPI2C_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_gpio.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_gpio.c
index 565ef43e650144f8da8fed0ab259c16c04ddf34a..c9604759633e7cfa767ed42a6a6028b1c15c171a 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_gpio.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_gpio.c
@@ -93,29 +93,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -329,22 +313,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
if(iocurrent == ioposition)
{
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floating Mode */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
-
- /* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
-
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-
- /* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
-
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2U];
tmp &= (0x0FU << (4U * (position & 0x03U)));
@@ -362,6 +330,22 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
}
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floating Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
}
}
}
@@ -453,7 +437,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- GPIOx->ODR ^= GPIO_Pin;
+ if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ }
+ else
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash.c
index 596b8fd893ffb00793e4b74e1bde31634ad2e3c6..96ed151107f31c5f580df179338b1a8a9ae46072 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash.c
@@ -5,90 +5,160 @@
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
- * + Initialization and de-initialization functions
- * + HASH/HMAC Processing functions by algorithm using polling mode
- * + HASH/HMAC functions by algorithm using interrupt mode
- * + HASH/HMAC functions by algorithm using DMA mode
- * + Peripheral State functions
+ * + Initialization and de-initialization methods
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * + Peripheral State methods
+ * + HASH or HMAC processing suspension/resumption
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
[..]
The HASH HAL driver can be used as follows:
+
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
- (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
+ (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+ (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream one for managing data transfer from
+ (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+ (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
+ (+++) Enable the DMAx interface clock using
+ __DMAx_CLK_ENABLE()
+ (+++) Configure and enable one DMA stream to manage data transfer from
memory to peripheral (input stream). Managing data transfer from
- peripheral to memory can be performed only using CPU
+ peripheral to memory can be performed only using CPU.
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
- (##) For HMAC, the encryption key.
- (##) For HMAC, the key size used for encryption.
- (#)Three processing functions are available:
+ interrupt on the DMA Stream: use
+ HAL_NVIC_SetPriority() and
+ HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+ (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+ (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
+
+ (#)Three processing schemes are available:
(##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished
- e.g. HAL_HASH_SHA1_Start()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_HASH_SHA1_Start_IT()
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
(##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA
- e.g. HAL_HASH_SHA1_Start_DMA()
- (#)When the processing function is called at first time after HAL_HASH_Init()
- the HASH peripheral is initialized and processes the buffer in input.
- After that, the digest computation is started.
- When processing multi-buffer use the accumulate function to write the
- data in the peripheral without starting the digest computation. In last
- buffer use the start function to input the last buffer ans start the digest
- computation.
- (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
- (##) write (n-1)th data buffer in the peripheral without starting the digest computation
- (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
- (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
- (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
- After that, call the finish function in order to get the digest value
- e.g. HAL_HASH_SHA1_Finish()
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
+ for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
+ is then required to retrieve the digest.
+
+ (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
+ initialized and processes the buffer fed in input. When the input data have all been
+ fed to the IP, the digest computation can start.
+
+ (#)Multi-buffer processing is possible in polling and DMA mode.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASH_xxx_Finish().
+ (+++) HMAC processing (requires to resort to extended functions):
+ after initialization, the key and the first input buffer are entered
+ in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
+
+
+ (#)Context swapping.
+ (##) Two APIs are available to suspend HASH or HMAC processing:
+ (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
+ (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
+
+ (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
+ to save in memory the IP context. This context can be restored afterwards
+ to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
+
+ (##) Once the HASH IP has been restored to the same configuration as that at suspension
+ time, processing can be restarted with the same API call (same API, same handle,
+ same parameters) as done before the suspension. Relevant parameters to restart at
+ the proper location are internally saved in the HASH handle.
+
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ *** Callback registration ***
+ ===================================
+ [..]
+ (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+
+ (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) InCpltCallback : callback for input completion.
+ (+) DgstCpltCallback : callback for digest computation completion.
+ (+) ErrorCallback : callback for error.
+ (+) MspInitCallback : HASH MspInit.
+ (+) MspDeInitCallback : HASH MspDeInit.
+
+ (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
+ and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+ If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
+ or @ref HAL_HASH_Init function.
+
+ When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -96,227 +166,86 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#if defined (HASH)
-/** @defgroup HASH HASH
+/** @defgroup HASH HASH
* @brief HASH HAL module driver.
* @{
*/
#ifdef HAL_HASH_MODULE_ENABLED
-#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/** @defgroup HASH_Private_Constants HASH Private Constants
* @{
*/
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
+
+/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
+ * @{
+ */
+#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
+#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup HASH_Private_Functions
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
* @{
*/
-
+#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */
/**
- * @brief DMA HASH Input Data complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @}
*/
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0U;
- uint32_t buffersize = 0U;
-
- if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* Increment Interrupt counter */
- hhash->HashInCount++;
- /* Disable the DMA transfer before starting the next transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- if(hhash->HashInCount <= 2U)
- {
- /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
- if(hhash->HashInCount == 1U)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- buffersize = hhash->HashBuffSize;
- }
- /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
- else if(hhash->HashInCount == 2U)
- {
- inputaddr = (uint32_t)hhash->Init.pKey;
- buffersize = hhash->Init.KeySize;
- }
- /* Configure the number of valid bits in last word of the message */
- MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
-
- /* Set the HASH DMA transfer complete */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
- }
- else
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Reset the InCount */
- hhash->HashInCount = 0U;
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-}
+/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
+ * @{
+ */
+#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */
/**
- * @brief DMA HASH communication error callback.
- * @param hdma DMA handle
- * @retval None
+ * @}
*/
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hhash->State= HAL_HASH_STATE_READY;
- HAL_HASH_ErrorCallback(hhash);
-}
+/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
+ * @{
+ */
+#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */
/**
- * @brief Writes the input buffer in data register.
- * @param pInBuffer Pointer to input buffer
- * @param Size The size of input buffer
- * @retval None
+ * @}
*/
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
-{
- uint32_t buffercounter;
- uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0U; buffercounter < Size; buffercounter+=4)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
-}
/**
- * @brief Provides the message digest result.
- * @param pMsgDigest Pointer to the message digest
- * @param Size The size of the message digest in bytes
- * @retval None
+ * @}
*/
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- case 16U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- break;
- case 20U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- break;
- case 28U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
- break;
- case 32U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
- break;
- default:
- break;
- }
-}
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HASH_Exported_Functions
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
-
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization, configuration and call-back functions.
*
@verbatim
===============================================================================
@@ -324,67 +253,110 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the HASH according to the specified parameters
- in the HASH_InitTypeDef and creates the associated handle.
- (+) DeInitialize the HASH peripheral.
- (+) Initialize the HASH MSP.
- (+) DeInitialize HASH MSP.
+ in the HASH_InitTypeDef and create the associated handle
+ (+) DeInitialize the HASH peripheral
+ (+) Initialize the HASH MCU Specific Package (MSP)
+ (+) DeInitialize the HASH MSP
+
+ [..] This section provides as well call back functions definitions for user
+ code to manage:
+ (+) Input data transfer to IP completion
+ (+) Calculated digest retrieval completion
+ (+) Error management
+
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the HASH according to the specified parameters in the
- HASH_HandleTypeDef and creates the associated handle.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Initialize the HASH according to the specified parameters in the
+ HASH_HandleTypeDef and create the associated handle.
+ * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+ * other configuration bits are set by HASH or HMAC processing APIs.
+ * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
+ * multi-buffer HASH processing, user needs to resort to
+ * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
+ * relevant APIs manage themselves the MDMAT bit.
+ * @param hhash: HASH handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
+ /* Check the parameters */
+ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+
/* Check the hash handle allocation */
if(hhash == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if (hhash->State == HAL_HASH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhash->Lock = HAL_UNLOCKED;
+
+ /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ if(hhash->MspInitCallback == NULL)
+ {
+ hhash->MspInitCallback = HAL_HASH_MspInit;
+ }
+ /* Init the low level hardware */
+ hhash->MspInitCallback(hhash);
+ }
+#else
if(hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_HASH_MspInit(hhash);
}
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+ /* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
- /* Reset HashInCount, HashBuffSize and HashITCounter */
- hhash->HashInCount = 0U;
- hhash->HashBuffSize = 0U;
- hhash->HashITCounter = 0U;
+ /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+ hhash->NbWordsAlreadyPushed = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+ /* Set phase to READY */
+ hhash->Phase = HAL_HASH_PHASE_READY;
- /* Set the data type */
- HASH->CR |= (uint32_t) (hhash->Init.DataType);
+ /* Set the data type bit */
+ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
+#if defined(HASH_CR_MDMAT)
+ /* Reset MDMAT bit */
+__HAL_HASH_RESET_MDMAT();
+#endif
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
- /* Change the HASH state */
+ /* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_READY;
- /* Set the default HASH phase */
- hhash->Phase = HAL_HASH_PHASE_READY;
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
- * @brief DeInitializes the HASH peripheral.
- * @note This API must be called before starting a new processing.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief DeInitialize the HASH peripheral.
+ * @param hhash: HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -401,298 +373,1444 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
/* Set the default HASH phase */
hhash->Phase = HAL_HASH_PHASE_READY;
- /* Reset HashInCount, HashBuffSize and HashITCounter */
- hhash->HashInCount = 0U;
- hhash->HashBuffSize = 0U;
- hhash->HashITCounter = 0U;
+ /* Reset HashInCount, HashITCounter and HashBuffSize */
+ hhash->HashInCount = 0;
+ hhash->HashBuffSize = 0;
+ hhash->HashITCounter = 0;
+ /* Reset digest calculation bridle (MDMAT bit control) */
+ hhash->DigestCalculationDisable = RESET;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ if(hhash->MspDeInitCallback == NULL)
+ {
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+ }
- /* DeInit the low level hardware */
+ /* DeInit the low level hardware */
+ hhash->MspDeInitCallback(hhash);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC */
HAL_HASH_MspDeInit(hhash);
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
- /* Change the HASH state */
+
+ /* Reset HASH handle status */
+ hhash->Status = HAL_OK;
+
+ /* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hhash);
+ /* Initialise the error code */
+ hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the HASH MSP.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Initialize the HASH MSP.
+ * @param hhash: HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspInit() can be implemented in the user file.
*/
}
/**
- * @brief DeInitializes HASH MSP.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief DeInitialize the HASH MSP.
+ * @param hhash: HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_MspDeInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_MspDeInit() can be implemented in the user file.
*/
}
/**
- * @brief Input data transfer complete callback.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Input data transfer complete call back.
+ * @note HAL_HASH_InCpltCallback() is called when the complete input message
+ * has been fed to the IP. This API is invoked only when input data are
+ * entered under interruption or thru DMA.
+ * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
+ * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
+ * to the IP.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_InCpltCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_InCpltCallback() can be implemented in the user file.
*/
}
/**
- * @brief Data transfer Error callback.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Digest computation complete call back.
+ * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
+ * relevant with DMA.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_ErrorCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_DgstCpltCallback() can be implemented in the user file.
*/
}
/**
- * @brief Digest computation complete callback. It is used only with interrupt.
- * @note This callback is not relevant with DMA.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
+ * @brief Error callback.
+ * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+ * to retrieve the error type.
+ * @param hhash: HASH handle.
* @retval None
*/
- __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_HASH_DgstCpltCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified; when the callback is needed,
+ HAL_HASH_ErrorCallback() can be implemented in the user file.
*/
}
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
- * @brief processing functions using polling mode
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using polling mode functions#####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
+ * @brief Register a User HASH Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
{
- uint32_t tickstart = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Process Locked */
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
__HAL_LOCK(hhash);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(HAL_HASH_STATE_READY == hhash->State)
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = pCallback;
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
}
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ else if(HAL_HASH_STATE_RESET == hhash->State)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ switch (CallbackID)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
+ else
+ {
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
+ /* Release Lock */
__HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is multiple of 64 bytes, appending the input buffer is possible.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware
- * and appending the input buffer is no more possible.
- * @retval HAL status
+ * @brief Unregister a HASH Callback
+ * HASH Callback is redirected to the weak (surcharged) predefined callback
+ * @param hhash HASH handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+ * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+ * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+ * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+ * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+ * @retval status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
+HAL_StatusTypeDef status = HAL_OK;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Process locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(HAL_HASH_STATE_READY == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_INPUTCPLT_CB_ID :
+ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
+ break;
+
+ case HAL_HASH_DGSTCPLT_CB_ID :
+ hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+ break;
+
+ case HAL_HASH_ERROR_CB_ID :
+ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
+ break;
+
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_HASH_STATE_RESET == hhash->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HASH_MSPINIT_CB_ID :
+ hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
+ break;
+
+ case HAL_HASH_MSPDEINIT_CB_ID :
+ hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
+ /* Update the error code */
+ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
}
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Release Lock */
+ __HAL_UNLOCK(hhash);
+ return status;
+}
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+/**
+ * @}
+ */
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ * @brief HASH processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start()
+ (++) HAL_HASH_MD5_Accumulate()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start()
+ (++) HAL_HASH_SHA1_Accumulate()
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the IP), the user can resort to successive calls
+ to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASH_xxx_Start().
- /* Return function status */
- return HAL_OK;
-}
+@endverbatim
+ * @{
+ */
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+/**
+ * @brief If not already done, initialize the HASH peripheral in MD5 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_MD5_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief If not already done, initialize the HASH peripheral in SHA1 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASH_SHA1_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ * @brief HASH processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interruption mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_IT()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_IT()
+
+ [..] API HAL_HASH_IRQHandler() manages each HASH interruption.
+
+ [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+ HMAC processing mode.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @brief Handle HASH interrupt request.
+ * @param hhash: HASH handle.
+ * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
+ * @note In case of error reported during the HASH interruption processing,
+ * HAL_HASH_ErrorCallback() API is called so that user code can
+ * manage the error. The error type is available in hhash->Status field.
+ * @retval None
+ */
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
+{
+ hhash->Status = HASH_IT(hhash);
+ if (hhash->Status != HAL_OK)
+ {
+ hhash->ErrorCode |= HAL_HASH_ERROR_IT;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ * @brief HASH processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HASH_MD5_Start_DMA()
+ (++) HAL_HASH_MD5_Finish()
+ (+) SHA1
+ (++) HAL_HASH_SHA1_Start_DMA()
+ (++) HAL_HASH_SHA1_Finish()
+
+ [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASH_xxx_Finish().
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Return the computed digest in MD5 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
+ * HMAC MD5 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+
+/**
+ * @brief Return the computed digest in SHA1 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA1 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ * @brief HMAC processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start()
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ * @brief HMAC processing functions using interrupt mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupt mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in interrupt mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_IT()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_IT()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
+}
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+{
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ * @brief HMAC processing functions using DMA modes.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HMAC processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the HMAC value using one of the following algorithms:
+ (+) MD5
+ (++) HAL_HMAC_MD5_Start_DMA()
+ (+) SHA1
+ (++) HAL_HMAC_SHA1_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASH_xxx_Finish().
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State methods #####
+ ===============================================================================
+ [..]
+ This section permits to get in run-time the state and the peripheral handle
+ status of the peripheral:
+ (+) HAL_HASH_GetState()
+ (+) HAL_HASH_GetStatus()
+
+ [..]
+ Additionally, this subsection provides functions allowing to save and restore
+ the HASH or HMAC processing context in case of calculation suspension:
+ (+) HAL_HASH_ContextSaving()
+ (+) HAL_HASH_ContextRestoring()
+
+ [..]
+ This subsection provides functions allowing to suspend the HASH processing
+ (+) when input are fed to the IP by software
+ (++) HAL_HASH_SwFeed_ProcessSuspend()
+ (+) when input are fed to the IP by DMA
+ (++) HAL_HASH_DMAFeed_ProcessSuspend()
+
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the HASH handle state.
+ * @note The API yields the current state of the handle (BUSY, READY,...).
+ * @param hhash: HASH handle.
+ * @retval HAL HASH state
+ */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+ return hhash->State;
+}
+
+
+/**
+ * @brief Return the HASH HAL status.
+ * @note The API yields the HAL status of the handle: it is the result of the
+ * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
+ * @param hhash: HASH handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+{
+ return hhash->Status;
+}
+
+/**
+ * @brief Save the HASH context in case of processing suspension.
+ * @param hhash: HASH handle.
+ * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * is saved.
+ * @note The IMR, STR, CR then all the CSR registers are saved
+ * in that order. Only the r/w bits are read to be restored later on.
+ * @note By default, all the context swap registers (there are
+ * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
+ * @note pMemBuffer points to a buffer allocated by the user. The buffer size
+ * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
+ * @retval None
+ */
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Save IMR register content */
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
+ mem_ptr+=4U;
+ /* Save STR register content */
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
+ mem_ptr+=4U;
+ /* Save CR register content */
+#if defined(HASH_CR_MDMAT)
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
+#else
+ *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY);
+#endif
+ mem_ptr+=4U;
+ /* By default, save all CSRs registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ {
+ *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
+ mem_ptr+=4U;
+ csr_ptr+=4U;
+ }
+}
+
+
+/**
+ * @brief Restore the HASH context in case of processing resumption.
+ * @param hhash: HASH handle.
+ * @param pMemBuffer: pointer to the memory buffer where the HASH context
+ * is stored.
+ * @note The IMR, STR, CR then all the CSR registers are restored
+ * in that order. Only the r/w bits are restored.
+ * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+ * of those) are restored (all of them have been saved by default
+ * beforehand).
+ * @retval None
+ */
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+ uint32_t mem_ptr = (uint32_t)pMemBuffer;
+ uint32_t csr_ptr = (uint32_t)HASH->CSR;
+ uint32_t i;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhash);
+
+ /* Restore IMR register content */
+ WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ /* Restore STR register content */
+ WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ /* Restore CR register content */
+ WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+
+ /* Reset the HASH processor before restoring the Context
+ Swap Registers (CSR) */
+ __HAL_HASH_INIT();
+
+ /* By default, restore all CSR registers */
+ for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+ {
+ WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
+ mem_ptr+=4U;
+ csr_ptr+=4U;
+ }
+}
+
+
+/**
+ * @brief Initiate HASH processing suspension when in polling or interruption mode.
+ * @param hhash: HASH handle.
+ * @note Set the handle field SuspendRequest to the appropriate value so that
+ * the on-going HASH processing is suspended as soon as the required
+ * conditions are met. Note that the actual suspension is carried out
+ * by the functions HASH_WriteData() in polling mode and HASH_IT() in
+ * interruption mode.
+ * @retval None
+ */
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ /* Set Handle Suspend Request field */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND;
+}
+
+/**
+ * @brief Suspend the HASH processing when in DMA mode.
+ * @param hhash: HASH handle.
+ * @note When suspension attempt occurs at the very end of a DMA transfer and
+ * all the data have already been entered in the IP, hhash->State is
+ * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
+ * recommended to wrap-up the processing in reading the digest as usual.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+ uint32_t tmp_remaining_DMATransferSize_inWords;
+ uint32_t tmp_initial_DMATransferSize_inWords;
+ uint32_t tmp_words_already_pushed;
+
+ if (hhash->State == HAL_HASH_STATE_READY)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Make sure there is enough time to suspend the processing */
+ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+ if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
+ {
+ /* No suspension attempted since almost to the end of the transferred data. */
+ /* Best option for user code is to wrap up low priority message hashing */
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be reset */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable DMA channel */
+ if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK)
+ {
+ /*
+ Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ }
+
+ /* Clear DMAE bit */
+ CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* At this point, DMA interface is disabled and no transfer is on-going */
+ /* Retrieve from the DMA handle how many words remain to be written */
+ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+ if (tmp_remaining_DMATransferSize_inWords == 0U)
+ {
+ /* All the DMA transfer is actually done. Suspension occurred at the very end
+ of the transfer. Either the digest computation is about to start (HASH case)
+ or processing is about to move from one step to another (HMAC case).
+ In both cases, the processing can't be suspended at this point. It is
+ safer to
+ - retrieve the low priority block digest before starting the high
+ priority block processing (HASH case)
+ - re-attempt a new suspension (HMAC case)
+ */
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Compute how many words were supposed to be transferred by DMA */
+ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+
+ /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
+ by HASH IP, correct it */
+ /* tmp_words_already_pushed reflects the number of words that were already pushed before
+ the start of DMA transfer (multi-buffer processing case) */
+ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
+ if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED())
+ {
+ tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
+ }
+
+ /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+
+ /* And store in HashInCount the remaining size to transfer (in bytes) */
+ hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
+
+ }
+
+ /* Set State as suspended */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+
+ }
+}
+
+/**
+ * @brief Return the HASH handle error code.
+ * @param hhash: pointer to a HASH_HandleTypeDef structure.
+ * @retval HASH Error Code
+*/
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+{
+ /* Return HASH Error Code */
+ return hhash->ErrorCode;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HASH_Private_Functions HASH Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA HASH Input Data transfer completion callback.
+ * @param hdma: DMA handle.
+ * @note In case of HMAC processing, HASH_DMAXferCplt() initiates
+ * the next DMA transfer for the following HMAC step.
+ * @retval None
+ */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t inputaddr;
+ uint32_t buffersize;
+ HAL_StatusTypeDef status ;
+
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+
+ /* Disable the DMA transfer */
+ CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+
+ if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
+ {
+ /* If no HMAC processing, input data transfer is now over */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ }
+ else
+ {
+ /* HMAC processing: depending on the current HMAC step and whether or
+ not multi-buffer processing is on-going, the next step is initiated
+ and MDMAT bit is set. */
+
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+ {
+ /* This is the end of HMAC processing */
+
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Call Input data transfer complete call back
+ (note that the last DMA transfer was that of the key
+ for the outer HASH operation). */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ return;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
+ buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+#if defined(HASH_CR_MDMAT)
+ /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
+ no digest calculation will be triggered at the end of the input buffer feeding to the IP */
+ __HAL_HASH_SET_MDMAT();
+ }
+#endif
+ }
+ else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
+ {
+ if (hhash->DigestCalculationDisable != RESET)
+ {
+ /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+ (case of multi-buffer HMAC processing):
+ DCAL must not be set.
+ Phase remains in Step 2, MDMAT remains set at this point.
+ Change the HASH state to ready and call Input data transfer complete call back. */
+ hhash->State = HAL_HASH_STATE_READY;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ return ;
+ }
+ else
+ {
+ /* Digest calculation is not disabled (case of single buffer input or last buffer
+ of multi-buffer HMAC processing) */
+ inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */
+ buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ /* In case of suspension request, save the new starting parameters */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
+
+ hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
+ }
+ }
+
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(buffersize);
+
+ /* Set the HASH DMA transfert completion call back */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hhash->State = HAL_HASH_STATE_READY;
+ }
+ }
+ }
+
+ return;
+}
+
+/**
+ * @brief DMA HASH communication error callback.
+ * @param hdma: DMA handle.
+ * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
+ * can contain user code to manage the error.
+ * @retval None
+ */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
+ hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+ /* Set HASH state to ready to prevent any blocking issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State= HAL_HASH_STATE_READY;
+ /* Set HASH handle status to error */
+ hhash->Status = HAL_ERROR;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->ErrorCallback(hhash);
+#else
+ HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+ /* After error handling by code user, reset HASH handle HAL status */
+ hhash->Status = HAL_OK;
+
}
+}
+
+/**
+ * @brief Feed the input buffer to the HASH IP.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to input buffer.
+ * @param Size: the size of input buffer in bytes.
+ * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the IP feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ uint32_t buffercounter;
+ __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+
+ for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+ {
+ /* Write input data 4 bytes at a time */
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+ {
+ /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
+ in the input buffer */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Depending whether the key or the input data were fed to the IP, the feeding point
+ reached at suspension time is not saved in the same handle fields */
+ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashInCount = Size - (buffercounter + 4U);
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashKeyCount = Size - (buffercounter + 4U);
+ }
+ else
+ {
+ /* Unexpected phase: unlock process and report error */
+ hhash->State = HAL_HASH_STATE_READY;
+ __HAL_UNLOCK(hhash);
+ return HAL_ERROR;
+ }
+
+ /* Set the HASH state to Suspended and exit to stop entering data */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ return HAL_OK;
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
+ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
+
+ /* At this point, all the data have been entered to the IP: exit */
+ return HAL_OK;
+}
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+/**
+ * @brief Retrieve the message digest.
+ * @param pMsgDigest: pointer to the computed digest.
+ * @param Size: message digest size in bytes.
+ * @retval None
+ */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+ uint32_t msgdigest = (uint32_t)pMsgDigest;
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ switch(Size)
+ {
+ /* Read the message digest */
+ case 16: /* MD5 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ break;
+ case 20: /* SHA1 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+ break;
+ case 28: /* SHA224 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+#if defined(HASH_CR_MDMAT)
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+#endif
+ break;
+ case 32: /* SHA256 */
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+#if defined(HASH_CR_MDMAT)
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+ msgdigest+=4U;
+ *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+#endif
+ break;
+ default:
+ break;
+ }
+}
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief Handle HASH processing Timeout.
+ * @param hhash: HASH handle.
+ * @param Flag: specifies the HASH flag to check.
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_HASH_GET_FLAG(Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
{
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hhash);
@@ -701,1166 +1819,1267 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
}
}
}
+ }
+ else
+ {
+ while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Set State to Ready to be able to restart later on */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Store time out issue in handle status */
+ hhash->Status = HAL_TIMEOUT;
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Return function status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
+ * @brief HASH processing in interruption mode.
+ * @param hhash: HASH handle.
+ * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
+ * or not the HASH processing must be suspended. If this is the case, the
+ * processing is suspended when possible and the IP feeding point reached at
+ * suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
{
- /* Check the parameters */
- assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ if (hhash->State == HAL_HASH_STATE_BUSY)
+ {
+ /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
+ if(hhash->HashITCounter == 0U)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ /* HASH state set back to Ready to prevent any issue in user code
+ present in HAL_HASH_ErrorCallback() */
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if (hhash->HashITCounter == 1U)
+ {
+ /* This is the first call to HASH_IT, the first input data are about to be
+ entered in the IP. A specific processing is carried out at this point to
+ start-up the processing. */
+ hhash->HashITCounter = 2U;
+ }
+ else
+ {
+ /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
+ the HASH processing or the end of the current step for HMAC processing. */
+ hhash->HashITCounter = 3U;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* If digest is ready */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+ {
+ /* Read the digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
- }
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ /* Call digest computation complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->DgstCpltCallback(hhash);
+#else
+ HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ return HAL_OK;
+ }
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ /* If IP ready to accept new data */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+ {
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+ /* If the suspension flag has been raised and if the processing is not about
+ to end, suspend processing */
+ if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
- /* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+ }
-/**
- * @}
- */
+ /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+ check whether the digest calculation has been triggered */
+ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
+ {
+ /* Call Input data transfer complete call back
+ (called at the end of each step for HMAC) */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+ hhash->InCpltCallback(hhash);
+#else
+ HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /* Wait until IP is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
+ hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Wait until IP is not busy anymore */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+ return HAL_TIMEOUT;
+ }
+ /* Initialization start for HMAC STEP 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
+ hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
+ hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
+ hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
-/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using interrupt mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @brief Write a block of data in HASH IP in interruption mode.
+ * @param hhash: HASH handle.
+ * @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
{
uint32_t inputaddr;
- uint32_t outputaddr;
uint32_t buffercounter;
uint32_t inputcounter;
+ uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* If there are more than 64 bytes remaining to be entered */
+ if(hhash->HashInCount > 64U)
+ {
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Write the Input block in the Data IN register
+ (16 32-bit words, or 64 bytes are entered) */
+ for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* If this is the start of input data entering, an additional word
+ must be entered to start up the HASH processing */
+ if(hhash->HashITCounter == 2U)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ if(hhash->HashInCount >= 68U)
+ {
+ /* There are still data waiting to be entered in the IP.
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round. */
+ hhash->HashInCount -= 68U;
+ hhash->pHashInBuffPtr+= 68U;
+ }
+ else
+ {
+ /* All the input buffer has been fed to the HW. */
+ hhash->HashInCount = 0U;
+ }
+ }
+ else
+ {
+ /* 64 bytes have been entered and there are still some remaining:
+ Decrement buffer counter and set pointer to the proper
+ memory location for the next data entering round.*/
+ hhash->HashInCount -= 64U;
+ hhash->pHashInBuffPtr+= 64U;
+ }
+ }
+ else
+ {
+ /* 64 or less bytes remain to be entered. This is the last
+ data entering round. */
+
+ /* Get the buffer address */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+ /* Get the buffer counter */
+ inputcounter = hhash->HashInCount;
+ /* Disable Interrupts */
+ __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
+
+ /* Write the Input block in the Data IN register */
+ for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+ {
+ HASH->DIN = *(uint32_t*)inputaddr;
+ inputaddr+=4U;
+ }
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
+ /* Return indication that digest calculation has started:
+ this return value triggers the call to Input data transfer
+ complete call back as well as the proper transition from
+ one step to another in HMAC mode. */
+ ret = HASH_DIGEST_CALCULATION_STARTED;
+ /* Reset buffer counter */
+ hhash->HashInCount = 0;
+ }
- if(hhash->State == HAL_HASH_STATE_READY)
+ /* Return whether or digest calculation has started */
+ return ret;
+}
+
+/**
+ * @brief HMAC processing in polling mode.
+ * @param hhash: HASH handle.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+{
+ /* Ensure first that Phase is correct */
+ if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ hhash->State = HAL_HASH_STATE_READY;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
+ /* HMAC Step 1 processing */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+ {
+ /************************** STEP 1 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
{
- /* Select the SHA1 mode */
- HASH->CR |= HASH_ALGOSELECTION_MD5;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
+ return hhash->Status;
}
- /* Reset interrupt counter */
- hhash->HashITCounter = 0U;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 1 to Step 2 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
- /* Return function status */
- return HAL_OK;
}
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+
+ /* HMAC Step 2 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 2 processing was suspended previously
+ - or fall through from the Step 1 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
-
- if(hhash->HashInCount == 0U)
+ /************************** STEP 2 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
+ if (hhash->Status != HAL_OK)
{
- /* Disable Interrupts */
- HASH->IMR = 0U;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
+ return hhash->Status;
+ }
+ /* Check whether or not data entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
/* Process Unlocked */
__HAL_UNLOCK(hhash);
- /* Return function status */
+ /* Stop right there and return function status */
return HAL_OK;
}
+
+ /* No processing suspension at this point: set DCAL bit. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for BUSY flag to be cleared */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Move from Step 2 to Step 3 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+ /* In case Step 1 phase was suspended then resumed,
+ set again Key input buffers and size before moving to
+ next step */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+ hhash->HashKeyCount = hhash->Init.KeySize;
}
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+
+
+ /* HMAC Step 3 processing.
+ After phase check, HMAC_Processing() may
+ - directly start up from this point in resumption case
+ if the same Step 3 processing was suspended previously
+ - or fall through from the Step 2 processing carried out hereabove */
+ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
- if(hhash->HashInCount >= 68U)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- if(hhash->HashITCounter == 0U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
+ /************************** STEP 3 ******************************************/
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- if(hhash->HashInCount >= 68U)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
- }
- else
- {
- hhash->HashInCount = 0U;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1U;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
- }
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+ if (hhash->Status != HAL_OK)
+ {
+ return hhash->Status;
}
- else
+
+ /* Check whether or not key entering process has been suspended */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- if((inputcounter > 4U) && (inputcounter%4U))
- {
- inputcounter = (inputcounter+4U-inputcounter%4U);
- }
- else if ((inputcounter < 4U) && (inputcounter != 0U))
- {
- inputcounter = 4U;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0U;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
+ /* Stop right there and return function status */
+ return HAL_OK;
+ }
+
+ /* No processing suspension at this point: start the Digest calculation. */
+ __HAL_HASH_START_DIGEST();
+
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
}
+
+ /* Read the message digest */
+ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
}
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
- /* Return function status */
- return HAL_OK;
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
{
- uint32_t inputaddr;
- uint32_t outputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Process Locked */
- __HAL_LOCK(hhash);
- if(hhash->State == HAL_HASH_STATE_READY)
+ /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
+ /* Check if initialization phase has not been already performed */
if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- /* Select the SHA1 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA1;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
- /* Reset interrupt counter */
- hhash->HashITCounter = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
- /* Read the Output block from the Output FIFO */
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
- outputaddr+=4U;
- *(uint32_t*)(outputaddr) = __REV(HASH->HR[4U]);
- if(hhash->HashInCount == 0U)
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
- /* Disable Interrupts */
- HASH->IMR = 0U;
+ /* if the IP has already been initialized, two cases are possible */
+
+ /* Process resumption time ... */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr;
+ Size_tmp = hhash->HashInCount;
+ }
+ /* ... or multi-buffer HASH processing end */
+ else
+ {
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer;
+ Size_tmp = Size;
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
+ }
/* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ }
+ else
+ {
+ /* Phase error */
hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
- return HAL_OK;
+ return HAL_ERROR;
}
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68U)
+
+
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
{
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- if(hhash->HashITCounter == 0U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- if(hhash->HashInCount >= 68U)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
- }
- else
- {
- hhash->HashInCount = 0U;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1U;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
- }
+ return hhash->Status;
}
- else
+
+ /* If the process has not been suspended, carry on to digest calculation */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
+ /* Start the Digest calculation */
+ __HAL_HASH_START_DIGEST();
- if((inputcounter > 4U) && (inputcounter%4U))
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
- inputcounter = (inputcounter+4U-inputcounter%4U);
- }
- else if ((inputcounter < 4U) && (inputcounter != 0U))
- {
- inputcounter = 4U;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
+ return HAL_TIMEOUT;
}
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0U;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
- /* Return function status */
- return HAL_OK;
-}
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
-/**
- * @brief This function handles HASH interrupt request.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
- */
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
-{
- switch(HASH->CR & HASH_CR_ALGO)
- {
- case HASH_ALGOSELECTION_MD5:
- HAL_HASH_MD5_Start_IT(hhash, NULL, 0U, NULL);
- break;
+ }
- case HASH_ALGOSELECTION_SHA1:
- HAL_HASH_SHA1_Start_IT(hhash, NULL, 0U, NULL);
- break;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- default:
- break;
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
}
}
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
- *
-@verbatim
- ===============================================================================
- ##### HASH processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
- control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief If not already done, initialize the HASH peripheral then
+ * processes pInBuffer.
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
+ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+ assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* If resuming the HASH processing */
+ if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+ to the API input parameters but to those saved beforehand by HASH_WriteData()
+ when the processing was suspended */
+ pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
- /* Return function status */
- return HAL_OK;
-}
+ }
+ else
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
-/**
- * @brief Returns the computed digest in MD5 mode
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
+ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+ input parameters of HASH_WriteData() */
+ pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
+ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+ }
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* Get tick */
- tickstart = HAL_GetTick();
+ }
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Write input buffer in Data register */
+ hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+ if (hhash->Status != HAL_OK)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ return hhash->Status;
+ }
- return HAL_TIMEOUT;
- }
+ /* If the process has not been suspended, move the state to Ready */
+ if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+ {
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
}
- }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16U);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
+ /* Return function status */
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
}
+
/**
- * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA1;
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Configure the number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Return function status */
- return HAL_OK;
-}
-/**
- * @brief Returns the computed digest in SHA1 mode.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
-{
- uint32_t tickstart = 0U;
+ hhash->HashInCount = Size; /* Counter used to keep track of number of data
+ to be fed to the IP */
+ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at
+ the next interruption */
+ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+ the information describing where the HASH process is stopped.
+ These variables are used later on to resume the HASH processing at the
+ correct location. */
- /* Process Locked */
- __HAL_LOCK(hhash);
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
+ }
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
- /* Get tick */
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- return HAL_TIMEOUT;
- }
- }
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
}
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20U);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using polling mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+#if defined (HASH_CR_MDMAT)
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
+ (case of multi-buffer HASH processing) */
+ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
+#endif /* MDMA defined*/
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
+ /* Check input parameters */
+ if ( (pInBuffer == NULL ) || (Size == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or PROCESS (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
{
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* If not a resumption case */
+ if (hhash->State == HAL_HASH_STATE_READY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Check if initialization phase has already been performed.
+ If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+ API is processing a new input data message in case of multi-buffer HASH
+ computation. */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
- return HAL_TIMEOUT;
+ /* Set the phase */
+ hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+ /* Configure the Number of valid bits in last word of the message */
+ __HAL_HASH_SET_NBVALIDBITS(Size);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */
+ inputSize = Size; /* DMA transfer size (in bytes) */
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* In case of suspension request, save the starting parameters */
+ hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */
+ hhash->HashInCount = Size; /* DMA transfer size (in bytes) */
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ }
+ /* If resumption case */
+ else
{
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Resumption case, inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended */
+ inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
+ inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
- return HAL_TIMEOUT;
- }
}
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Set the HASH DMA transfert complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- return HAL_TIMEOUT;
- }
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
}
- }
-
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 16U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Return the computed digest.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if(hhash->State == HAL_HASH_STATE_READY)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
+ /* Check parameter */
+ if (pOutBuffer == NULL)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ return HAL_ERROR;
}
- }
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Change the HASH state to busy */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Wait for DCIS flag to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ /* Read the message digest */
+ HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the HASH state to ready */
+ hhash->State = HAL_HASH_STATE_READY;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
+ /* Process UnLock */
+ __HAL_UNLOCK(hhash);
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Return function status */
+ return HAL_OK;
- return HAL_TIMEOUT;
- }
- }
}
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Write input buffer in data register */
- HASH_WriteData(pInBuffer, Size);
+}
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Timeout: Timeout value.
+ * @param Algorithm: HASH algorithm.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
+ /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
{
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
}
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Write input buffer in data register */
- HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Check if initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- if((HAL_GetTick() - tickstart ) > Timeout)
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if(hhash->Init.KeySize > 64U)
{
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ /* Resort to hhash internal fields to feed the IP.
+ Parameters will be updated in case of suspension to contain the proper
+ information at resumption time. */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */
+ hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */
+ hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
+ hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */
}
- }
- /* Read the message digest */
- HASH_GetDigest(pOutBuffer, 20U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Carry out HMAC processing */
+ return HMAC_Processing(hhash, Timeout);
- /* Return function status */
- return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
-/**
- * @}
- */
-
-/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA mode functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) MD5
- (+) SHA1
-@endverbatim
- * @{
- */
/**
- * @brief Initializes the HASH peripheral in HMAC MD5 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
{
- uint32_t inputaddr = 0U;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
- /* Process Locked */
- __HAL_LOCK(hhash);
+ /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0U;
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
+ /* Initialize IT counter */
+ hhash->HashITCounter = 1;
+
+ /* Check if initialization phase has already be performed */
+ if (hhash->Phase == HAL_HASH_PHASE_READY)
+ {
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if(hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+
+ /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
+ to feed the IP whatever the HMAC step.
+ Lines below are set to start HMAC Step 1 processing where key is entered first. */
+ hhash->HashInCount = hhash->Init.KeySize; /* Key size */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
+
+ /* Store input and output parameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */
+ hhash->HashBuffSize = Size; /* Input message size (in bytes) */
+ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
+
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
+
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ /* Restart IT-based HASH processing after Step 2 suspension */
+
}
else
{
- /* Select the HMAC MD5 mode */
- HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ /* Error report as phase incorrect */
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
}
- }
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Process Unlock */
+ __HAL_UNLOCK(hhash);
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
+ /* Enable Interrupts */
+ __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+}
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
-}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA1 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
+ * be a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * Only the length of the last buffer of the thread doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param Algorithm: HASH algorithm.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
- uint32_t inputaddr = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ uint32_t inputaddr;
+ uint32_t inputSize;
+ HAL_StatusTypeDef status ;
+ HAL_HASH_StateTypeDef State_tmp = hhash->State;
+ /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+ is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+ assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+ /* If State is ready or suspended, start or resume DMA-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+ {
+ /* Check input parameters */
+ if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
+ /* Check phase coherency. Phase must be
+ either READY (fresh start)
+ or one of HMAC PROCESS steps (multi-buffer HASH management) */
+ ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+ {
+ hhash->State = HAL_HASH_STATE_READY;
+ return HAL_ERROR;
+ }
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0U;
+ /* Process Locked */
+ __HAL_LOCK(hhash);
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
+ /* If not a case of resumption after suspension */
+ if (hhash->State == HAL_HASH_STATE_READY)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
+ /* Check whether or not initialization phase has already be performed */
+ if(hhash->Phase == HAL_HASH_PHASE_READY)
{
- /* Select the HMAC SHA1 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+ #if defined(HASH_CR_MDMAT)
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+ At the same time, ensure MDMAT bit is cleared. */
+ if(hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ #else
+ /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+ if(hhash->Init.KeySize > 64U)
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+ }
+ else
+ {
+ MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+ }
+ #endif
+ /* Store input aparameters in handle fields to manage steps transition
+ or possible HMAC suspension/resumption */
+ hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
+ hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
+ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+ hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
+ hhash->HashBuffSize = Size; /* input data size (in bytes) */
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
+ inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+ /* Configure the number of valid bits in last word of the key */
+ __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
+ /* Set the phase to Step 1 */
+ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASH_DMAError;
+ }
+ else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+ {
+ /* Process a new input data message in case of multi-buffer HMAC processing
+ (this is not a resumption case) */
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ /* Save input parameters to be able to manage possible suspension/resumption */
+ hhash->HashInCount = Size; /* Input message address */
+ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
- /* Return function status */
- return HAL_OK;
-}
+ /* Set DMA input parameters */
+ inputaddr = (uint32_t)pInBuffer; /* Input message address */
+ inputSize = Size; /* Input message size in bytes */
-/**
- * @}
- */
+ if (hhash->DigestCalculationDisable == RESET)
+ {
+ /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+#if defined(HASH_CR_MDMAT)
+ __HAL_HASH_RESET_MDMAT();
+#endif
+ __HAL_HASH_SET_NBVALIDBITS(inputSize);
+ }
+ }
+ else
+ {
+ /* Phase not aligned with handle READY state */
+ __HAL_UNLOCK(hhash);
+ /* Return function status */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Resumption case (phase may be Step 1, 2 or 3) */
-/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral.
+ /* Change the HASH state */
+ hhash->State = HAL_HASH_STATE_BUSY;
+
+ /* Set DMA input parameters at resumption location;
+ inputaddr and inputSize are not set to the API input parameters
+ but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+ processing was suspended. */
+ inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */
+ inputSize = hhash->HashInCount; /* Input message size in bytes */
+ }
-@endverbatim
- * @{
- */
-/**
- * @brief return the HASH state
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval HAL state
- */
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
-{
- return hhash->State;
-}
+ /* Set the HASH DMA transfert complete callback */
+ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+ /* Set the DMA error callback */
+ hhash->hdmain->XferErrorCallback = HASH_DMAError;
-/**
- * @}
- */
+ /* Store number of words already pushed to manage proper DMA processing suspension */
+ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+ /* Enable the DMA In DMA Stream */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+ /* Enable DMA requests */
+ SET_BIT(HASH->CR, HASH_CR_DMAE);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhash);
+
+ /* Return function status */
+ if (status != HAL_OK)
+ {
+ /* Update HASH state machine to error */
+ hhash->State = HAL_HASH_STATE_ERROR;
+ }
+ else
+ {
+ /* Change HASH state */
+ hhash->State = HAL_HASH_STATE_READY;
+ }
+ /* Return function status */
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
/**
* @}
*/
-#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
#endif /* HAL_HASH_MODULE_ENABLED */
+
/**
* @}
*/
-
+#endif /* HASH*/
/**
* @}
*/
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash_ex.c
index b9b92f8606e93a1ed60fa2e627663fcc913a5706..792b2e58fd52bbfea38d10e617266bad9386620e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hash_ex.c
@@ -2,90 +2,76 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
- * @brief HASH HAL Extension module driver.
+ * @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of HASH peripheral:
- * + Extended HASH processing functions based on SHA224 Algorithm
- * + Extended HASH processing functions based on SHA256 Algorithm
+ * functionalities of the HASH peripheral for SHA-224 and SHA-256
+ * alogrithms:
+ * + HASH or HMAC processing in polling mode
+ * + HASH or HMAC processing in interrupt mode
+ * + HASH or HMAC processing in DMA mode
+ * Additionally, this file provides functions to manage HMAC
+ * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
+ * and SHA-256.
+ *
*
@verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
+ ===============================================================================
+ ##### HASH peripheral extended features #####
+ ===============================================================================
[..]
- The HASH HAL driver can be used as follows:
- (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
- (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
- (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
- (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
- (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
- (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
- (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
- (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream one for managing data transfer from
- memory to peripheral (input stream). Managing data transfer from
- peripheral to memory can be performed only using CPU
- (+++) Associate the initialized DMA handle to the HASH DMA handle
- using __HAL_LINKDMA()
- (+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
- (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
- (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
- (##) For HMAC, the encryption key.
- (##) For HMAC, the key size used for encryption.
- (#)Three processing functions are available:
+ The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
+ the same way as for SHA-1 or MD-5 algorithms.
+ (#) Three modes are available.
(##) Polling mode: processing APIs are blocking functions
- i.e. they process the data and wait till the digest computation is finished
- e.g. HAL_HASHEx_SHA224_Start()
- (##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
- e.g. HAL_HASHEx_SHA224_Start_IT()
+ i.e. they process the data and wait till the digest computation is finished,
+ e.g. HAL_HASHEx_xxx_Start()
+ (##) Interrupt mode: processing APIs are not blocking functions
+ i.e. they process the data under interrupt,
+ e.g. HAL_HASHEx_xxx_Start_IT()
(##) DMA mode: processing APIs are not blocking functions and the CPU is
- not used for data transfer i.e. the data transfer is ensured by DMA
- e.g. HAL_HASHEx_SHA224_Start_DMA()
- (#)When the processing function is called at first time after HAL_HASH_Init()
- the HASH peripheral is initialized and processes the buffer in input.
- After that, the digest computation is started.
- When processing multi-buffer use the accumulate function to write the
- data in the peripheral without starting the digest computation. In last
- buffer use the start function to input the last buffer ans start the digest
- computation.
- (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
- (##) write (n-1)th data buffer in the peripheral without starting the digest computation
- (##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
- (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
- (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
- After that, call the finish function in order to get the digest value
- e.g. HAL_HASHEx_SHA224_Finish()
- (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ not used for data transfer i.e. the data transfer is ensured by DMA,
+ e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
+ HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
+
+ (#)Multi-buffer processing is possible in polling and DMA mode.
+ (##) In polling mode, only multi-buffer HASH processing is possible.
+ API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
+ User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as
+ well the computed digest.
+
+ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API.
+ Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
+ macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
+ API HAL_HASHEx_xxx_Finish().
+
+ (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
+ extended functions): after initialization, the key and the first input buffer are entered
+ in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ starts step 2.
+ The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
+ point, the HMAC processing is still carrying out step 2.
+ Then, step 2 for the last input buffer and step 3 are carried out by a single call
+ to HAL_HMACEx_xxx_Step2_3_DMA().
+
+ The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
+ MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -93,1544 +79,838 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+
+
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+#if defined (HASH)
/** @defgroup HASHEx HASHEx
- * @brief HASH Extension HAL module driver.
+ * @brief HASH HAL extended module driver.
* @{
*/
-
#ifdef HAL_HASH_MODULE_ENABLED
-
-#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup HASHEx_Private_Functions
+/* Private functions ---------------------------------------------------------*/
+#if defined (HASH_CR_MDMAT)
+
+/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
-static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
-static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
+/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
+ * @brief HASH extended processing functions using polling mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Polling mode HASH extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in polling mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start()
+ (++) HAL_HASHEx_SHA224_Accumulate()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start()
+ (++) HAL_HASHEx_SHA256_Accumulate()
+
+ [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
-/** @addtogroup HASHEx_Private_Functions
+ [..] In case of multi-buffer HASH processing (a single digest is computed while
+ several buffers are fed to the IP), the user can resort to successive calls
+ to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
+ to HAL_HASHEx_xxx_Start().
+
+@endverbatim
* @{
*/
+
/**
- * @brief Writes the input buffer in data register.
- * @param pInBuffer Pointer to input buffer
- * @param Size The size of input buffer
- * @retval None
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
*/
-static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t buffercounter;
- uint32_t inputaddr = (uint32_t) pInBuffer;
-
- for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Provides the message digest result.
- * @param pMsgDigest Pointer to the message digest
- * @param Size The size of the message digest in bytes
- * @retval None
+ * @brief If not already done, initialize the HASH peripheral in SHA224 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA224_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
*/
-static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t msgdigest = (uint32_t)pMsgDigest;
-
- switch(Size)
- {
- case 16U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- break;
- case 20U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- break;
- case 28U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
- break;
- case 32U:
- /* Read the message digest */
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6U]);
- msgdigest+=4U;
- *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7U]);
- break;
- default:
- break;
- }
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief DMA HASH Input Data complete callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value
+ * @retval HAL status
*/
-static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t inputaddr = 0U;
- uint32_t buffersize = 0U;
-
- if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- else
- {
- /* Increment Interrupt counter */
- hhash->HashInCount++;
- /* Disable the DMA transfer before starting the next transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- if(hhash->HashInCount <= 2U)
- {
- /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
- if(hhash->HashInCount == 1U)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- buffersize = hhash->HashBuffSize;
- }
- /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
- else if(hhash->HashInCount == 2U)
- {
- inputaddr = (uint32_t)hhash->Init.pKey;
- buffersize = hhash->Init.KeySize;
- }
- /* Configure the number of valid bits in last word of the message */
- MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
-
- /* Set the HASH DMA transfer complete */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
- }
- else
- {
- /* Disable the DMA transfer */
- HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-
- /* Reset the InCount */
- hhash->HashInCount = 0U;
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
+ return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
- * @brief DMA HASH communication error callback.
- * @param hdma DMA handle
- * @retval None
+ * @brief If not already done, initialize the HASH peripheral in SHA256 mode then
+ * processes pInBuffer.
+ * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed
+ * several input buffers back-to-back to the IP that will yield a single
+ * HASH signature once all buffers have been entered. Wrap-up of input
+ * buffers feeding and retrieval of digest is done by a call to
+ * HAL_HASHEx_SHA256_Start().
+ * @note Field hhash->Phase of HASH handle is tested to check whether or not
+ * the IP has already been initialized.
+ * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start()
+ * to read it, feeding at the same time the last input buffer to the IP.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able
+ * to manage the ending buffer with a length in bytes not a multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes, must be a multiple of 4.
+ * @retval HAL status
*/
-static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hhash->State= HAL_HASH_STATE_READY;
- HAL_HASH_ErrorCallback(hhash);
+ return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
}
- /**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HASHEx_Exported_Functions
- * @{
+/**
+ * @}
*/
-/** @defgroup HASHEx_Group1 HASH processing functions
- * @brief processing functions using polling mode
+/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
+ * @brief HASH extended processing functions using interrupt mode.
*
@verbatim
===============================================================================
- ##### HASH processing using polling mode functions #####
+ ##### Interruption mode HASH extended processing functions #####
===============================================================================
- [..] This section provides functions allowing to calculate in polling mode
+ [..] This section provides functions allowing to calculate in interrupt mode
the hash value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_IT()
(+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_IT()
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout Specify Timeout value
+ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout Specify Timeout value
+ * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
+ * read the computed digest in interruption mode.
+ * @note Digest is available in pOutBuffer.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+}
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+/**
+ * @}
+ */
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
+/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
+ * @brief HASH extended processing functions using DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA mode HASH extended processing functionss #####
+ ===============================================================================
+ [..] This section provides functions allowing to calculate in DMA mode
+ the hash value using one of the following algorithms:
+ (+) SHA224
+ (++) HAL_HASHEx_SHA224_Start_DMA()
+ (++) HAL_HASHEx_SHA224_Finish()
+ (+) SHA256
+ (++) HAL_HASHEx_SHA256_Start_DMA()
+ (++) HAL_HASHEx_SHA256_Finish()
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
+ [..] When resorting to DMA mode to enter the data in the IP, user must resort
+ to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
+ HAL_HASHEx_xxx_Finish().
- /* Get tick */
- tickstart = HAL_GetTick();
+ [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
+ the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
+ reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
+ retrieved thanks to HAL_HASHEx_xxx_Finish().
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
+@endverbatim
+ * @{
+ */
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32U);
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
-
/**
- * @brief Initializes the HASH peripheral in SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Return the computed digest in SHA224 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA224 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
}
-
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
+ * to feed the input buffer to the IP.
+ * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
+ * be called to retrieve the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
+/**
+ * @brief Return the computed digest in SHA256 mode.
+ * @note The API waits for DCIS to be set then reads the computed digest.
+ * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
+ * HMAC SHA256 mode.
+ * @param hhash: HASH handle.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
+ return HASH_Finish(hhash, pOutBuffer, Timeout);
+}
/**
* @}
*/
-/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
- * @brief HMAC processing functions using polling mode .
+/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
+ * @brief HMAC extended processing functions using polling mode.
*
@verbatim
===============================================================================
- ##### HMAC processing using polling mode functions #####
+ ##### Polling mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start()
@endverbatim
* @{
*/
+
+
/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout Timeout value
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @param Timeout: Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /************************** STEP 1 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 2 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(pInBuffer, Size);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /************************** STEP 3 ******************************************/
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Write input buffer in data register */
- HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((HAL_GetTick() - tickstart ) > Timeout)
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32U);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
-/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
- * @brief processing functions using interrupt mode.
+
+/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
+ * @brief HMAC extended processing functions using interruption mode.
*
@verbatim
===============================================================================
- ##### HASH processing using interrupt functions #####
+ ##### Interrupt mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
- the hash value using one of the following algorithms:
+ the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_IT()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_IT()
@endverbatim
* @{
*/
-/**
- * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
-{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA224;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
- /* Reset interrupt counter */
- hhash->HashITCounter = 0U;
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28U);
- if(hhash->HashInCount == 0U)
- {
- /* Disable Interrupts */
- HASH->IMR = 0U;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68U)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- if(hhash->HashITCounter == 0U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68U)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
- }
- else
- {
- hhash->HashInCount = 0U;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1U;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4U) && (inputcounter%4U))
- {
- inputcounter = (inputcounter+4U-inputcounter%4U);
- }
- else if ((inputcounter < 4U) && (inputcounter != 0U))
- {
- inputcounter = 4U;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0U;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
-}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
- * The digest is available in pOutBuffer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- uint32_t inputaddr;
- uint32_t buffercounter;
- uint32_t inputcounter;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- if(hhash->State == HAL_HASH_STATE_READY)
- {
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- hhash->HashInCount = Size;
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->pHashOutBuffPtr = pOutBuffer;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA256 mode */
- HASH->CR |= HASH_ALGOSELECTION_SHA256;
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
- }
- /* Reset interrupt counter */
- hhash->HashITCounter = 0U;
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Enable Interrupts */
- HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-
- /* Return function status */
- return HAL_OK;
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
- {
- /* Read the message digest */
- HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32U);
- if(hhash->HashInCount == 0U)
- {
- /* Disable Interrupts */
- HASH->IMR = 0U;
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_READY;
- /* Call digest computation complete callback */
- HAL_HASH_DgstCpltCallback(hhash);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
- }
- }
- if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
- {
- if(hhash->HashInCount >= 68U)
- {
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- if(hhash->HashITCounter == 0U)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
-
- if(hhash->HashInCount >= 68U)
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 68U;
- hhash->pHashInBuffPtr+= 68U;
- }
- else
- {
- hhash->HashInCount = 0U;
- hhash->pHashInBuffPtr+= hhash->HashInCount;
- }
- /* Set Interrupt counter */
- hhash->HashITCounter = 1U;
- }
- else
- {
- /* Decrement buffer counter */
- hhash->HashInCount -= 64U;
- hhash->pHashInBuffPtr+= 64U;
- }
- }
- else
- {
- /* Get the buffer address */
- inputaddr = (uint32_t)hhash->pHashInBuffPtr;
- /* Get the buffer counter */
- inputcounter = hhash->HashInCount;
- /* Disable Interrupts */
- HASH->IMR &= ~(HASH_IT_DINI);
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-
- if((inputcounter > 4U) && (inputcounter%4U))
- {
- inputcounter = (inputcounter+4U-inputcounter%4U);
- }
- else if ((inputcounter < 4U) && (inputcounter != 0U))
- {
- inputcounter = 4U;
- }
- /* Write the Input block in the Data IN register */
- for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
- {
- HASH->DIN = *(uint32_t*)inputaddr;
- inputaddr+=4U;
- }
- /* Start the digest calculation */
- __HAL_HASH_START_DIGEST();
- /* Reset buffer counter */
- hhash->HashInCount = 0U;
- /* Call Input data transfer complete callback */
- HAL_HASH_InCpltCallback(hhash);
- }
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief This function handles HASH interrupt request.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @retval None
+ * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
+ * read the computed digest in interrupt mode.
+ * @note Digest is available in pOutBuffer.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes.
+ * @retval HAL status
*/
-void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
{
- switch(HASH->CR & HASH_CR_ALGO)
- {
+ return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
+}
- case HASH_ALGOSELECTION_SHA224:
- HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0U, NULL);
- break;
- case HASH_ALGOSELECTION_SHA256:
- HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0U, NULL);
- break;
- default:
- break;
- }
-}
/**
* @}
*/
-/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
- * @brief processing functions using DMA mode.
+
+/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions using DMA mode.
*
@verbatim
===============================================================================
- ##### HASH processing using DMA functions #####
+ ##### DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
- the hash value using one of the following algorithms:
+ the HMAC value using one of the following algorithms:
(+) SHA224
+ (++) HAL_HMACEx_SHA224_Start_DMA()
(+) SHA256
+ (++) HAL_HMACEx_SHA256_Start_DMA()
+
+ [..] When resorting to DMA mode to enter the data in the IP for HMAC processing,
+ user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
+ with HAL_HASHEx_xxx_Finish().
+
@endverbatim
* @{
*/
+
/**
- * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
- /* Process Locked */
- __HAL_LOCK(hhash);
+/**
+ * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
+ * DMA transfers to feed the key and the input buffer to the IP.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note If MDMAT bit is set before calling this function (multi-buffer
+ * HASH processing case), the input buffer size (in bytes) must be
+ * a multiple of 4 otherwise, the HASH digest computation is corrupted.
+ * For the processing of the last buffer of the thread, MDMAT bit must
+ * be reset and the buffer length (in bytes) doesn't have to be a
+ * multiple of 4.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (buffer to be hashed).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
- {
- /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;
- }
+/**
+ * @}
+ */
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
+/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
+ * @brief HMAC extended processing functions in multi-buffer DMA mode.
+ *
+@verbatim
+ ===============================================================================
+ ##### Multi-buffer DMA mode HMAC extended processing functions #####
+ ===============================================================================
+ [..] This section provides functions to manage HMAC multi-buffer
+ DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
+ (+) MD5
+ (++) HAL_HMACEx_MD5_Step1_2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_DMA()
+ (++) HAL_HMACEx_MD5_Step2_3_DMA()
+ (+) SHA1
+ (++) HAL_HMACEx_SHA1_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_DMA()
+ (++) HAL_HMACEx_SHA1_Step2_3_DMA()
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
+ (+) SHA256
+ (++) HAL_HMACEx_SHA224_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_DMA()
+ (++) HAL_HMACEx_SHA224_Step2_3_DMA()
+ (+) SHA256
+ (++) HAL_HMACEx_SHA256_Step1_2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_DMA()
+ (++) HAL_HMACEx_SHA256_Step2_3_DMA()
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
+ [..] User must first start-up the multi-buffer DMA-based HMAC computation in
+ calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+ intiates step 2 with the first input buffer.
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
+ [..] The following buffers are next fed to the IP with a call to the API
+ HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
+ to this API.
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
+ [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
+ HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
+ buffer to the IP then carries out step 3.
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
+ [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
+ SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
- /* Return function status */
- return HAL_OK;
-}
+ [..] If only two buffers need to be consecutively processed, a call to
+ HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
+ is sufficient.
+
+@endverbatim
+ * @{
+ */
/**
- * @brief Returns the computed digest in SHA224
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout Timeout value
+ * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 28U);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
- * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
- control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief MD5 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr = (uint32_t)pInBuffer;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;
+ return HAL_ERROR;
}
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(Size);
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
-
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process UnLock */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
- * @brief Returns the computed digest in SHA256.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout Timeout value
+ * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t tickstart = 0U;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_BUSY;
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
- while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
+/**
+ * @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Change state */
- hhash->State = HAL_HASH_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- return HAL_TIMEOUT;
- }
- }
+ return HAL_ERROR;
}
-
- /* Read the message digest */
- HASHEx_GetDigest(pOutBuffer, 32U);
-
- /* Change HASH peripheral state */
- hhash->State = HAL_HASH_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
-
/**
- * @}
+ * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
*/
-/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
- * @brief HMAC processing functions using DMA mode .
- *
-@verbatim
- ===============================================================================
- ##### HMAC processing using DMA functions #####
- ===============================================================================
- [..] This section provides functions allowing to calculate in DMA mode
- the HMAC value using one of the following algorithms:
- (+) SHA224
- (+) SHA256
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
-@endverbatim
- * @{
+/**
+ * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA224 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
-
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0U;
-
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
- }
- else
- {
- /* Select the HMAC SHA224 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
- }
+ return HAL_ERROR;
}
-
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
- * @brief Initializes the HASH peripheral in HMAC SHA256 mode
- * then enables DMA to control data transfer.
- * @param hhash pointer to a HASH_HandleTypeDef structure that contains
- * the configuration information for HASH module
- * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
- * @param Size Length of the input buffer in bytes.
- * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+ * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
- uint32_t inputaddr;
-
- /* Process Locked */
- __HAL_LOCK(hhash);
-
- /* Change the HASH state */
- hhash->State = HAL_HASH_STATE_BUSY;
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
+}
- /* Save buffer pointer and size in handle */
- hhash->pHashInBuffPtr = pInBuffer;
- hhash->HashBuffSize = Size;
- hhash->HashInCount = 0U;
+/**
+ * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
+ * @note Step 1 consists in writing the inner hash function key in the IP,
+ * step 2 consists in writing the message text.
+ * @note The API carries out the HMAC step 1 then starts step 2 with
+ * the first buffer entered to the IP. DCAL bit is not automatically set after
+ * the message buffer feeding, allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = SET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Check if initialization phase has already been performed */
- if(hhash->Phase == HAL_HASH_PHASE_READY)
+/**
+ * @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP.
+ * @note The API carries on the HMAC step 2, applied to the buffer entered as input
+ * parameter. DCAL bit is not automatically set after the message buffer feeding,
+ * allowing other messages DMA transfers to occur.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+ * HASH digest computation is corrupted.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ if (hhash->DigestCalculationDisable != SET)
{
- /* Check if key size is greater than 64 bytes */
- if(hhash->Init.KeySize > 64U)
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);
- }
- else
- {
- /* Select the HMAC SHA256 mode */
- HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);
- }
- /* Reset the HASH processor core, so that the HASH will be ready to compute
- the message digest of a new message */
- HASH->CR |= HASH_CR_INIT;
+ return HAL_ERROR;
}
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
+}
- /* Set the phase */
- hhash->Phase = HAL_HASH_PHASE_PROCESS;
-
- /* Configure the number of valid bits in last word of the message */
- __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
- /* Get the key address */
- inputaddr = (uint32_t)(hhash->Init.pKey);
-
- /* Set the HASH DMA transfer complete callback */
- hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
- /* Set the DMA error callback */
- hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
-
- /* Enable the DMA In DMA Stream */
- HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
- /* Enable DMA requests */
- HASH->CR |= (HASH_CR_DMAE);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hhash);
-
- /* Return function status */
- return HAL_OK;
+/**
+ * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
+ * @note Step 2 consists in writing the message text in the IP,
+ * step 3 consists in writing the outer hash function key.
+ * @note The API wraps up the HMAC step 2 in processing the buffer entered as input
+ * parameter (the input buffer must be the last one of the multi-buffer thread)
+ * then carries out HMAC step 3.
+ * @note Same key is used for the inner and the outer hash functions; pointer to key and
+ * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+ * @note Once the DMA transfers are finished (indicated by hhash->State set back
+ * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
+ * the computed digest.
+ * @param hhash: HASH handle.
+ * @param pInBuffer: pointer to the input buffer (message buffer).
+ * @param Size: length of the input buffer in bytes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+ hhash->DigestCalculationDisable = RESET;
+ return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
+#endif /* MDMA defined*/
/**
* @}
*/
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-
#endif /* HAL_HASH_MODULE_ENABLED */
+
/**
* @}
*/
-
+#endif /* HASH*/
/**
* @}
*/
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hcd.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hcd.c
index 3d48b0cf80e53eb175f9867ca36df7d224c0ba1e..6d90fdcdd3d3d051511cbb32011a7462e73fb7c0 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hcd.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_hcd.c
@@ -42,29 +42,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -76,17 +60,15 @@
* @{
*/
+#ifdef HAL_HCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
-#ifdef HAL_HCD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -128,8 +110,10 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
+ USB_OTG_GlobalTypeDef *USBx;
+
/* Check the HCD handle allocation */
- if(hhcd == NULL)
+ if (hhcd == NULL)
{
return HAL_ERROR;
}
@@ -137,24 +121,55 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
+ USBx = hhcd->Instance;
+
+ if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hhcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+ if (hhcd->MspInitCallback == NULL)
+ {
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hhcd->MspInitCallback(hhcd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
+ }
+
hhcd->State = HAL_HCD_STATE_BUSY;
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_HCD_MspInit(hhcd);
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hhcd->Init.dma_enable = 0U;
+ }
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- USB_CoreInit(hhcd->Instance, hhcd->Init);
+ (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
/* Force Host Mode*/
- USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
+ (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
/* Init Host */
- USB_HostInit(hhcd->Instance, hhcd->Init);
+ (void)USB_HostInit(hhcd->Instance, hhcd->Init);
- hhcd->State= HAL_HCD_STATE_READY;
+ hhcd->State = HAL_HCD_STATE_READY;
return HAL_OK;
}
@@ -166,7 +181,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
* This parameter can be a value from 1 to 15
* @param epnum Endpoint number.
* This parameter can be a value from 1 to 15
- * @param dev_address Current device address
+ * @param dev_address Current device address
* This parameter can be a value from 0 to 255
* @param speed Current device speed.
* This parameter can be one of these values:
@@ -191,16 +206,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ep_type,
uint16_t mps)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
__HAL_LOCK(hhcd);
-
+ hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
- hhcd->hc[ch_num].ep_num = epnum & 0x7F;
- hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+ hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ hhcd->hc[ch_num].ep_is_in = 1U;
+ }
+ else
+ {
+ hhcd->hc[ch_num].ep_is_in = 0U;
+ }
+
hhcd->hc[ch_num].speed = speed;
status = USB_HC_Init(hhcd->Instance,
@@ -227,7 +251,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hhcd);
- USB_HC_Halt(hhcd->Instance, ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_UNLOCK(hhcd);
return status;
@@ -241,15 +265,25 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
- if(hhcd == NULL)
+ if (hhcd == NULL)
{
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_BUSY;
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ if (hhcd->MspDeInitCallback == NULL)
+ {
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
/* DeInit the low level hardware */
+ hhcd->MspDeInitCallback(hhcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_HCD_MspDeInit(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_DISABLE(hhcd);
@@ -267,8 +301,9 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_MspInit could be implemented in the user file
*/
}
@@ -281,8 +316,9 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_MspDeInit could be implemented in the user file
*/
}
@@ -333,14 +369,16 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t direction,
uint8_t ep_type,
uint8_t token,
- uint8_t* pbuff,
+ uint8_t *pbuff,
uint16_t length,
uint8_t do_ping)
{
+ UNUSED(do_ping);
+
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
- if(token == 0)
+ if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
}
@@ -350,101 +388,103 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
}
/* Manage Data Toggle */
- switch(ep_type)
+ switch (ep_type)
{
- case EP_TYPE_CTRL:
- if((token == 1) && (direction == 0)) /*send data */
- {
- if (length == 0)
- { /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1;
- }
-
- /* Set the Data Toggle bit as per the Flag */
- if (hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
+ case EP_TYPE_CTRL:
+ if ((token == 1U) && (direction == 0U)) /*send data */
{
- hhcd->hc[ch_num].do_ping = do_ping;
- }
- }
- break;
+ if (length == 0U)
+ {
+ /* For Status OUT stage, Length==0, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1U;
+ }
- case EP_TYPE_BULK:
- if(direction == 0)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0)
+ break;
+
+ case EP_TYPE_BULK:
+ if (direction == 0U)
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
else
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- break;
- case EP_TYPE_INTR:
- if(direction == 0)
- {
- /* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
- { /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- }
- else
- { /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
- }
- }
- else
- {
- if( hhcd->hc[ch_num].toggle_in == 0)
+ break;
+ case EP_TYPE_INTR:
+ if (direction == 0U)
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
else
{
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
- }
- break;
+ break;
- case EP_TYPE_ISOC:
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
+ case EP_TYPE_ISOC:
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ break;
+
+ default:
+ break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0;
+ hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
- return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
+ return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
}
/**
@@ -455,83 +495,94 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t i = 0U , interrupt = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i, interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
/* Avoid spurious interrupt */
- if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle Host Disconnect Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
/* Cleanup HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
- /* Handle Host Port Interrupts */
+ /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->DisconnectCallback(hhcd);
+#else
HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
/* Handle Host Port Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
{
- HCD_Port_IRQHandler (hhcd);
+ HCD_Port_IRQHandler(hhcd);
}
- /* Handle Host SOF Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+ /* Handle Host SOF Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
{
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->SOFCallback(hhcd);
+#else
HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
- /* Handle Host channel Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+ /* Handle Host channel Interrupt */
+ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
for (i = 0U; i < hhcd->Init.Host_channels; i++)
{
- if (interrupt & (1U << i))
+ if ((interrupt & (1UL << (i & 0xFU))) != 0U)
{
- if ((USBx_HC(i)->HCCHAR) & USB_OTG_HCCHAR_EPDIR)
+ if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
{
- HCD_HC_IN_IRQHandler(hhcd, i);
+ HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
}
else
{
- HCD_HC_OUT_IRQHandler (hhcd, i);
+ HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
}
}
}
@@ -539,11 +590,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
}
/* Handle Rx Queue Level Interrupts */
- if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- HCD_RXQLVL_IRQHandler (hhcd);
+ HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
@@ -559,7 +610,8 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
@@ -573,7 +625,8 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
@@ -587,7 +640,38 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Port Enabled Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Port Disabled Event callback.
+ * @param hhcd HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
@@ -613,11 +697,288 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
UNUSED(hhcd);
UNUSED(chnum);
UNUSED(urb_state);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
}
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB HCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB HCD Callback
+ * USB HCD callabck is redirected to the weak predefined callback
+ * @param hhcd USB HCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+ * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+ * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+ * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+ * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+ * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_SOF_CB_ID :
+ hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+ break;
+
+ case HAL_HCD_CONNECT_CB_ID :
+ hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+ break;
+
+ case HAL_HCD_DISCONNECT_CB_ID :
+ hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+ break;
+
+ case HAL_HCD_PORT_ENABLED_CB_ID :
+ hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+ break;
+
+ case HAL_HCD_PORT_DISABLED_CB_ID :
+ hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+ break;
+
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hhcd->State == HAL_HCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_HCD_MSPINIT_CB_ID :
+ hhcd->MspInitCallback = HAL_HCD_MspInit;
+ break;
+
+ case HAL_HCD_MSPDEINIT_CB_ID :
+ hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+ return status;
+}
+
+/**
+ * @brief Register USB HCD Host Channel Notify URB Change Callback
+ * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback
+ * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+ * @param hhcd HCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hhcd);
+
+ if (hhcd->State == HAL_HCD_STATE_READY)
+ {
+ hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hhcd);
+
+ return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -646,7 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
__HAL_HCD_ENABLE(hhcd);
- USB_DriveVbus(hhcd->Instance, 1U);
+ (void)USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@@ -660,7 +1021,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
- USB_StopHost(hhcd->Instance);
+ (void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@@ -794,144 +1155,174 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
- * @retval None
+ * @retval none
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)chnum;
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ uint32_t tmpreg;
+
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].state = HC_STALL;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].state = HC_STALL;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- hhcd->hc[chnum].state = HC_DATATGLERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
}
-
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ else
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ /* ... */
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
-
- if (hhcd->Init.dma_enable)
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+ {
+ if (hhcd->Init.dma_enable != 0U)
{
- hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
- (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+ hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
+ (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
- hhcd->hc[chnum].state = HC_XFRC;
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+ hhcd->hc[ch_num].state = HC_XFRC;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
-
- if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
- else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
- USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
- hhcd->hc[chnum].urb_state = URB_DONE;
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
- hhcd->hc[chnum].toggle_in ^= 1U;
+ else
+ {
+ /* ... */
+ }
+ hhcd->hc[ch_num].toggle_in ^= 1U;
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
+ __HAL_HCD_MASK_HALT_HC_INT(ch_num);
- if(hhcd->hc[chnum].state == HC_XFRC)
+ if (hhcd->hc[ch_num].state == HC_XFRC)
{
- hhcd->hc[chnum].urb_state = URB_DONE;
+ hhcd->hc[ch_num].urb_state = URB_DONE;
}
-
- else if (hhcd->hc[chnum].state == HC_STALL)
+ else if (hhcd->hc[ch_num].state == HC_STALL)
{
- hhcd->hc[chnum].urb_state = URB_STALL;
+ hhcd->hc[ch_num].urb_state = URB_STALL;
}
-
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
+ else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
{
- if(hhcd->hc[chnum].ErrCnt++ > 3U)
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 3U)
{
- hhcd->hc[chnum].ErrCnt = 0U;
- hhcd->hc[chnum].urb_state = URB_ERROR;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
/* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
+ else if (hhcd->hc[ch_num].state == HC_NAK)
+ {
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
}
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ else
+ {
+ /* ... */
+ }
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ hhcd->hc[ch_num].ErrCnt++;
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
- if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
+ else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+ {
+ hhcd->hc[ch_num].ErrCnt = 0U;
- /* Clear the NAK flag before re-enabling the channel for new IN request */
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-
- if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ if (hhcd->Init.dma_enable == 0U)
+ {
+ hhcd->hc[ch_num].state = HC_NAK;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ }
+ }
+ else
{
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
+ /* ... */
}
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ }
+ else
+ {
+ /* ... */
}
}
@@ -940,189 +1331,204 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
- * @retval None
+ * @retval none
*/
-static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)chnum;
+ uint32_t tmpreg;
- if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
+ if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
}
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
- if( hhcd->hc[chnum].do_ping == 1U)
+ if (hhcd->hc[ch_num].do_ping == 1U)
{
- hhcd->hc[chnum].state = HC_NYET;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[ch_num].do_ping = 0U;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
- hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt= 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
-
+ hhcd->hc[ch_num].state = HC_NYET;
+ hhcd->hc[ch_num].do_ping = 1U;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
- hhcd->hc[chnum].state = HC_XFRC;
-
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+ hhcd->hc[ch_num].state = HC_XFRC;
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_STALL;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ hhcd->hc[ch_num].state = HC_STALL;
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
- hhcd->hc[chnum].ErrCnt = 0U;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_NAK;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- }
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].state = HC_NAK;
+
+ if (hhcd->hc[ch_num].do_ping == 0U)
+ {
+ if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
+ {
+ hhcd->hc[ch_num].do_ping = 1U;
+ }
+ }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ }
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_XACTERR;
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ hhcd->hc[ch_num].state = HC_XACTERR;
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- hhcd->hc[chnum].state = HC_DATATGLERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+ (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+ hhcd->hc[ch_num].state = HC_DATATGLERR;
}
-
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
+ else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
+ __HAL_HCD_MASK_HALT_HC_INT(ch_num);
- if(hhcd->hc[chnum].state == HC_XFRC)
+ if (hhcd->hc[ch_num].state == HC_XFRC)
{
- hhcd->hc[chnum].urb_state = URB_DONE;
- if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+ hhcd->hc[ch_num].urb_state = URB_DONE;
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
- hhcd->hc[chnum].toggle_out ^= 1U;
+ hhcd->hc[ch_num].toggle_out ^= 1U;
}
}
- else if (hhcd->hc[chnum].state == HC_NAK)
+ else if (hhcd->hc[ch_num].state == HC_NAK)
{
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
-
- else if (hhcd->hc[chnum].state == HC_NYET)
+ else if (hhcd->hc[ch_num].state == HC_NYET)
{
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- hhcd->hc[chnum].do_ping = 0U;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
-
- else if (hhcd->hc[chnum].state == HC_STALL)
+ else if (hhcd->hc[ch_num].state == HC_STALL)
{
- hhcd->hc[chnum].urb_state = URB_STALL;
+ hhcd->hc[ch_num].urb_state = URB_STALL;
}
-
- else if((hhcd->hc[chnum].state == HC_XACTERR) ||
- (hhcd->hc[chnum].state == HC_DATATGLERR))
+ else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+ (hhcd->hc[ch_num].state == HC_DATATGLERR))
{
- if(hhcd->hc[chnum].ErrCnt++ > 3U)
+ hhcd->hc[ch_num].ErrCnt++;
+ if (hhcd->hc[ch_num].ErrCnt > 3U)
{
- hhcd->hc[chnum].ErrCnt = 0U;
- hhcd->hc[chnum].urb_state = URB_ERROR;
+ hhcd->hc[ch_num].ErrCnt = 0U;
+ hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
+
+ /* re-activate the channel */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ }
+ else
+ {
+ /* ... */
}
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+ }
+ else
+ {
+ /* ... */
}
}
/**
* @brief Handle Rx Queue Level interrupt requests.
* @param hhcd HCD handle
- * @retval None
+ * @retval none
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum = 0;
+ uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
- uint32_t temp = 0U;
- uint32_t tmpreg = 0U;
+ uint32_t temp;
+ uint32_t tmpreg;
+ uint32_t ch_num;
temp = hhcd->Instance->GRXSTSP;
- channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
- pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U;
- pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
switch (pktsts)
{
- case GRXSTS_PKTSTS_IN:
- /* Read the data into the host buffer. */
- if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
- {
-
- USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
+ case GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
+ {
+ (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
- /*manage multiple Xfer */
- hhcd->hc[channelnum].xfer_buff += pktcnt;
- hhcd->hc[channelnum].xfer_count += pktcnt;
+ /*manage multiple Xfer */
+ hhcd->hc[ch_num].xfer_buff += pktcnt;
+ hhcd->hc[ch_num].xfer_count += pktcnt;
- if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
- {
- /* re-activate the channel when more packets are expected */
- tmpreg = USBx_HC(channelnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(channelnum)->HCCHAR = tmpreg;
- hhcd->hc[channelnum].toggle_in ^= 1;
+ if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
+ {
+ /* re-activate the channel when more packets are expected */
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
+ hhcd->hc[ch_num].toggle_in ^= 1U;
+ }
}
- }
- break;
-
- case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
- break;
- case GRXSTS_PKTSTS_IN_XFER_COMP:
- case GRXSTS_PKTSTS_CH_HALTED:
- default:
- break;
+ break;
+
+ case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ break;
+
+ case GRXSTS_PKTSTS_IN_XFER_COMP:
+ case GRXSTS_PKTSTS_CH_HALTED:
+ default:
+ break;
}
}
@@ -1131,70 +1537,87 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
* @param hhcd HCD handle
* @retval None
*/
-static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0, hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
hprt0_dup = USBx_HPRT0;
- hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
- /* Check whether Port Connect Detected */
- if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+ /* Check whether Port Connect detected */
+ if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
{
- if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+ if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->ConnectCallback(hhcd);
+#else
HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
-
}
/* Check whether Port Enable Changed */
- if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+ if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
- if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+ if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
- if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
+ if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
- if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
}
else
{
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
else
{
- if(hhcd->Init.speed == HCD_SPEED_FULL)
+ if (hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = 60000U;
}
}
-
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortEnabledCallback(hhcd);
+ hhcd->ConnectCallback(hhcd);
+#else
+ HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
}
else
{
- /* Clean up HPRT */
- USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+ hhcd->PortDisabledCallback(hhcd);
+#else
+ HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+ /* Cleanup HPRT */
+ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}
- /* Check for an over current */
- if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+ /* Check for an overcurrent */
+ if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
}
@@ -1206,10 +1629,14 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || defined(STM32F413xx) || defined(STM32F423xx) */
+
+/**
+ * @}
+ */
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_HCD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c.c
index 9d8e327ce8e01ad3d3af85a1fd7854b2e6835168..38d555cb6f3454d58373a9f0edd8990bac642931 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c.c
@@ -19,7 +19,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -31,154 +31,174 @@
(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream
+ (+++) Configure the DMA Tx or Rx stream
(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx Stream
+ the DMA Tx or Rx stream
(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
-
- *** Interrupt mode IO sequential operation ***
- ==============================================
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+ (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+ or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+ or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** Interrupt mode IO MEM operation ***
=======================================
[..]
- (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ @ref HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ @ref HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ @ref HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
*** DMA mode IO MEM operation ***
=================================
[..]
- (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ @ref HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ @ref HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -186,44 +206,94 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
+ (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+
+ Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+
+ By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+ or @ref HAL_I2C_Init() function.
+
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
-
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -252,12 +322,12 @@
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
/**
* @}
@@ -266,7 +336,8 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions to handle DMA transfer */
@@ -280,6 +351,8 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
@@ -289,26 +362,30 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
/* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
+
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
@@ -321,7 +398,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialize the I2Cx peripheral:
+ deinitialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
@@ -346,18 +423,18 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
/**
* @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
- uint32_t freqrange = 0U;
- uint32_t pclk1 = 0U;
+ uint32_t freqrange;
+ uint32_t pclk1;
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -373,12 +450,35 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
- if(hi2c->State == HAL_I2C_STATE_RESET)
+ if (hi2c->State == HAL_I2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ /* Init the I2C Callback settings */
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hi2c->MspInitCallback == NULL)
+ {
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ hi2c->MspInitCallback(hi2c);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
@@ -389,32 +489,38 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
+ /* Check the minimum allowed PCLK1 frequency */
+ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
+ {
+ return HAL_ERROR;
+ }
+
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
- hi2c->Instance->CR2 = freqrange;
+ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
- hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
- hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
- hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
- hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
+ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
- hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
+ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
@@ -428,15 +534,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief DeInitializes the I2C peripheral.
- * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -449,8 +555,18 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ if (hi2c->MspDeInitCallback == NULL)
+ {
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hi2c->MspDeInitCallback(hi2c);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_RESET;
@@ -464,40 +580,364 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief I2C MSP Init.
- * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * @brief Initialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
/**
- * @brief I2C MSP DeInit
- * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User I2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2C Callback
+ * I2C callback is redirected to the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match I2C Callback
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match I2C Callback
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
@@ -532,12 +972,15 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Master_Receive_IT()
(++) HAL_I2C_Slave_Transmit_IT()
(++) HAL_I2C_Slave_Receive_IT()
- (++) HAL_I2C_Master_Sequential_Transmit_IT()
- (++) HAL_I2C_Master_Sequential_Receive_IT()
- (++) HAL_I2C_Slave_Sequential_Transmit_IT()
- (++) HAL_I2C_Slave_Sequential_Receive_IT()
(++) HAL_I2C_Mem_Write_IT()
(++) HAL_I2C_Mem_Read_IT()
+ (++) HAL_I2C_Master_Seq_Transmit_IT()
+ (++) HAL_I2C_Master_Seq_Receive_IT()
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()
+ (++) HAL_I2C_Slave_Seq_Receive_IT()
+ (++) HAL_I2C_EnableListen_IT()
+ (++) HAL_I2C_DisableListen_IT()
+ (++) HAL_I2C_Master_Abort_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2C_Master_Transmit_DMA()
@@ -546,14 +989,20 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
(++) HAL_I2C_Slave_Receive_DMA()
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()
+ (++) HAL_I2C_Master_Seq_Receive_DMA()
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
(++) HAL_I2C_MasterRxCpltCallback()
(++) HAL_I2C_SlaveTxCpltCallback()
(++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_AddrCallback()
+ (++) HAL_I2C_ListenCpltCallback()
(++) HAL_I2C_ErrorCallback()
(++) HAL_I2C_AbortCpltCallback()
@@ -565,7 +1014,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -574,15 +1023,13 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0x00U;
-
/* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
@@ -591,93 +1038,84 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
/* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+ if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(hi2c->XferSize > 0U)
+ while (hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
hi2c->XferSize--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
hi2c->XferSize--;
}
/* Wait until BTF flag is set */
- if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
}
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -697,7 +1135,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -706,15 +1144,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0x00U;
-
/* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
@@ -723,14 +1159,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
@@ -739,52 +1175,41 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
/* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
+ if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
- if(hi2c->XferSize == 0U)
+ if (hi2c->XferSize == 0U)
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
- else if(hi2c->XferSize == 1U)
+ else if (hi2c->XferSize == 1U)
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
- else if(hi2c->XferSize == 2U)
+ else if (hi2c->XferSize == 2U)
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -792,56 +1217,64 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
else
{
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(hi2c->XferSize > 0U)
+ while (hi2c->XferSize > 0U)
{
- if(hi2c->XferSize <= 3U)
+ if (hi2c->XferSize <= 3U)
{
/* One byte */
- if(hi2c->XferSize == 1U)
+ if (hi2c->XferSize == 1U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
}
/* Two bytes */
- else if(hi2c->XferSize == 2U)
+ else if (hi2c->XferSize == 2U)
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
}
@@ -849,35 +1282,50 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
else
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
}
@@ -885,27 +1333,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
else
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
}
@@ -937,14 +1388,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0x00U;
-
/* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -953,14 +1402,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
@@ -969,77 +1418,80 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
/* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* If 10bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(hi2c->XferSize > 0U)
+ while (hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
hi2c->XferSize--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
hi2c->XferSize--;
}
}
/* Wait until AF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -1066,30 +1518,28 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0x00U;
-
/* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == (uint16_t)0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
@@ -1098,74 +1548,70 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
/* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(hi2c->XferSize > 0U)
+ while (hi2c->XferSize > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferSize--;
hi2c->XferCount--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
__HAL_I2C_CLEAR_STOPFLAG(hi2c);
/* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -1185,7 +1631,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1195,37 +1641,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
{
__IO uint32_t count = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
- if(count-- == 0U)
+ count--;
+ if (count == 0U)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
@@ -1234,12 +1683,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->Devaddress = DevAddress;
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1262,7 +1711,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -1272,37 +1721,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
{
__IO uint32_t count = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
- if(count-- == 0U)
+ count--;
+ if (count == 0U)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
@@ -1311,15 +1763,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->Devaddress = DevAddress;
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1340,96 +1792,55 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
}
/**
- * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- __IO uint32_t Prev_State = 0x00U;
- __IO uint32_t count = 0x00U;
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
-
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- /* Check Busy Flag only if FIRST call of Master interface */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ if ((pData == NULL) || (Size == 0U))
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- Prev_State = hi2c->PreviousState;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Generate Start */
- if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
- {
- /* Generate Start condition if first transfer */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else
- {
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- }
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1443,98 +1854,55 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
}
/**
- * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- __IO uint32_t count = 0U;
-
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- /* Check Busy Flag only if FIRST call of Master interface */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ if ((pData == NULL) || (Size == 0U))
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
- {
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
- {
- /* Generate Start condition if first transfer */
- if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
-
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
- {
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
- }
- }
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1548,76 +1916,137 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
__IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
- if(count-- == 0U)
+ count--;
+ if (count == 0U)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ if (hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
return HAL_OK;
}
@@ -1628,142 +2057,137 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
__IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
- if(count-- == 0U)
+ count--;
+ if (count == 0U)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ if (hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-/**
- * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
- {
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
- hi2c->XferSize = hi2c->XferCount;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
return HAL_OK;
}
@@ -1774,23 +2198,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
}
/**
- * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
- * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
- * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- /* Check the parameters */
- assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+ HAL_StatusTypeDef dmaxferstatus;
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1799,105 +2220,73 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
+ hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = XferOptions;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
-/**
- * @brief Enable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- hi2c->State = HAL_I2C_STATE_LISTEN;
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
- /* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if (dmaxferstatus == HAL_OK)
{
- /* Enable I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
- }
-
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-/**
- * @brief Disable the Address listen mode with Interrupt.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
-{
- /* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- /* Disable Address listen mode only if a transfer is not ongoing */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
- {
- tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
- hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Disable Address Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
- /* Disable EVT and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_OK;
+ return HAL_ERROR;
+ }
}
else
{
@@ -1906,84 +2295,66 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- __IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if ((pData == NULL) || (Size == 0U))
{
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
- hi2c->Devaddress = DevAddress;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferM1CpltCallback = NULL;
- hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1991,33 +2362,28 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
-
/* Enable EVT and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ return HAL_OK;
}
else
{
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ return HAL_ERROR;
}
-
- return HAL_OK;
}
else
{
@@ -2026,265 +2392,989 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
}
/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- __IO uint32_t count = 0U;
+ /* Init tickstart for timeout management*/
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ return HAL_BUSY;
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ while (hi2c->XferSize > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ return HAL_ERROR;
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+
+ /* Wait until BTF flag is set */
+ if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ return HAL_ERROR;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ /* Init tickstart for timeout management*/
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferSize == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if (hi2c->XferSize == 1U)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if (hi2c->XferSize == 2U)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ while (hi2c->XferSize > 0U)
+ {
+ if (hi2c->XferSize <= 3U)
+ {
+ /* One byte */
+ if (hi2c->XferSize == 1U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* Two bytes */
+ else if (hi2c->XferSize == 2U)
+ {
+ /* Wait until BTF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ /* 3 Last bytes */
+ else
+ {
+ /* Wait until BTF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Wait until BTF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ else
+ {
+ /* Wait until RXNE flag is set */
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ }
+ }
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
+
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Init tickstart for timeout management*/
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
/* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
/* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferM1CpltCallback = NULL;
- hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferM1CpltCallback = NULL;
+ hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Init tickstart for timeout management*/
+ uint32_t tickstart = HAL_GetTick();
+ __IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
}
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
+ if (hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferM1CpltCallback = NULL;
+ hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hi2c->XferSize == 1U)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
+ else
+ {
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
-/**
- * @brief Abort a master I2C process communication with Interrupt.
- * @note This abort can be called only if state is ready
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address The device 7 bits address value
- * in datasheet must be shifted to the left before calling the interface
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(DevAddress);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
- /* Abort Master transfer during Receive or Transmit process */
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
- {
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_ABORT;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Send Slave Address and Memory Address */
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- hi2c->XferCount = 0U;
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Call the corresponding callback to inform upper layer of End of Transfer */
- I2C_ITError(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
return HAL_OK;
}
else
{
- /* Wrong usage of abort function */
- /* This function should be used only in case of abort monitored by master device */
- return HAL_ERROR;
+ return HAL_BUSY;
}
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param pData Pointer to data buffer
- * @param Size Amount of data to be sent
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- __IO uint32_t count = 0U;
+ /* Get tick */
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t I2C_Trials = 1U;
+ FlagStatus tmp1;
+ FlagStatus tmp2;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ return HAL_BUSY;
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferSize = hi2c->XferCount;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+ do
+ {
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Wait until SB flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferM1CpltCallback = NULL;
- hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ /* Wait until ADDR or AF flag are set */
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ hi2c->State = HAL_I2C_STATE_TIMEOUT;
+ }
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ /* Check if the ADDR flag has been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear ADDR Flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ hi2c->State = HAL_I2C_STATE_READY;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear AF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Increment Trials */
+ I2C_Trials++;
+ }
+ while (I2C_Trials < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
}
else
{
@@ -2293,93 +3383,94 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- __IO uint32_t count = 0U;
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0x00U;
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
- if(count-- == 0U)
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
+ }
}
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->Devaddress = DevAddress;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferM1CpltCallback = NULL;
- hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ Prev_State = hi2c->PreviousState;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+ {
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable EVT and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
return HAL_OK;
}
@@ -2388,130 +3479,164 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
return HAL_BUSY;
}
}
+
/**
- * @brief Write an amount of data in blocking mode to a specific memory address
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
- * @param Timeout Timeout duration
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t tickstart = 0x00U;
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0x00U;
+ HAL_StatusTypeDef dmaxferstatus;
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- /* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->Devaddress = DevAddress;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ Prev_State = hi2c->PreviousState;
- while(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ if (dmaxferstatus == HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
{
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- else
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+ /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+ if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
{
- return HAL_TIMEOUT;
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
}
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
}
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Wait until BTF flag is set */
- if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
- else
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
{
- return HAL_TIMEOUT;
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- }
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
return HAL_OK;
}
@@ -2522,231 +3647,302 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
/**
- * @brief Read an amount of data in blocking mode from a specific memory address
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
- * @param Timeout Timeout duration
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0U;
+ uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
- return HAL_BUSY;
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ count--;
+ if (count == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->Devaddress = DevAddress;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- if(hi2c->XferSize == 0U)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- else if(hi2c->XferSize == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ Prev_State = hi2c->PreviousState;
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- }
- else if(hi2c->XferSize == 2U)
+ if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
+ enableIT &= ~I2C_IT_BUF;
}
else
{
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+ {
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- while(hi2c->XferSize > 0U)
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable interrupts */
+ __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0U;
+ uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
- if(hi2c->XferSize <= 3U)
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
{
- /* One byte */
- if(hi2c->XferSize== 1U)
+ count--;
+ if (count == 0U)
{
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
- }
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
}
- /* Two bytes */
- else if(hi2c->XferSize == 2U)
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ }
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ }
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Check if the I2C is already enabled */
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- /* 3 Last bytes */
- else
- {
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ /* Clear Last DMA bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->Devaddress = DevAddress;
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ Prev_State = hi2c->PreviousState;
- /* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ if (hi2c->XferSize > 0U)
+ {
+ if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Enable Pos */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+ {
+ /* Enable Last DMA bit */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
}
}
- else
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ if (dmaxferstatus == HAL_OK)
{
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+ /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+ if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
{
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferSize--;
- hi2c->XferCount--;
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
}
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
}
}
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+ {
+ /* Generate Start */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable interrupts */
+ __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+ }
return HAL_OK;
}
else
@@ -2756,78 +3952,59 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
/**
- * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- __IO uint32_t count = 0U;
-
/* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if ((pData == NULL) || (Size == 0U))
{
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
- hi2c->Memaddress = MemAddress;
- hi2c->MemaddSize = MemAddSize;
- hi2c->EventCount = 0U;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -2841,88 +4018,155 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/**
- * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- __IO uint32_t count = 0U;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
- if(count-- == 0U)
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
- return HAL_TIMEOUT;
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->Devaddress = DevAddress;
- hi2c->Memaddress = MemAddress;
- hi2c->MemaddSize = MemAddSize;
- hi2c->EventCount = 0U;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
- /* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- if(hi2c->XferSize > 0U)
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ if (dmaxferstatus == HAL_OK)
{
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
}
- return HAL_OK;
}
else
{
@@ -2931,119 +4175,63 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
/**
- * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- __IO uint32_t count = 0U;
-
- uint32_t tickstart = 0x00U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
/* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if ((pData == NULL) || (Size == 0U))
{
- if(count-- == 0U)
- {
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferM1CpltCallback = NULL;
- hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Disable Pos */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
- }
return HAL_OK;
}
else
@@ -3053,113 +4241,123 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
/**
- * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param MemAddress Internal memory address
- * @param MemAddSize Size of internal memory address
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
- * @param Size Amount of data to be read
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t tickstart = 0x00U;
- __IO uint32_t count = 0U;
-
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
- assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
- /* Wait until BUSY flag is reset */
- count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
- do
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
- if(count-- == 0U)
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
- return HAL_TIMEOUT;
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
}
}
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
/* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
- if(hi2c->XferSize > 0U)
- {
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferM1CpltCallback = NULL;
- hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable the DMA stream */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
- if(Size == 1U)
- {
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- }
- else
- {
- /* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
- }
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -3167,47 +4365,31 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Enable DMA Request */
- hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ return HAL_OK;
}
else
{
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- }
- return HAL_OK;
+ return HAL_ERROR;
+ }
}
else
{
@@ -3216,132 +4398,128 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/**
- * @brief Checks if target device is ready for communication.
- * @note This function is used with Memory devices
+ * @brief Enable the Address listen mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
- * @param Trials Number of trials
- * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
{
- uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ hi2c->State = HAL_I2C_STATE_LISTEN;
/* Check if the I2C is already enabled */
- if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
/* Enable I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
}
- /* Disable Pos */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
- hi2c->State = HAL_I2C_STATE_BUSY;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-
- do
- {
- /* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ /* Enable Address Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Send slave address */
- hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
- /* Wait until ADDR or AF flag are set */
- /* Get tick */
- tickstart = HAL_GetTick();
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- tmp3 = hi2c->State;
- while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State = HAL_I2C_STATE_TIMEOUT;
- }
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- tmp3 = hi2c->State;
- }
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Check if the ADDR flag has been set */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
- /* Clear ADDR Flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+/**
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(DevAddress);
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Abort Master transfer during Receive or Transmit process */
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_ABORT;
- return HAL_OK;
- }
- else
- {
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- /* Clear AF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- }while(I2C_Trials++ < Trials);
+ hi2c->XferCount = 0U;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
+
+ return HAL_OK;
}
else
{
- return HAL_BUSY;
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
/**
* @brief This function handles I2C event interrupt request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3350,100 +4528,153 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
{
- uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
- uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
- uint32_t itsources = READ_REG(hi2c->Instance->CR2);
-
- uint32_t CurrentMode = hi2c->Mode;
+ uint32_t sr1itflags;
+ uint32_t sr2itflags = 0U;
+ uint32_t itsources = READ_REG(hi2c->Instance->CR2);
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+ HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
/* Master or Memory mode selected */
- if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
+ if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
{
+ sr2itflags = READ_REG(hi2c->Instance->SR2);
+ sr1itflags = READ_REG(hi2c->Instance->SR1);
+
+ /* Exit IRQ event until Start Bit detected in case of Other frame requested */
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
+ {
+ return;
+ }
+
/* SB Set ----------------------------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
I2C_Master_SB(hi2c);
}
/* ADD10 Set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
I2C_Master_ADD10(hi2c);
}
/* ADDR Set --------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
I2C_Master_ADDR(hi2c);
}
-
/* I2C in mode Transmitter -----------------------------------------------*/
- if((sr2itflags & I2C_FLAG_TRA) != RESET)
+ else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
{
- /* TXE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_MasterTransmit_TXE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+ if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
{
- I2C_MasterTransmit_BTF(hi2c);
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+ {
+ I2C_MasterTransmit_TXE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+ {
+ I2C_MasterTransmit_BTF(hi2c);
+ }
+ else
+ {
+ /* Do nothing */
+ }
}
}
/* I2C in mode Receiver --------------------------------------------------*/
else
{
- /* RXNE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
- {
- I2C_MasterReceive_RXNE(hi2c);
- }
- /* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+ if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
{
- I2C_MasterReceive_BTF(hi2c);
+ /* RXNE set and BTF reset -----------------------------------------------*/
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+ {
+ I2C_MasterReceive_RXNE(hi2c);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+ {
+ I2C_MasterReceive_BTF(hi2c);
+ }
+ else
+ {
+ /* Do nothing */
+ }
}
}
}
/* Slave mode selected */
else
{
+ /* If an error is detected, read only SR1 register to prevent */
+ /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ sr1itflags = READ_REG(hi2c->Instance->SR1);
+ }
+ else
+ {
+ sr2itflags = READ_REG(hi2c->Instance->SR2);
+ sr1itflags = READ_REG(hi2c->Instance->SR1);
+ }
+
/* ADDR set --------------------------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
- I2C_Slave_ADDR(hi2c);
+ /* Now time to read SR2, this will clear ADDR flag automatically */
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ sr2itflags = READ_REG(hi2c->Instance->SR2);
+ }
+ I2C_Slave_ADDR(hi2c, sr2itflags);
}
/* STOPF set --------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
I2C_Slave_STOPF(hi2c);
}
/* I2C in mode Transmitter -----------------------------------------------*/
- else if((sr2itflags & I2C_FLAG_TRA) != RESET)
+ else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
/* TXE set and BTF reset -----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
{
I2C_SlaveTransmit_TXE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
I2C_SlaveTransmit_BTF(hi2c);
}
+ else
+ {
+ /* Do nothing */
+ }
}
/* I2C in mode Receiver --------------------------------------------------*/
else
{
/* RXNE set and BTF reset ----------------------------------------------*/
- if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
{
I2C_SlaveReceive_RXNE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
I2C_SlaveReceive_BTF(hi2c);
}
+ else
+ {
+ /* Do nothing */
+ }
}
}
}
@@ -3456,68 +4687,73 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+ HAL_I2C_ModeTypeDef tmp1;
+ uint32_t tmp2;
+ HAL_I2C_StateTypeDef tmp3;
+ uint32_t tmp4;
uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
uint32_t itsources = READ_REG(hi2c->Instance->CR2);
+ uint32_t error = HAL_I2C_ERROR_NONE;
/* I2C Bus error interrupt occurred ----------------------------------------*/
- if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+ error |= HAL_I2C_ERROR_BERR;
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
}
- /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
- if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+ error |= HAL_I2C_ERROR_ARLO;
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
}
/* I2C Acknowledge failure error interrupt occurred ------------------------*/
- if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
tmp1 = hi2c->Mode;
tmp2 = hi2c->XferCount;
tmp3 = hi2c->State;
tmp4 = hi2c->PreviousState;
- if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
- ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
- ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
+ if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
{
I2C_Slave_AF(hi2c);
}
else
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ error |= HAL_I2C_ERROR_AF;
/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
- if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
+ if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+ error |= HAL_I2C_ERROR_OVR;
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
}
/* Call the Error Callback in case of Error detected -----------------------*/
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (error != HAL_I2C_ERROR_NONE)
{
+ hi2c->ErrorCode |= error;
I2C_ITError(hi2c);
}
}
@@ -3534,7 +4770,7 @@ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
*/
}
@@ -3550,7 +4786,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
*/
}
@@ -3565,7 +4801,7 @@ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
*/
}
@@ -3581,7 +4817,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
*/
}
@@ -3589,7 +4825,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
* @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
* @param AddrMatchCode Address Match Code
* @retval None
*/
@@ -3601,7 +4837,7 @@ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirect
UNUSED(AddrMatchCode);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_AddrCallback can be implemented in the user file
+ the HAL_I2C_AddrCallback() could be implemented in the user file
*/
}
@@ -3616,9 +4852,9 @@ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ListenCpltCallback can be implemented in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+ */
}
/**
@@ -3633,7 +4869,7 @@ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemTxCpltCallback can be implemented in the user file
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file
*/
}
@@ -3649,7 +4885,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_MemRxCpltCallback can be implemented in the user file
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file
*/
}
@@ -3665,7 +4901,7 @@ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback can be implemented in the user file
+ the HAL_I2C_ErrorCallback could be implemented in the user file
*/
}
@@ -3690,14 +4926,14 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
*/
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State and Errors functions
+ * @brief Peripheral State, Mode and Error functions
*
@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -3717,7 +4953,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Return the I2C Master, Slave, Memory or no mode.
+ * @brief Returns the I2C Master, Slave, Memory or no mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL mode
@@ -3728,7 +4964,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Return the I2C error code
+ * @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
@@ -3742,23 +4978,31 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
/**
* @brief Handle TXE flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentMode = hi2c->Mode;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+ HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
- if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
+ if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
/* Call TxCpltCallback() directly if no stop mode is set */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -3766,7 +5010,11 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else /* Generate Stop condition then Call TxCpltCallback() */
{
@@ -3774,44 +5022,52 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
}
- else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
- ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
+ else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
{
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Disable BUF interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
}
else
{
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
- if(hi2c->EventCount == 0)
+ if (hi2c->EventCount == 0U)
{
/* If Memory address size is 8Bit */
- if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+ if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
- hi2c->EventCount += 2;
+ hi2c->EventCount += 2U;
}
/* If Memory address size is 16Bit */
else
@@ -3822,62 +5078,88 @@ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
hi2c->EventCount++;
}
}
- else if(hi2c->EventCount == 1)
+ else if (hi2c->EventCount == 1U)
{
/* Send LSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount++;
}
- else if(hi2c->EventCount == 2)
+ else if (hi2c->EventCount == 2U)
{
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
/* Generate Restart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
- else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
+ else
+ {
+ /* Do nothing */
+ }
+ }
+ else
+ {
+ /* Do nothing */
}
}
else
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
}
}
- return HAL_OK;
+ else
+ {
+ /* Do nothing */
+ }
}
/**
* @brief Handle BTF flag for Master transmitter
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
else
{
/* Call TxCpltCallback() directly if no stop mode is set */
- if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -3885,7 +5167,11 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else /* Generate Stop condition then Call TxCpltCallback() */
{
@@ -3893,49 +5179,60 @@ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
}
}
- return HAL_OK;
}
/**
* @brief Handle RXNE flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
- uint32_t tmp = 0U;
+ uint32_t tmp;
tmp = hi2c->XferCount;
- if(tmp > 3U)
+ if (tmp > 3U)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
- if(hi2c->XferCount == 3)
+ if (hi2c->XferCount == (uint16_t)3)
{
/* Disable BUF interrupt, this help to treat correctly the last 4 bytes
on BTF subroutine */
@@ -3943,134 +5240,192 @@ static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
}
}
- else if((tmp == 1U) || (tmp == 0U))
+ else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->PreviousState = I2C_STATE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Do nothing */
+ }
}
- return HAL_OK;
}
/**
* @brief Handle BTF flag for Master receiver
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
- if(hi2c->XferCount == 4U)
+ if (hi2c->XferCount == 4U)
{
/* Disable BUF interrupt, this help to treat correctly the last 2 bytes
on BTF subroutine if there is a reception delay between N-1 and N byte */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- else if(hi2c->XferCount == 3U)
+ else if (hi2c->XferCount == 3U)
{
/* Disable BUF interrupt, this help to treat correctly the last 2 bytes
on BTF subroutine if there is a reception delay between N-1 and N byte */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- else if(hi2c->XferCount == 2U)
+ else if (hi2c->XferCount == 2U)
{
/* Prepare next transfer or stop current transfer */
- if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME))
+ if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
- /* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
- else
+ else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
+ else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
+ else
+ {
+ /* Do nothing */
}
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
/* Disable EVT and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->PreviousState = I2C_STATE_NONE;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+ hi2c->PreviousState = I2C_STATE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- return HAL_OK;
}
/**
* @brief Handle SB flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
- if(hi2c->EventCount == 0U)
+ if (hi2c->EventCount == 0U)
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
@@ -4082,10 +5437,10 @@ static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
}
else
{
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave 7 Bits address */
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
}
@@ -4093,90 +5448,108 @@ static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
{
hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
}
+
+ if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+ {
+ if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
+ {
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ }
+ }
}
else
{
- if(hi2c->EventCount == 0U)
+ if (hi2c->EventCount == 0U)
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
}
- else if(hi2c->EventCount == 1U)
+ else if (hi2c->EventCount == 1U)
{
/* Send header of slave address */
hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
}
+ else
+ {
+ /* Do nothing */
+ }
}
}
-
- return HAL_OK;
}
/**
* @brief Handle ADD10 flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
{
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
- return HAL_OK;
+ if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+ {
+ if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
+ {
+ /* Enable DMA Request */
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ }
+ }
}
/**
* @brief Handle ADDR flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentMode = hi2c->Mode;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
- uint32_t Prev_State = hi2c->PreviousState;
+ HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+ uint32_t Prev_State = hi2c->PreviousState;
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
- if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+ if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+ else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
hi2c->EventCount++;
}
else
{
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
- else if(hi2c->XferCount == 1U)
+ else if (hi2c->XferCount == 1U)
{
- if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
+ if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -4187,22 +5560,22 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
}
/* Prepare next transfer or stop current transfer */
- else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
- && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
+ else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+ && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
{
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
else
{
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
/* Clear ADDR flag */
@@ -4211,35 +5584,35 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
else
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
}
- else if(hi2c->XferCount == 2U)
+ else if (hi2c->XferCount == 2U)
{
- if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
{
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Enable Pos */
- hi2c->Instance->CR1 |= I2C_CR1_POS;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
}
else
{
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
}
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
{
/* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
}
/* Clear ADDR flag */
@@ -4248,12 +5621,12 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
else
{
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
{
/* Enable Last DMA bit */
- hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
}
/* Clear ADDR flag */
@@ -4269,28 +5642,31 @@ static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
-
- return HAL_OK;
}
/**
* @brief Handle TXE flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
- if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
/* Last Byte is received, disable Interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
@@ -4299,48 +5675,60 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
hi2c->State = HAL_I2C_STATE_LISTEN;
- /* Call the Tx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
- return HAL_OK;
}
/**
* @brief Handle BTF flag for Slave transmitter
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- return HAL_OK;
}
/**
* @brief Handle RXNE flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
- if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Last Byte is received, disable Interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
@@ -4349,72 +5737,99 @@ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
hi2c->State = HAL_I2C_STATE_LISTEN;
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
- return HAL_OK;
}
/**
* @brief Handle BTF flag for Slave receiver
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- return HAL_OK;
}
/**
* @brief Handle ADD flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @param IT2Flags Interrupt2 flags to handle.
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
{
uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
- uint16_t SlaveAddrCode = 0U;
+ uint16_t SlaveAddrCode;
- /* Transfer Direction requested by Master */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
- TransferDirection = I2C_DIRECTION_TRANSMIT;
- }
+ /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
+ __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
- {
- SlaveAddrCode = hi2c->Init.OwnAddress1;
+ /* Transfer Direction requested by Master */
+ if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
+ {
+ TransferDirection = I2C_DIRECTION_TRANSMIT;
+ }
+
+ if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
+ {
+ SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
+ }
+ else
+ {
+ SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#else
+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
- SlaveAddrCode = hi2c->Init.OwnAddress2;
- }
-
- /* Call Slave Addr callback */
- HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
}
/**
* @brief Handle STOPF flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -4423,53 +5838,127 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_STOPFLAG(hi2c);
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* If a DMA is ongoing, Update handle size context */
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
- if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
- hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Disable, stop the current DMA */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Abort DMA Xfer if any */
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
}
else
{
- hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Disable, stop the current DMA */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+ /* Abort DMA Xfer if any */
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
}
}
/* All data are not transferred, so set error code accordingly */
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ /* Update counter */
hi2c->XferCount--;
}
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ if (hi2c->XferCount != 0U)
+ {
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
}
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c);
}
else
{
- if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
- (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
@@ -4477,36 +5966,43 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
- if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
}
- return HAL_OK;
}
/**
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentXferOptions = hi2c->XferOptions;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
- if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
- (CurrentState == HAL_I2C_STATE_LISTEN))
+ if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+ (CurrentState == HAL_I2C_STATE_LISTEN))
{
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -4517,21 +6013,25 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
- else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
+ else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
{
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -4540,9 +6040,13 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4550,8 +6054,6 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
/* State Listen, but XferOptions == FIRST or NEXT */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
-
- return HAL_OK;
}
/**
@@ -4562,9 +6064,15 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
static void I2C_ITError(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+ if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ {
+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+ }
- if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* keep HAL_I2C_STATE_LISTEN */
hi2c->PreviousState = I2C_STATE_NONE;
@@ -4574,7 +6082,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
{
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
- if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
+ if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
{
hi2c->State = HAL_I2C_STATE_READY;
}
@@ -4582,21 +6090,18 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
hi2c->Mode = HAL_I2C_MODE_NONE;
}
- /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
- hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
/* Abort DMA transfer */
- if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
{
hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
- if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
+ if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
{
/* Set the DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
- if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
@@ -4613,13 +6118,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
- if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
}
/* Disable I2C peripheral to prevent dummy data in buffer */
@@ -4632,55 +6140,77 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
}
}
}
- else if(hi2c->State == HAL_I2C_STATE_ABORT)
+ else if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
}
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
}
/* Call user error callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* STOP Flag is not set after a NACK reception */
/* So may inform upper layer that listen phase is stopped */
/* during NACK error treatment */
- if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
+ CurrentState = hi2c->State;
+ if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
{
- hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/**
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
@@ -4692,24 +6222,28 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
uint32_t CurrentXferOptions = hi2c->XferOptions;
/* Generate Start condition if first transfer */
- if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
{
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
{
/* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ }
+ else
+ {
+ /* Do nothing */
}
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
@@ -4720,16 +6254,9 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send slave address */
@@ -4737,16 +6264,9 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
return HAL_OK;
@@ -4756,7 +6276,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
* @brief Master sends target device address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address The device 7 bits address value
+ * @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
@@ -4768,27 +6288,31 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
uint32_t CurrentXferOptions = hi2c->XferOptions;
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Generate Start condition if first transfer */
- if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
{
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
}
- else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
{
/* Generate ReStart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ }
+ else
+ {
+ /* Do nothing */
}
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
@@ -4799,44 +6323,30 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send slave address */
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Send header of slave address */
@@ -4844,16 +6354,9 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
return HAL_OK;
@@ -4863,7 +6366,8 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -4873,50 +6377,39 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
@@ -4928,18 +6421,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -4953,7 +6442,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -4963,53 +6453,42 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
/* Enable Acknowledge */
- hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
/* Generate Start */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
@@ -5021,18 +6500,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -5040,43 +6515,32 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
}
+ return HAL_ERROR;
}
/* Generate Restart */
- hi2c->Instance->CR1 |= I2C_CR1_START;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
return HAL_OK;
@@ -5089,61 +6553,129 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
*/
static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
- uint32_t CurrentState = hi2c->State;
- uint32_t CurrentMode = hi2c->Mode;
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+ HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Clear Complete callback */
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ hi2c->hdmarx->XferCpltCallback = NULL;
- if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
+ if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
{
/* Disable DMA Request */
- hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
hi2c->XferCount = 0U;
- /* Enable EVT and ERR interrupt */
+ if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
}
- else
+ /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
+ else if (hi2c->Mode != HAL_I2C_MODE_NONE)
{
- /* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ if (hi2c->XferCount == (uint16_t)1)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ }
- /* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Prepare next transfer or stop current transfer */
+ if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ }
/* Disable Last DMA */
- hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
/* Disable DMA Request */
- hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
hi2c->XferCount = 0U;
/* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->PreviousState = I2C_STATE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
}
+ else
+ {
+ /* Do nothing */
+ }
}
/**
@@ -5153,10 +6685,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Clear Complete callback */
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ hi2c->hdmarx->XferCpltCallback = NULL;
/* Ignore DMA FIFO error */
- if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+ if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
{
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -5168,7 +6704,11 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -5180,10 +6720,17 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+ /* Clear Complete callback */
+ hi2c->hdmatx->XferCpltCallback = NULL;
+ hi2c->hdmarx->XferCpltCallback = NULL;
/* Disable Acknowledge */
- hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->XferCount = 0U;
@@ -5191,29 +6738,49 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
hi2c->hdmatx->XferAbortCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
/* Check if come from abort from user */
- if(hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ /* Renable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
- /* Disable I2C peripheral to prevent dummy data in buffer */
- __HAL_I2C_DISABLE(hi2c);
+ /* Enable Acknowledge */
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+ /* keep HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ }
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -5230,25 +6797,25 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait until flag is set */
- while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
-
return HAL_OK;
}
@@ -5263,19 +6830,20 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
*/
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Generate Stop */
- hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5284,17 +6852,19 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -5311,27 +6881,28 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
*/
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
{
return HAL_ERROR;
}
-
+
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -5348,27 +6919,28 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -5385,25 +6957,26 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -5420,17 +6993,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if a STOPF is detected */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5439,15 +7013,17 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -5461,14 +7037,15 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->PreviousState = I2C_STATE_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5477,12 +7054,40 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
}
return HAL_OK;
}
+
+/**
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+ /* if user set XferOptions to I2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to I2C_FIRST_FRAME */
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c_ex.c
index 852fe619ce44356938547d42ea727b6267e8f0f8..ed50332005cc93c8cc61d0e6ccf97054f01dc8e7 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2c_ex.c
@@ -28,29 +28,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -69,9 +53,7 @@
#ifdef HAL_I2C_MODULE_ENABLED
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -110,7 +92,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
hi2c->State = HAL_I2C_STATE_BUSY;
@@ -150,7 +132,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
hi2c->State = HAL_I2C_STATE_BUSY;
@@ -188,9 +170,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
/**
* @}
*/
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\
- STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F413xx ||\
- STM32F423xx */
+#endif
#endif /* HAL_I2C_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s.c
index de0c3a1c422067937a2a6744e939eed439cd5215..fc7f6ae52ec0ecc91231ff67205deb9cb27197c9 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s.c
@@ -27,13 +27,13 @@
(+++) Enable the NVIC I2S IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx Stream/Channel.
(+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Stream.
+ DMA Tx/Rx Stream/Channel.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
@@ -42,11 +42,11 @@
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-@- Make sure that either:
- (+@) I2S PLL is configured or
+ (+@) I2S PLL clock is configured or
(+@) External clock source is configured after setting correctly
the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
- (#) Three operation modes are available within this driver :
+ (#) Three mode of operations are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -90,7 +90,7 @@
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
*** I2S HAL driver macros list ***
- =============================================
+ ===================================
[..]
Below the list of most used macros in I2S HAL driver.
@@ -103,33 +103,74 @@
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : I2S Tx Completed callback
+ (+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxRxCpltCallback : I2S TxRx Completed callback
+ (+) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) ErrorCallback : I2S Error callback
+ (+) MspInitCallback : I2S Msp Init callback
+ (+) MspDeInitCallback : I2S Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : I2S Tx Completed callback
+ (+) RxCpltCallback : I2S Rx Completed callback
+ (+) TxRxCpltCallback : I2S TxRx Completed callback
+ (+) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (+) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (+) ErrorCallback : I2S Error callback
+ (+) MspInitCallback : I2S Msp Init callback
+ (+) MspDeInitCallback : I2S Msp DeInit callback
+
+ By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+ or HAL_I2S_Init() function.
+
+ When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -137,12 +178,12 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#ifdef HAL_I2S_MODULE_ENABLED
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-#ifdef HAL_I2S_MODULE_ENABLED
-
/** @defgroup I2S I2S
* @brief I2S HAL module driver
* @{
@@ -153,8 +194,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
-/** @addtogroup I2S_Private_Functions
+/** @defgroup I2S_Private_Functions I2S Private Functions
* @{
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
@@ -165,18 +205,19 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
uint32_t Timeout);
/**
* @}
*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
-/** @addtogroup I2S_Exported_Functions_Group1
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -199,14 +240,14 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
(++) Polarity
(++) Full duplex mode
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
of the selected I2Sx peripheral.
-@endverbatim
+ @endverbatim
* @{
*/
/**
- * @brief Initializes the I2S according to the specified parameters
+ * @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -214,11 +255,17 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
- uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
- uint32_t tmp = 0U, i2sclk = 0U;
+ uint32_t i2sdiv;
+ uint32_t i2sodd;
+ uint32_t packetlength;
+ uint32_t tmp;
+ uint32_t i2sclk;
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ uint16_t tmpreg;
+#endif
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
@@ -233,51 +280,76 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
- hi2s->State = HAL_I2S_STATE_BUSY;
+ if (hi2s->State == HAL_I2S_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+
+ /* Initialize Default I2S IrqHandler ISR */
+ hi2s->IrqHandlerISR = I2S_IRQHandler;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ /* Init the I2S Callback settings */
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+#endif
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+#endif
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
- /* Initialize Default I2S IrqHandler ISR */
- hi2s->IrqHandlerISR = I2S_IRQHandler;
+ if (hi2s->MspInitCallback == NULL)
+ {
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hi2s->MspInitCallback(hi2s);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+ }
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
+ hi2s->State = HAL_I2S_STATE_BUSY;
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
hi2s->Instance->I2SPR = 0x0002U;
- /* Get the I2SCFGR register value */
- tmpreg = hi2s->Instance->I2SCFGR;
-
- /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+ /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
/* If the requested audio frequency is not the default, compute the prescaler */
- if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+ if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
- /* Check the frame length (For the Prescaler computing) *******************/
- /* Set I2S Packet Length value*/
- if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ /* Check the frame length (For the Prescaler computing) ********************/
+ if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
- /* Packet length is 32 bits */
- packetlength = 32U;
+ /* Packet length is 16 bits */
+ packetlength = 16U;
}
else
{
- /* Packet length is 16 bits */
- packetlength = 16U;
+ /* Packet length is 32 bits */
+ packetlength = 32U;
}
/* I2S standard */
- if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
{
/* In I2S standard packet lenght is multiplied by 2 */
packetlength = packetlength * 2U;
}
- /* Get I2S source Clock frequency from RCC ********************************/
+ /* Get the source clock value **********************************************/
#if defined(I2S_APB1_APB2_FEATURE)
- if(IS_I2S_APB1_INSTANCE(hi2s->Instance))
+ if (IS_I2S_APB1_INSTANCE(hi2s->Instance))
{
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1);
}
@@ -290,72 +362,72 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
#endif
/* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
{
- tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
else
{
- tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
}
else
{
/* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)1U);
+ i2sodd = (uint32_t)(tmp & (uint32_t)1U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+ i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint32_t) (i2sodd << 8U);
+ i2sodd = (uint32_t)(i2sodd << 8U);
}
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ else
{
/* Set the default values */
i2sdiv = 2U;
i2sodd = 0U;
+ }
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
- HAL_I2S_ErrorCallback(hi2s);
return HAL_ERROR;
}
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
- /* Configure the I2S with the I2S_InitStruct values */
- tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
- (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL));
#if defined(SPI_I2SCFGR_ASTRTEN)
- if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||(hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
{
- /* Write to SPIx I2SCFGR */
- WRITE_REG(hi2s->Instance->I2SCFGR,(tmpreg | SPI_I2SCFGR_ASTRTEN));
- }
- else
- {
- /* Write to SPIx I2SCFGR */
- WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
+ /* Write to SPIx I2SCFGR */
+ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
}
-#else
- /* Write to SPIx I2SCFGR */
- WRITE_REG(hi2s->Instance->I2SCFGR, tmpreg);
#endif
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
@@ -363,22 +435,22 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* Configure the I2S extended if the full duplex mode is enabled */
assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
- if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
- /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
+ /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
I2SxEXT(hi2s->Instance)->I2SPR = 2U;
/* Get the I2SCFGR register value */
tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
/* Get the mode to be configured for the extended I2S */
- if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
tmp = I2S_MODE_SLAVE_RX;
}
@@ -390,10 +462,10 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* Configure the I2S Slave with the I2S Master parameter values */
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
(uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
- (uint16_t)hi2s->Init.CPOL))));
+ (uint16_t)hi2s->Init.CPOL))));
/* Write to SPIx I2SCFGR */
- WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR,tmpreg);
+ WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
@@ -412,15 +484,31 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
hi2s->State = HAL_I2S_STATE_BUSY;
+ /* Disable the I2S Peripheral Clock */
+ __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ if (hi2s->MspDeInitCallback == NULL)
+ {
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hi2s->MspDeInitCallback(hi2s);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_RESET;
@@ -437,10 +525,11 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
*/
@@ -452,19 +541,236 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
*/
}
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User I2S Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = pCallback;
+ break;
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+ hi2s->TxRxCpltCallback = pCallback;
+ break;
+#endif
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = pCallback;
+ break;
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+ hi2s->TxRxHalfCpltCallback = pCallback;
+ break;
+#endif
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2S Callback
+ * I2S callback is redirected to the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ case HAL_I2S_TX_RX_COMPLETE_CB_ID :
+ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+#endif
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
+ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+#endif
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group2
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -507,517 +813,538 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
/**
- * @brief Transmit an amount of data in blocking mode
+ * @brief Transmit an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
* @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- while(hi2s->TxXferCount > 0U)
- {
- hi2s->Instance->DR = (*pData++);
- hi2s->TxXferCount--;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR;
- /* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
- {
- /* Clear underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- HAL_I2S_ErrorCallback(hi2s);
+ while (hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
- return HAL_ERROR;
- }
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
- hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- return HAL_OK;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
}
- else
+
+ /* Check if Slave mode is selected */
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
- return HAL_BUSY;
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
}
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming)
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continuous way and as the I2S is not disabled at the end of the I2S transaction
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Receive data */
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- HAL_I2S_ErrorCallback(hi2s);
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
- return HAL_ERROR;
- }
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
- (*pData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
+ /* Receive data */
+ while (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
}
- hi2s->State = HAL_I2S_STATE_READY;
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
}
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if ((pData == NULL) || (Size == 0U))
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pTxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ return HAL_ERROR;
+ }
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- return HAL_OK;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
- return HAL_BUSY;
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
* between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if ((pData == NULL) || (Size == 0U))
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- hi2s->pRxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ return HAL_ERROR;
+ }
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- return HAL_OK;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
-
else
{
- return HAL_BUSY;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
}
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Transmit data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t *tmp = NULL;
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
- /* Check if the I2S Tx request is already enabled */
- if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
- {
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- }
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- return HAL_OK;
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
- else
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
{
- return HAL_BUSY;
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with DMA
+ * @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- uint32_t *tmp = NULL;
- uint32_t tmp1 = 0U;
+ uint32_t tmpreg_cfgr;
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- hi2s->pRxBuffPtr = pData;
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ __HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
- /* Check if the I2S Rx request is already enabled */
- if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
- {
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- }
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
- return HAL_OK;
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
}
- else
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
{
- return HAL_BUSY;
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Pauses the audio stream playing from the Media.
+ * @brief Pauses the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -1027,24 +1354,28 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Pause the audio file playing by disabling the I2S DMA request */
- CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN));
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+ else
+ {
+ /* nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
@@ -1053,7 +1384,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Resumes the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -1063,22 +1394,22 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Pause the audio file playing by disabling the I2S DMA request */
- SET_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ SET_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
/* If the I2Sext peripheral is still not enabled, enable it */
if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
@@ -1088,9 +1419,13 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
}
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+ else
+ {
+ /* nothing to do */
+ }
/* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
@@ -1103,42 +1438,52 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Stops the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ */
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
{
- /* Disable the I2S DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
-
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmatx);
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
- {
- /* Disable the I2S DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
- /* Disable the I2S DMA Channel */
- HAL_DMA_Abort(hi2s->hdmarx);
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
- else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ /* In case of Full-Duplex, disable the I2SxEXT Tx/Rx DMA requests*/
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
- /* Disable the I2S DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-
- /* Disable the I2S DMA Channels */
- HAL_DMA_Abort(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmarx);
+ /* Disable the I2SxEXT DMA requests */
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
/* Disable I2Sext peripheral */
__HAL_I2SEXT_DISABLE(hi2s);
@@ -1150,10 +1495,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
+ return errorcode;
}
/**
@@ -1169,37 +1511,39 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Tx Transfer Half completed callbacks
+ * @brief Tx Transfer Half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Tx Transfer completed callbacks
+ * @brief Tx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer half completed callbacks
+ * @brief Rx Transfer half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1208,13 +1552,14 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks
+ * @brief Rx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1223,21 +1568,23 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief I2S error callbacks
+ * @brief I2S error callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/
@@ -1247,7 +1594,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
* @}
*/
-/** @addtogroup I2S_Exported_Functions_Group3
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State functions
*
@verbatim
@@ -1295,139 +1642,180 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
* @{
*/
/**
- * @brief DMA I2S transmit process complete callback
+ * @brief DMA I2S transmit process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
hi2s->TxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
+
/**
- * @brief DMA I2S transmit process half complete callback
+ * @brief DMA I2S transmit process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxHalfCpltCallback(hi2s);
+#else
HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process complete callback
+ * @brief DMA I2S receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
hi2s->RxXferCount = 0U;
- hi2s->State = HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
}
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process half complete callback
+ * @brief DMA I2S receive process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxHalfCpltCallback(hi2s);
+#else
HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S communication error callback
+ * @brief DMA I2S communication error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @retval HAL status
+ * @retval None
*/
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0U)
+ if (hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @retval HAL status
+ * @retval None
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
/* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
- if(hi2s->RxXferCount == 0U)
+ if (hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
* @brief This function handles I2S interrupt request.
- * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1435,16 +1823,16 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
__IO uint32_t i2ssr = hi2s->Instance->SR;
- if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* I2S in mode Receiver ------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
{
I2S_Receive_IT(hi2s);
}
- /* I2S Overrun error interrupt occured -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2S Overrun error interrupt occurred -------------------------------------*/
+ if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1457,22 +1845,27 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
- }
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
+ }
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
{
- /* I2S in mode Transmitter -----------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
- }
+ I2S_Transmit_IT(hi2s);
+ }
- /* I2S Underrun error interrupt occurred --------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1484,31 +1877,38 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief This function handles I2S Communication Timeout.
+ * @brief This function handles I2S Communication Timeout.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
- uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Wait until flag is set to status*/
- while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ /* Wait until flag is set to status*/
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
@@ -1531,9 +1931,10 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
* @}
*/
-#endif /* HAL_I2S_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_I2S_MODULE_ENABLED */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s_ex.c
index 81443a5ab5f4a4512c493586e384b11d54d0920d..abc960fb35c6a8d516ba09008aa45abaecc4b9fe 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_i2s_ex.c
@@ -72,29 +72,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -123,7 +107,7 @@ typedef enum
{
I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
-}I2S_UseTypeDef;
+} I2S_UseTypeDef;
/**
* @}
*/
@@ -137,10 +121,12 @@ typedef enum
static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
-static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
-static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
+static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
+static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
+static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
/**
* @}
*/
@@ -197,429 +183,347 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp
* @{
*/
/**
- * @brief Full-Duplex Transmit/Receive data in blocking mode.
+ * @brief Full-Duplex Transmit/Receive data in blocking mode.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
uint32_t tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Check the I2S State */
- if(hi2s->State == HAL_I2S_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ /* Set state and reset error code */
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Prepare the First Data before enabling the I2S */
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
- /* Set the I2S State busy TX/RX */
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
{
- /* Prepare the First Data before enabling the I2S */
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
+ }
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
+ while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ {
+ if (hi2s->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+ /* Write Data on DR register */
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
- /* Enable I2Sx peripheral */
- __HAL_I2S_ENABLE(hi2s);
+ /* Check if an underrun occurs */
+ if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
}
-
- while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ if (hi2s->RxXferCount > 0U)
{
- if(hi2s->TxXferCount > 0U)
+ /* Wait until RXNE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
{
- /* Wait until TXE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
- /* Write Data on DR register */
- hi2s->Instance->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Check if an underrun occurs */
- if((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ errorcode = HAL_ERROR;
+ goto error;
}
- if(hi2s->RxXferCount > 0U)
+ /* Read Data from DR register */
+ (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
{
- /* Wait until RXNE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
- /* Read Data from DR register */
- (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
-
- /* Check if an overrun occurs */
- if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
}
}
}
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
- {
- /* Prepare the First Data before enabling the I2S */
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Prepare the First Data before enabling the I2S */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
- /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
- /* Enable I2S peripheral before the I2Sext*/
- __HAL_I2S_ENABLE(hi2s);
+ /* Enable I2S peripheral before the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
- while((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
+ {
+ if (hi2s->TxXferCount > 0U)
{
- if(hi2s->TxXferCount > 0U)
+ /* Wait until TXE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
{
- /* Wait until TXE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
- /* Write Data on DR register */
- I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
- hi2s->TxXferCount--;
-
- /* Check if an underrun occurs */
- if((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
- {
- /* Clear Underrun flag */
- __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ errorcode = HAL_ERROR;
+ goto error;
}
- if(hi2s->RxXferCount > 0U)
+ /* Write Data on DR register */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Check if an underrun occurs */
+ if ((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
{
- /* Wait until RXNE flag is set */
- if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
- {
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
- HAL_I2S_ErrorCallback(hi2s);
- return HAL_TIMEOUT;
- }
- /* Read Data from DR register */
- (*pRxData++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
-
- /* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
- {
- /* Clear Overrun flag */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
- HAL_I2S_ErrorCallback(hi2s);
-
- return HAL_ERROR;
- }
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
}
}
- }
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ if (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+ /* Read Data from DR register */
+ (*pRxData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- return HAL_OK;
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+ }
+ }
}
- else
+
+ if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
{
- return HAL_BUSY;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return errorcode;
}
/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size)
{
uint32_t tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
- {
- return HAL_ERROR;
- }
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- /* Enable I2Sx TXE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ /* Set the function for IT treatment */
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
- {
- /* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0U)
- {
- /* Transmit First data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable I2Sext RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
- }
- }
- }
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable I2Sx TXE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- /* Enable I2Sx peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
- }
- /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
- else
+ /* Transmit First data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if (hi2s->TxXferCount == 0U)
{
- /* Enable I2Sext TXE and ERR interrupts */
- __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+ }
+ }
+ else /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ {
+ /* Enable I2Sext TXE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- /* Enable I2Sext RXNE and ERR interrupts */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Check if the I2S_MODE_MASTER_RX is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0U)
- {
- /* Transmit First data */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0U)
- {
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0U)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
-
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
- }
- }
- }
- /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
+ /* Transmit First data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
+ if (hi2s->TxXferCount == 0U)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
}
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
}
+
+ /* Enable I2Sext peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+
+error :
+ __HAL_UNLOCK(hi2s);
+ return errorcode;
}
/**
- * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData a 16-bit pointer to the Transmit data buffer.
- * @param pRxData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
@@ -627,131 +531,130 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
{
uint32_t *tmp = NULL;
uint32_t tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- return HAL_ERROR;
+ errorcode = HAL_BUSY;
+ goto error;
}
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- hi2s->pTxBuffPtr = pTxData;
- hi2s->pRxBuffPtr = pRxData;
-
- tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
- /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
- is selected during the I2S configuration phase, the Size parameter means the number
- of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
- frame is selected the Size parameter means the number of 16-bit data length. */
- if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
+ return HAL_ERROR;
+ }
- /* Process Locked */
- __HAL_LOCK(hi2s);
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
- /* Set the I2S Rx DMA Half transfer complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
- /* Set the I2S Rx DMA transfer complete callback */
- hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
- /* Set the I2S Rx DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
- /* Set the I2S Tx DMA Half transfer complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
+ /* Set the I2S Rx DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
- /* Set the I2S Tx DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
- tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
- /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
- {
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
- /* Enable Rx DMA Request */
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
+ /* Set the I2S Tx DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+ tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t *)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
- /* Enable Tx DMA Request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ /* Enable Rx DMA Request */
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t *)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
- /* Enable I2S peripheral after the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext */
+ __HAL_I2S_ENABLE(hi2s);
}
- else
+ }
+ else
+ {
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
- /* Enable the Tx DMA Stream */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t *)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
- /* Enable Tx DMA Request */
- SET_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
+ /* Enable Tx DMA Request */
+ SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
- /* Enable the Rx DMA Stream */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t *)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
- __HAL_I2SEXT_ENABLE(hi2s);
- /* Enable I2S peripheral before the I2Sext */
- __HAL_I2S_ENABLE(hi2s);
- }
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ /* Enable I2S peripheral before the I2Sext */
+ __HAL_I2S_ENABLE(hi2s);
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
}
+
+error :
+ __HAL_UNLOCK(hi2s);
+ return errorcode;
}
/**
@@ -761,31 +664,32 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
*/
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
{
- __IO uint32_t i2ssr = hi2s->Instance->SR ;
- __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
+ __IO uint32_t i2ssr = hi2s->Instance->SR;
+ __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
+ __IO uint32_t i2scr2 = hi2s->Instance->CR2;
+ __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
- if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
- || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
/* I2S in mode Transmitter -------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET))
{
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
+ I2SEx_TxISR_I2S(hi2s);
}
/* I2Sext in mode Receiver -----------------------------------------------*/
- if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET))
{
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
+ I2SEx_RxISR_I2SExt(hi2s);
}
- /* I2Sext Overrun error interrupt occured --------------------------------*/
- if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2Sext Overrun error interrupt occurred --------------------------------*/
+ if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
{
/* Disable RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -800,12 +704,17 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
- /* I2S Underrun error interrupt occured ----------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2S Underrun error interrupt occurred ----------------------------------*/
+ if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -820,31 +729,36 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
/* I2Sext in mode Transmitter ----------------------------------------------*/
- if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET))
{
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
- I2SEx_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
+ I2SEx_TxISR_I2SExt(hi2s);
}
/* I2S in mode Receiver --------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET))
{
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
- I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
+ I2SEx_RxISR_I2S(hi2s);
}
- /* I2S Overrun error interrupt occured -------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2S Overrun error interrupt occurred -------------------------------------*/
+ if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET))
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -856,12 +770,17 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
- /* I2Sext Underrun error interrupt occured -------------------------------*/
- if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ /* I2Sext Underrun error interrupt occurred -------------------------------*/
+ if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
{
/* Disable TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -873,15 +792,20 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_UDR);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief Tx and Rx Transfer half completed callback
- * @param hi2s I2S handle
+ * @brief Tx and Rx Transfer half completed callback
+ * @param hi2s I2S handle
* @retval None
*/
__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -895,8 +819,8 @@ __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
}
/**
- * @brief Tx and Rx Transfer completed callback
- * @param hi2s I2S handle
+ * @brief Tx and Rx Transfer completed callback
+ * @param hi2s I2S handle
* @retval None
*/
__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -904,7 +828,7 @@ __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
*/
}
@@ -922,42 +846,47 @@ __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
*/
/**
- * @brief DMA I2S transmit receive process half complete callback
+ * @brief DMA I2S transmit receive process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Call user TxRx Half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxHalfCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S transmit receive process complete callback
+ * @brief DMA I2S transmit receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- /* if DMA is not configured in DMA_CIRCULAR mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* if DMA is configured in DMA_NORMAL mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
if (hi2s->hdmarx == hdma)
{
/* Disable Rx DMA Request */
- if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
+ if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
{
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_RXDMAEN);
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
}
else
{
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
hi2s->RxXferCount = 0U;
@@ -966,21 +895,26 @@ static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
{
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
if (hi2s->hdmatx == hdma)
{
/* Disable Tx DMA Request */
- if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) ||\
+ if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
{
- CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
else
{
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,SPI_CR2_TXDMAEN);
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
}
hi2s->TxXferCount = 0U;
@@ -989,123 +923,157 @@ static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
{
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
}
/**
- * @brief DMA I2S communication error callback
- * @param hdma DMA handle
+ * @brief DMA I2S communication error callback
+ * @param hdma DMA handle
* @retval None
*/
static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief Full-Duplex IT handler transmit function
- * @param hi2s I2S handle
- * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
+ * @brief I2S Full-Duplex IT handler transmit function
+ * @param hi2s I2S handle
* @retval None
*/
-static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s)
{
- if(i2sUsed == I2S_USE_I2S)
+ /* Write Data on DR register */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if (hi2s->TxXferCount == 0U)
{
- /* Write Data on DR register */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->TxXferCount == 0U)
+ if (hi2s->RxXferCount == 0U)
{
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
- else
+}
+
+/**
+ * @brief I2SExt Full-Duplex IT handler transmit function
+ * @param hi2s I2S handle
+ * @retval None
+ */
+static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s)
+{
+ /* Write Data on DR register */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if (hi2s->TxXferCount == 0U)
{
- /* Write Data on DR register */
- I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->TxXferCount == 0U)
+ if (hi2s->RxXferCount == 0U)
{
- /* Disable I2Sext TXE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- if(hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief Full-Duplex IT handler receive function
- * @param hi2s I2S handle
- * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
+ * @brief I2S Full-Duplex IT handler receive function
+ * @param hi2s I2S handle
* @retval None
*/
-static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s)
{
- if(i2sUsed == I2S_USE_I2S)
+ /* Read Data from DR register */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if (hi2s->RxXferCount == 0U)
{
- /* Read Data from DR register */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0U)
+ if (hi2s->TxXferCount == 0U)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if(hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
- else
+}
+
+/**
+ * @brief I2SExt Full-Duplex IT handler receive function
+ * @param hi2s I2S handle
+ * @retval None
+ */
+static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
+{
+ /* Read Data from DR register */
+ (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ if (hi2s->RxXferCount == 0U)
{
- /* Read Data from DR register */
- (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
- hi2s->RxXferCount--;
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0U)
+ if (hi2s->TxXferCount == 0U)
{
- /* Disable I2Sext RXNE and ERR interrupt */
- __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- if(hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2SEx_TxRxCpltCallback(hi2s);
- }
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxRxCpltCallback(hi2s);
+#else
+ HAL_I2SEx_TxRxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
@@ -1120,21 +1088,21 @@ static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUse
* @retval HAL status
*/
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
- uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
{
uint32_t tickstart = HAL_GetTick();
- if(i2sUsed == I2S_USE_I2S)
+ if (i2sUsed == I2S_USE_I2S)
{
/* Wait until flag is reset */
- while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
@@ -1147,14 +1115,14 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp
else /* i2sUsed == I2S_USE_I2SEXT */
{
/* Wait until flag is reset */
- while(((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
+ while (((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_irda.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_irda.c
index e9f3bc08b832a5677a2ebd30ef5f80265b205be8..97b1475d10e5f3a7c8fd3e12faf26c24bf43d4b2 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_irda.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_irda.c
@@ -5,10 +5,10 @@
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
- * + Initialization and de-initialization methods
- * + IO operation methods
- * + Peripheral Control methods
- *
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,12 +16,12 @@
[..]
The IRDA HAL driver can be used as follows:
- (#) Declare a IRDA_HandleTypeDef handle structure.
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
(#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
(##) Enable the USARTx interface clock.
(##) IRDA pins configuration:
(+++) Enable the clock for the IRDA GPIOs.
- (+++) Configure these IRDA pins as alternate function pull-up.
+ (+++) Configure IRDA pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
and HAL_IRDA_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -31,19 +31,22 @@
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx stream.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+ (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
and Mode(Receiver/Transmitter) in the hirda Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_IRDA_MspInit() API.
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
@@ -69,56 +72,128 @@
=============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
+ (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
+ (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
*** IRDA HAL driver macros list ***
===================================
[..]
Below the list of most used macros in IRDA HAL driver.
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
- (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
- (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
- (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
- (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
[..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
+ Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
+ and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
+ or @ref HAL_IRDA_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible IRDA frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | IRDA frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | 1 STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -139,19 +214,17 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Constants
- * @{
- */
-/**
- * @}
- */
+/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
@@ -165,12 +238,13 @@ static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
* @{
@@ -181,12 +255,12 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
*
@verbatim
-===============================================================================
+ ==============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in IrDA mode.
+ in asynchronous IrDA mode.
(+) For the asynchronous mode only these parameters can be configured:
(++) BaudRate
(++) WordLength
@@ -211,14 +285,14 @@ static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -228,12 +302,25 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* Check the IRDA mode parameter in the IRDA handle */
assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
- if(hirda->gState == HAL_IRDA_STATE_RESET)
+ if (hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ IRDA_InitCallbacksToDefault(hirda);
+
+ if (hirda->MspInitCallback == NULL)
+ {
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hirda->MspInitCallback(hirda);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
hirda->gState = HAL_IRDA_STATE_BUSY;
@@ -247,8 +334,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* In IrDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(hirda->Instance->CR2, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* Enable the IRDA peripheral */
__HAL_IRDA_ENABLE(hirda);
@@ -264,22 +351,22 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
/* Initialize the IRDA state*/
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the IRDA peripheral
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -293,7 +380,16 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
__HAL_IRDA_DISABLE(hirda);
/* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ if (hirda->MspDeInitCallback == NULL)
+ {
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hirda->MspDeInitCallback(hirda);
+#else
HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -308,7 +404,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
/**
* @brief IRDA MSP Init.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -316,14 +412,15 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit could be implemented in the user file
- */
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
}
/**
* @brief IRDA MSP DeInit.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -331,24 +428,263 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit could be implemented in the user file
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IRDA Callback
+ * To be used instead of the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an IRDA callback
+ * IRDA callback is redirected to the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (HAL_IRDA_STATE_READY == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_IRDA_STATE_RESET == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit/Receive functions
+ * @brief IRDA Transmit and Receive functions
*
@verbatim
- ===============================================================================
+ ==============================================================================
##### IO operation functions #####
- ===============================================================================
- This subsection provides a set of functions allowing to manage the IRDA data transfers.
+ ==============================================================================
[..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
@@ -359,16 +695,16 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
+ (++) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
+ will be executed respectively at the end of the Transmit or Receive process
The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
+ (#) Blocking mode APIs are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
@@ -380,19 +716,48 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
(#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_IRDA_Abort()
+ (+) HAL_IRDA_AbortTransmit()
+ (+) HAL_IRDA_AbortReceive()
+ (+) HAL_IRDA_Abort_IT()
+ (+) HAL_IRDA_AbortTransmit_IT()
+ (+) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_IRDA_AbortCpltCallback()
+ (+) HAL_IRDA_AbortTransmitCpltCallback()
+ (+) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
* @brief Sends an amount of data in blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -401,13 +766,13 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -423,29 +788,29 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0U)
+ while (hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData;
+ tmp = (uint16_t *) pData;
hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
- pData +=2;
+ pData += 2U;
}
else
{
- pData +=1;
+ pData += 1U;
}
}
else
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -453,7 +818,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
}
}
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -474,7 +839,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
@@ -483,13 +848,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -505,35 +870,37 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
+
/* Check the remain data to be received */
- while(hirda->RxXferCount > 0U)
+ while (hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+
+ if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData ;
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ tmp = (uint16_t *) pData ;
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
- pData +=2;
+ pData += 2U;
}
else
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
- pData +=1;
+ pData += 1U;
}
}
else
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
}
@@ -560,7 +927,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -569,18 +936,20 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
@@ -599,8 +968,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
}
/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Receive an amount of data in non blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
@@ -608,10 +977,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -622,16 +991,17 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+ /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
@@ -643,8 +1013,8 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
}
/**
- * @brief Sends an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Send an amount of data in non blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -655,9 +1025,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -668,6 +1038,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
@@ -683,9 +1054,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/* Set the DMA abort callback */
hirda->hdmatx->XferAbortCallback = NULL;
- /* Enable the IRDA transmit DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
+ /* Enable the IRDA transmit DMA stream */
+ tmp = (uint32_t *)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
@@ -707,7 +1078,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
@@ -719,9 +1090,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -731,6 +1102,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
@@ -746,10 +1118,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Set the DMA abort callback */
hirda->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
-
+ /* Enable the DMA stream */
+ tmp = (uint32_t *)&pData;
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size);
+
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
@@ -759,7 +1131,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/* Enable the IRDA Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
@@ -776,7 +1148,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
/**
* @brief Pauses the DMA Transfer.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -788,14 +1160,14 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
__HAL_LOCK(hirda);
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
@@ -813,7 +1185,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
/**
* @brief Resumes the DMA Transfer.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -822,12 +1194,13 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
/* Process Locked */
__HAL_LOCK(hirda);
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
@@ -848,7 +1221,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
/**
* @brief Stops the DMA Transfer.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -856,19 +1229,19 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
uint32_t dmarequest = 0x00U;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
*/
/* Stop IRDA DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
HAL_DMA_Abort(hirda->hdmatx);
}
@@ -877,17 +1250,18 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
/* Stop IRDA DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
HAL_DMA_Abort(hirda->hdmarx);
}
IRDA_EndRxTransfer(hirda);
}
+
return HAL_OK;
}
@@ -910,12 +1284,12 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -926,12 +1300,12 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
}
/* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -973,12 +1347,12 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -1016,12 +1390,12 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -1056,7 +1430,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
- uint32_t AbortCplt = 1U;
+ uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
@@ -1065,11 +1439,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
@@ -1079,11 +1453,11 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
}
/* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
@@ -1094,19 +1468,19 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at IRDA level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
@@ -1118,18 +1492,18 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
/* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
@@ -1142,7 +1516,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
+ if (AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0x00U;
@@ -1156,7 +1530,13 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1167,7 +1547,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1182,19 +1562,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
@@ -1209,7 +1589,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
@@ -1221,7 +1607,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1248,19 +1640,19 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1275,7 +1667,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
@@ -1287,7 +1685,13 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1295,24 +1699,24 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief This function handles IRDA interrupt request.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
- uint32_t isrflags = READ_REG(hirda->Instance->SR);
- uint32_t cr1its = READ_REG(hirda->Instance->CR1);
- uint32_t cr3its = READ_REG(hirda->Instance->CR3);
- uint32_t errorflags = 0x00U;
- uint32_t dmarequest = 0x00U;
+ uint32_t isrflags = READ_REG(hirda->Instance->SR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its = READ_REG(hirda->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
+ if (errorflags == RESET)
{
/* IRDA in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
IRDA_Receive_IT(hirda);
return;
@@ -1320,44 +1724,44 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* IRDA parity error interrupt occurred -------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
}
/* IRDA noise error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
}
/* IRDA frame error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
}
/* IRDA Over-Run interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
/* Call IRDA Error Call back function if need be -----------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
/* IRDA in mode Receiver ---------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
IRDA_Receive_IT(hirda);
}
- dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
- if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
{
/* Blocking error : transfer is aborted
Set the IRDA state ready to be able to start again the process,
@@ -1365,18 +1769,19 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
IRDA_EndRxTransfer(hirda);
/* Disable the IRDA DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1384,21 +1789,38 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
}
}
@@ -1406,14 +1828,14 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
} /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
IRDA_Transmit_IT(hirda);
return;
}
/* IRDA in mode Transmitter end --------------------------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
IRDA_EndTransmit_IT(hirda);
return;
@@ -1421,260 +1843,105 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
}
/**
- * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda IRDA handle.
+ * @brief Tx Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
- * @param hirda IRDA handle.
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
+ * @brief Rx Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0x00U;
- hirda->TxXferCount = 0x00U;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- HAL_IRDA_ErrorCallback(hirda);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user
- * (To be called at end of DMA Tx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
- {
- if(hirda->hdmarx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
+/**
+ * @brief IRDA error callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
}
/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user
- * (To be called at end of DMA Rx Abort procedure following user abort request).
- * @note When this callback is executed, User Abort complete call back is called only if no
- * Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
- {
- if(hirda->hdmatx->XferAbortCallback != NULL)
- {
- return;
- }
- }
-
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
- hirda->TxXferCount = 0x00U;
- hirda->RxXferCount = 0x00U;
-
- /* Reset ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Restore hirda->gState and hirda->RxState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
- * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
- * and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->TxXferCount = 0x00U;
-
- /* Restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortTransmitCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
- * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
- * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
- * and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
- * @retval None
- */
-static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->RxXferCount = 0x00U;
-
- /* Restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Call user Abort complete callback */
- HAL_IRDA_AbortReceiveCpltCallback(hirda);
-}
-
-/**
- * @brief Tx Transfer complete callbacks.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Tx Half Transfer completed callbacks.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
- * @retval None
- */
-__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Transfer complete callbacks.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Rx Half Transfer complete callbacks.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA error callbacks.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA Abort Complete callback.
- * @param hirda IRDA handle.
- * @retval None
- */
-__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
- */
-}
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
/**
* @brief IRDA Abort Transmit Complete callback.
- * @param hirda IRDA handle.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -1688,8 +1955,9 @@ __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
}
/**
- * @brief IRDA Abort ReceiveComplete callback.
- * @param hirda IRDA handle.
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -1724,9 +1992,9 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
*/
/**
- * @brief Returns the IRDA state.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Return the IRDA state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
@@ -1739,8 +2007,8 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
}
/**
- * @brief Return the IARDA error code
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Return the IRDA error code
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA.
* @retval IRDA Error Code
*/
@@ -1753,21 +2021,51 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
* @}
*/
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hirda IRDA handle.
+ * @retval none
+ */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+ /* Init the IRDA Callback settings */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @brief DMA IRDA transmit process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
hirda->TxXferCount = 0U;
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Enable the IRDA Transmit Complete Interrupt */
@@ -1776,33 +2074,47 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Circular mode */
else
{
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
/**
* @brief DMA IRDA receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half complete callback */
+ hirda->TxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA receive process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
hirda->RxXferCount = 0U;
@@ -1810,42 +2122,56 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the IRDA CR3 register */
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
/**
- * @brief DMA IRDA receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ hirda->RxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx Half complete callback */
HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA communication error callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop IRDA DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
hirda->TxXferCount = 0U;
IRDA_EndTxTransfer(hirda);
@@ -1853,7 +2179,7 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
/* Stop IRDA DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
hirda->RxXferCount = 0U;
IRDA_EndRxTransfer(hirda);
@@ -1861,13 +2187,19 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief This function handles IRDA Communication Timeout.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA.
* @param Flag specifies the IRDA flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Tickstart Tick start value
@@ -1877,12 +2209,12 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -1901,24 +2233,216 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
return HAL_OK;
}
- /**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hirda->RxXferCount = 0x00U;
+ hirda->TxXferCount = 0x00U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmarx != NULL)
+ {
+ if (hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
*/
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hirda->hdmatx != NULL)
+ {
+ if (hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
/* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- tmp = (uint16_t*) hirda->pTxBuffPtr;
+ tmp = (uint16_t *) hirda->pTxBuffPtr;
hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
hirda->pTxBuffPtr += 2U;
}
@@ -1932,7 +2456,7 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
}
- if(--hirda->TxXferCount == 0U)
+ if (--hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
@@ -1951,7 +2475,7 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief Wraps up transmission in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -1966,30 +2490,36 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
return HAL_OK;
}
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint16_t uhdata;
/* Check that a Rx process is ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+ if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- tmp = (uint16_t*) hirda->pRxBuffPtr;
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ tmp = (uint16_t *) hirda->pRxBuffPtr;
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
hirda->pRxBuffPtr += 2U;
@@ -2002,7 +2532,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
}
else
{
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
+ if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
}
@@ -2012,7 +2542,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
}
}
- if(--hirda->RxXferCount == 0U)
+ if (--hirda->RxXferCount == 0U)
{
/* Disable the IRDA Data Register not empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
@@ -2026,7 +2556,13 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
return HAL_OK;
}
@@ -2040,7 +2576,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
/**
* @brief Configures the IRDA peripheral.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -2052,25 +2588,26 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
- /*-------------------------- IRDA CR2 Configuration ------------------------*/
+ /*-------------------------- USART CR2 Configuration ------------------------*/
/* Clear STOP[13:12] bits */
CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Clear M, PCE, PS, TE and RE bits */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE));
/* Configure the USART Word Length, Parity and mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
/* Write to USART CR1 */
- SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
+ SET_BIT(hirda->Instance->CR1, (hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode));
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Clear CTSE and RTSE bits */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
#if defined(USART6)
@@ -2082,7 +2619,7 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
if(hirda->Instance == USART1)
{
SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
- }
+ }
#endif /* USART6 */
else
{
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_iwdg.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_iwdg.c
index b7c518356eacc9852bbd637a10b3eceef21aa666..cb49dbf449b2ffc5c886edb37538fd80910e629d 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_iwdg.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_iwdg.c
@@ -36,7 +36,7 @@
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
@@ -48,13 +48,14 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
+ (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (+) Enable write access to configuration registers:
+ IWDG_PR and IWDG_RLR.
+ (+) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) wait for status flags to be reset"
+ (+) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@@ -72,29 +73,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -107,7 +92,7 @@
*/
#ifdef HAL_IWDG_MODULE_ENABLED
-/** @defgroup IWDG IWDG
+/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
@@ -118,9 +103,9 @@
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to HSI variation, we need to wait at
+ higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48U
+#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
@@ -135,8 +120,8 @@
*/
/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
+ * @brief Initialization and Start functions.
+ *
@verbatim
===============================================================================
##### Initialization and Start functions #####
@@ -164,7 +149,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
uint32_t tickstart;
/* Check the IWDG handle allocation */
- if(hiwdg == NULL)
+ if (hiwdg == NULL)
{
return HAL_ERROR;
}
@@ -174,10 +159,11 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
- /* Enable IWDG. LSI is turned on automaticaly */
+ /* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
- /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
+ /* Enable write access to IWDG_PR and IWDG_RLR registers by writing
+ 0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
@@ -188,9 +174,9 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
tickstart = HAL_GetTick();
/* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
+ while (hiwdg->Instance->SR != 0x00u)
{
- if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -207,9 +193,10 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
* @}
*/
+
/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -221,6 +208,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
* @{
*/
+
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_lptim.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_lptim.c
index f57afb2552799e33ee0e5d0324d9ba9439cc06df..1d43bb83c81f6f5102d1cf80aff644c967c7ee78 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_lptim.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_lptim.c
@@ -20,101 +20,132 @@
(#)Initialize the LPTIM low level resources by implementing the
HAL_LPTIM_MspInit():
- (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
- (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
+ (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
+ (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
(+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
(+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
(+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
(#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
configures mainly:
- (##) The instance: LPTIM1.
- (##) Clock: the counter clock.
+ (++) The instance: LPTIM1.
+ (++) Clock: the counter clock.
(+++) Source : it can be either the ULPTIM input (IN1) or one of
the internal clock; (APB, LSE or LSI).
(+++) Prescaler: select the clock divider.
- (##) UltraLowPowerClock : To be used only if the ULPTIM is selected
+ (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
as counter clock source.
(+++) Polarity: polarity of the active edge for the counter unit
if the ULPTIM input is selected.
(+++) SampleTime: clock sampling time to configure the clock glitch
filter.
- (##) Trigger: How the counter start.
+ (++) Trigger: How the counter start.
(+++) Source: trigger can be software or one of the hardware triggers.
(+++) ActiveEdge : only for hardware trigger.
(+++) SampleTime : trigger sampling time to configure the trigger
glitch filter.
- (##) OutputPolarity : 2 opposite polarities are possibles.
- (##) UpdateMode: specifies whether the update of the autoreload and
+ (++) OutputPolarity : 2 opposite polarities are possible.
+ (++) UpdateMode: specifies whether the update of the autoreload and
the compare values is done immediately or after the end of current
period.
(#)Six modes are available:
- (##) PWM Mode: To generate a PWM signal with specified period and pulse,
+ (++) PWM Mode: To generate a PWM signal with specified period and pulse,
call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
mode.
- (##) One Pulse Mode: To generate pulse with specified width in response
+ (++) One Pulse Mode: To generate pulse with specified width in response
to a stimulus, call HAL_LPTIM_OnePulse_Start() or
HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
- (##) Set once Mode: In this mode, the output changes the level (from
+ (++) Set once Mode: In this mode, the output changes the level (from
low level to high level if the output polarity is configured high, else
the opposite) when a compare match occurs. To start this mode, call
HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
interruption mode.
- (##) Encoder Mode: To use the encoder interface call
+ (++) Encoder Mode: To use the encoder interface call
HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
- interruption mode.
+ interruption mode. Only available for LPTIM1 instance.
- (##) Time out Mode: an active edge on one selected trigger input rests
+ (++) Time out Mode: an active edge on one selected trigger input rests
the counter. The first trigger event will start the timer, any
successive trigger event will reset the counter and the timer will
restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
- (##) Counter Mode: counter can be used to count external events on
+ (++) Counter Mode: counter can be used to count external events on
the LPTIM Input1 or it can be used to count internal clock cycles.
To start this mode, call HAL_LPTIM_Counter_Start() or
HAL_LPTIM_Counter_Start_IT() for interruption mode.
+
(#) User can stop any process by calling the corresponding API:
HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
already started in interruption mode.
- (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+ (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
+ @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+ default weak function.
+ @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ These functions allow to register/unregister following callbacks:
+
+ (+) MspInitCallback : LPTIM Base Msp Init Callback.
+ (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
+ (+) CompareMatchCallback : Compare match Callback.
+ (+) AutoReloadMatchCallback : Auto-reload match Callback.
+ (+) TriggerCallback : External trigger event detection Callback.
+ (+) CompareWriteCallback : Compare register write complete Callback.
+ (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
+ (+) DirectionUpCallback : Up-counting direction change Callback.
+ (+) DirectionDownCallback : Down-counting direction change Callback.
+
+ By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
+ all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init/DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+
+ When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * @attention
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ * ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -130,76 +161,26 @@
*/
#ifdef HAL_LPTIM_MODULE_ENABLED
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Types LPTIM Private Types
- * @{
- */
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Defines LPTIM Private Defines
- * @{
- */
-
-/**
- * @}
- */
+#if defined (LPTIM1)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+#define TIMEOUT 1000UL /* Timeout is 1s */
/* Private variables ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
- * @{
- */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
- * @{
- */
-
-/**
- * @}
- */
+/* Exported functions --------------------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
-/** @defgroup LPTIM_Group1 Initialization/de-initialization functions
+/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
@@ -208,27 +189,27 @@
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the LPTIM according to the specified parameters in the
- LPTIM_InitTypeDef and creates the associated handle.
+ LPTIM_InitTypeDef and initialize the associated handle.
(+) DeInitialize the LPTIM peripheral.
(+) Initialize the LPTIM MSP.
- (+) DeInitialize LPTIM MSP.
+ (+) DeInitialize the LPTIM MSP.
@endverbatim
* @{
*/
/**
- * @brief Initializes the LPTIM according to the specified parameters in the
- * LPTIM_InitTypeDef and creates the associated handle.
+ * @brief Initialize the LPTIM according to the specified parameters in the
+ * LPTIM_InitTypeDef and initialize the associated handle.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
{
- uint32_t tmpcfgr = 0U;
+ uint32_t tmpcfgr;
/* Check the LPTIM handle allocation */
- if(hlptim == NULL)
+ if (hlptim == NULL)
{
return HAL_ERROR;
}
@@ -238,13 +219,13 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
@@ -253,12 +234,26 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
- if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hlptim->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ LPTIM_ResetCallback(hlptim);
+
+ if (hlptim->MspInitCallback == NULL)
+ {
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ hlptim->MspInitCallback(hlptim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_LPTIM_MspInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
/* Change the LPTIM state */
@@ -267,18 +262,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
- tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
- /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
- LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));
+ /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
+ LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
tmpcfgr |= (hlptim->Init.Clock.Source |
@@ -287,13 +282,13 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
tmpcfgr |= (hlptim->Init.Trigger.Source |
@@ -312,14 +307,14 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
}
/**
- * @brief DeInitializes the LPTIM peripheral.
+ * @brief DeInitialize the LPTIM peripheral.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Check the LPTIM handle allocation */
- if(hlptim == NULL)
+ if (hlptim == NULL)
{
return HAL_ERROR;
}
@@ -330,8 +325,18 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ if (hlptim->MspDeInitCallback == NULL)
+ {
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hlptim->MspDeInitCallback(hlptim);
+#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_LPTIM_MspDeInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_RESET;
@@ -344,7 +349,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
}
/**
- * @brief Initializes the LPTIM MSP.
+ * @brief Initialize the LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
@@ -352,13 +357,14 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes LPTIM MSP.
+ * @brief DeInitialize LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
@@ -366,7 +372,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspDeInit could be implemented in the user file
*/
}
@@ -375,7 +382,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
* @}
*/
-/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
+/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
@@ -402,11 +409,11 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
*/
/**
- * @brief Starts the LPTIM PWM generation.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -418,7 +425,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
@@ -436,15 +443,15 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM PWM generation.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM PWM generation.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -453,24 +460,24 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM PWM generation in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
*/
@@ -482,7 +489,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
@@ -500,7 +507,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
@@ -519,15 +526,15 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM PWM generation in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM PWM generation in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -536,12 +543,12 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
- /* Disable Autoreload write complete interrupt */
+ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
/* Disable Compare write complete interrupt */
@@ -554,25 +561,25 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM One pulse generation.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -584,7 +591,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
@@ -598,19 +605,19 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
- /* Start timer in continuous mode */
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM One pulse generation.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM One pulse generation.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -619,24 +626,24 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM One pulse generation in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -648,7 +655,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
@@ -666,7 +673,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
@@ -681,19 +688,19 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
- /* Start timer in continuous mode */
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM One pulse generation in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM One pulse generation in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -702,7 +709,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -720,25 +727,25 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM in Set once mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM in Set once mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -750,7 +757,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
@@ -764,19 +771,19 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
- /* Start timer in single mode */
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM Set once mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM Set once mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -785,24 +792,24 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the LPTIM Set once mode in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -814,7 +821,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
assert_param(IS_LPTIM_PULSE(Pulse));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
@@ -832,7 +839,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then enable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
@@ -847,19 +854,19 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
- /* Start timer in single mode */
+ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the LPTIM Set once mode in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the LPTIM Set once mode in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -868,7 +875,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -886,29 +893,29 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
/* If external trigger source is used, then disable external trigger interrupt */
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Disable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Encoder interface.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Encoder interface.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
- uint32_t tmpcfgr = 0U;
+ uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -918,7 +925,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
@@ -945,15 +952,15 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Encoder interface.
- * @param hlptim LPTIM handle
+ * @brief Stop the Encoder interface.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -962,7 +969,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -971,22 +978,22 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Encoder interface in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
- uint32_t tmpcfgr = 0U;
+ uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -996,7 +1003,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Configure edge sensitivity for encoder mode */
/* Get the LPTIMx CFGR value */
@@ -1030,15 +1037,15 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Encoder interface in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Encoder interface in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1047,7 +1054,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -1062,20 +1069,20 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Timeout function. The first trigger event will start the
- * timer, any successive trigger event will reset the counter and
- * the timer restarts.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Timeout function.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1087,7 +1094,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
assert_param(IS_LPTIM_PULSE(Timeout));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
@@ -1105,15 +1112,15 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Timeout function.
- * @param hlptim LPTIM handle
+ * @brief Stop the Timeout function.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1122,7 +1129,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -1131,20 +1138,20 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Timeout function in interrupt mode. The first trigger
- * event will start the timer, any successive trigger event will reset
- * the counter and the timer restarts.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Timeout function in interrupt mode.
+ * @note The first trigger event will start the timer, any successive
+ * trigger event will reset the counter and the timer restarts.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1156,14 +1163,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
assert_param(IS_LPTIM_PULSE(Timeout));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
- /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
@@ -1183,15 +1187,15 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Timeout function in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Timeout function in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1200,10 +1204,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
@@ -1218,16 +1219,16 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Counter mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Counter mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1238,10 +1239,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
assert_param(IS_LPTIM_PERIOD(Period));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1259,15 +1260,15 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Counter mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Counter mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1276,22 +1277,22 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Starts the Counter mode in interrupt mode.
- * @param hlptim LPTIM handle
- * @param Period Specifies the Autoreload value.
+ * @brief Start the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1302,16 +1303,13 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
assert_param(IS_LPTIM_PERIOD(Period));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
- /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
-
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
- if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@@ -1335,15 +1333,15 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the Counter mode in interrupt mode.
- * @param hlptim LPTIM handle
+ * @brief Stop the Counter mode in interrupt mode.
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1352,10 +1350,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
- hlptim->State= HAL_LPTIM_STATE_BUSY;
-
- /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
- __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
+ hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
@@ -1370,7 +1365,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
/* Change the TIM state*/
- hlptim->State= HAL_LPTIM_STATE_READY;
+ hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -1380,7 +1375,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @}
*/
-/** @defgroup LPTIM_Group3 LPTIM Read operation functions
+/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
* @brief Read operation functions.
*
@verbatim
@@ -1396,39 +1391,39 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
*/
/**
- * @brief This function returns the current counter value.
+ * @brief Return the current counter value.
* @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->CNT);
}
/**
- * @brief This function return the current Autoreload (Period) value.
+ * @brief Return the current Autoreload (Period) value.
* @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->ARR);
}
/**
- * @brief This function return the current Compare (Pulse) value.
+ * @brief Return the current Compare (Pulse) value.
* @param hlptim LPTIM handle
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->CMP);
@@ -1438,212 +1433,470 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
* @}
*/
-
-
-/** @defgroup LPTIM_Group4 LPTIM IRQ handler
+/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
* @brief LPTIM IRQ handler.
*
@verbatim
==============================================================================
- ##### LPTIM IRQ handler #####
+ ##### LPTIM IRQ handler and callbacks #####
==============================================================================
-[..] This section provides LPTIM IRQ handler function.
+[..] This section provides LPTIM IRQ handler and callback functions called within
+ the IRQ handler:
+ (+) LPTIM interrupt request handler
+ (+) Compare match Callback
+ (+) Auto-reload match Callback
+ (+) External trigger event detection Callback
+ (+) Compare register write complete Callback
+ (+) Auto-reload register write complete Callback
+ (+) Up-counting direction change Callback
+ (+) Down-counting direction change Callback
@endverbatim
* @{
*/
/**
- * @brief This function handles LPTIM interrupt request.
+ * @brief Handle LPTIM interrupt request.
* @param hlptim LPTIM handle
* @retval None
*/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
{
/* Compare match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
+ {
/* Clear Compare match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
+
/* Compare match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareMatchCallback(hlptim);
+#else
HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Autoreload match interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
+ {
/* Clear Autoreload match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
+
/* Autoreload match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadMatchCallback(hlptim);
+#else
HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Trigger detected interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
+ {
/* Clear Trigger detected flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
+
/* Trigger detected callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->TriggerCallback(hlptim);
+#else
HAL_LPTIM_TriggerCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Compare write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
+ {
/* Clear Compare write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
+
/* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareWriteCallback(hlptim);
+#else
HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Autoreload write interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
+ {
/* Clear Autoreload write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
+
/* Autoreload write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadWriteCallback(hlptim);
+#else
HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Direction counter changed from Down to Up interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
+ {
/* Clear Direction counter changed from Down to Up flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
+
/* Direction counter changed from Down to Up Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionUpCallback(hlptim);
+#else
HAL_LPTIM_DirectionUpCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Direction counter changed from Up to Down interrupt */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
- {
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
- {
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
+ {
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
+ {
/* Clear Direction counter changed from Up to Down flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
+
/* Direction counter changed from Up to Down Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionDownCallback(hlptim);
+#else
HAL_LPTIM_DirectionDownCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
- __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
}
/**
- * @brief Compare match callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Compare match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
*/
}
/**
- * @brief Autoreload match callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Autoreload match callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
*/
}
/**
- * @brief Trigger detected callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Trigger detected callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_TriggerCallback could be implemented in the user file
*/
}
/**
- * @brief Compare write callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Compare write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
*/
}
/**
- * @brief Autoreload write callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Autoreload write callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
*/
}
/**
- * @brief Direction counter changed from Down to Up callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Direction counter changed from Down to Up callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
*/
}
/**
- * @brief Direction counter changed from Up to Down callback in non blocking mode
- * @param hlptim LPTIM handle
+ * @brief Direction counter changed from Up to Down callback in non-blocking mode.
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
*/
}
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID,
+ pLPTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a LPTIM callback
+ * LLPTIM callback is redirected to the weak predefined callback
+ * @param hlptim LPTIM handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
+ * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
+ HAL_LPTIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if (hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
+ break;
+
+ case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1663,12 +1916,13 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
*/
/**
- * @brief Returns the LPTIM state.
+ * @brief Return the LPTIM handle state.
* @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
{
+ /* Return LPTIM handle state */
return hlptim->State;
}
@@ -1681,7 +1935,150 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
* @}
*/
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @retval None
+ */
+static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
+{
+ /* Reset the LPTIM callback to the legacy weak callbacks */
+ lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */
+ lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */
+ lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */
+ lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
+ lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
+ lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
+ lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief Disable LPTIM HW instance.
+ * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
+ * the configuration information for LPTIM module.
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @retval None
+ */
+void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
+{
+ uint32_t tmpclksource = 0;
+ uint32_t tmpIER;
+ uint32_t tmpCFGR;
+ uint32_t tmpCMP;
+ uint32_t tmpARR;
+ uint32_t tmpOR;
+
+ __disable_irq();
+
+ /*********** Save LPTIM Config ***********/
+ /* Save LPTIM source clock */
+ switch ((uint32_t)lptim->Instance)
+ {
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ default:
+ break;
+ }
+
+ /* Save LPTIM configuration registers */
+ tmpIER = lptim->Instance->IER;
+ tmpCFGR = lptim->Instance->CFGR;
+ tmpCMP = lptim->Instance->CMP;
+ tmpARR = lptim->Instance->ARR;
+ tmpOR = lptim->Instance->OR;
+
+ /*********** Reset LPTIM ***********/
+ switch ((uint32_t)lptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ default:
+ break;
+ }
+
+ /*********** Restore LPTIM Config ***********/
+ uint32_t Ref_Time;
+ uint32_t Time_Elapsed;
+
+ if ((tmpCMP != 0UL) || (tmpARR != 0UL))
+ {
+ /* Force LPTIM source kernel clock from APB */
+ switch ((uint32_t)lptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
+ }
+
+ if (tmpCMP != 0UL)
+ {
+ /* Restore CMP register (LPTIM should be enabled first) */
+ lptim->Instance->CR |= LPTIM_CR_ENABLE;
+ lptim->Instance->CMP = tmpCMP;
+ /* Polling on CMP write ok status after above restore operation */
+ Ref_Time = HAL_GetTick();
+ do
+ {
+ Time_Elapsed = HAL_GetTick() - Ref_Time;
+ } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT));
+
+ __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK);
+ }
+
+ if (tmpARR != 0UL)
+ {
+ /* Restore ARR register (LPTIM should be enabled first) */
+ lptim->Instance->CR |= LPTIM_CR_ENABLE;
+ lptim->Instance->ARR = tmpARR;
+ /* Polling on ARR write ok status after above restore operation */
+ Ref_Time = HAL_GetTick();
+ do
+ {
+ Time_Elapsed = HAL_GetTick() - Ref_Time;
+ } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT));
+
+ __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK);
+ }
+
+ /* Restore LPTIM source kernel clock */
+ switch ((uint32_t)lptim->Instance)
+ {
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Restore configuration registers (LPTIM should be disabled first) */
+ lptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
+ lptim->Instance->IER = tmpIER;
+ lptim->Instance->CFGR = tmpCFGR;
+ lptim->Instance->OR = tmpOR;
+
+ __enable_irq();
+}
+/**
+ * @}
+ */
+#endif /* LPTIM1 */
+
#endif /* HAL_LPTIM_MODULE_ENABLED */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc.c
index 03bfa346594ac8a70289509b759071cdb685491a..6620eb6016a8c87e610f1f300bec3ca973fd13d1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc.c
@@ -40,18 +40,18 @@
value, the window size, the window position and the layer start address
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
- HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
+ HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
- (#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload.
+ (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
- then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Reload”
-
- After calling the “_NoReload” functions to set different color/format/layer settings,
- the program can call the function “HAL_LTDC_Reload” To apply(Reload) these settings.
- Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
- set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
- Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
- set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
+ then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
+
+ After calling the _NoReload functions to set different color/format/layer settings,
+ the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
+ Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
+ an immediate reload is required.
+ Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
+ the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
@@ -64,11 +64,63 @@
(+) __HAL_LTDC_ENABLE: Enable the LTDC.
(+) __HAL_LTDC_DISABLE: Disable the LTDC.
- (+) __HAL_LTDC_LAYER_ENABLE: Enable a LTDC Layer.
- (+) __HAL_LTDC_LAYER_DISABLE: Disable a LTDC Layer.
+ (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
+ (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
+ (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration.
+ (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
(+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
(+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
(+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+ (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
+
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_LTDC_RegisterCallback() to register a callback.
+
+ Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback.
+ (+) ReloadEventCallback : LTDC Reload Event Callback.
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit.
+ (+) MspDeInitCallback : LTDC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) LineEventCallback : LTDC Line Event Callback.
+ (+) ReloadEventCallback : LTDC Reload Event Callback.
+ (+) ErrorCallback : LTDC Error Callback
+ (+) MspInitCallback : LTDC MspInit.
+ (+) MspDeInitCallback : LTDC MspDeInit.
+
+ By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit
+ or HAL_LTDC_Init function.
+
+ When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
@@ -77,29 +129,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -107,17 +143,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
+#ifdef HAL_LTDC_MODULE_ENABLED
+#if defined (LTDC)
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
-#ifdef HAL_LTDC_MODULE_ENABLED
-
-#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -132,8 +168,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
*/
/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -154,10 +190,10 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
- if(hltdc == NULL)
+ if (hltdc == NULL)
{
return HAL_ERROR;
}
@@ -177,21 +213,41 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
- if(hltdc->State == HAL_LTDC_STATE_RESET)
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hltdc->Lock = HAL_UNLOCKED;
+
+ /* Reset the LTDC callback to the legacy weak callbacks */
+ hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
+ hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
+ hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hltdc->MspInitCallback == NULL)
+ {
+ hltdc->MspInitCallback = HAL_LTDC_MspInit;
+ }
+ /* Init the low level hardware */
+ hltdc->MspInitCallback(hltdc);
+ }
+#else
+ if (hltdc->State == HAL_LTDC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
- hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
- hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
+ hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
+ hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
@@ -243,8 +299,17 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
{
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ if (hltdc->MspDeInitCallback == NULL)
+ {
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hltdc->MspDeInitCallback(hltdc);
+#else
/* DeInit the low level hardware */
HAL_LTDC_MspDeInit(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
@@ -264,7 +329,7 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
@@ -280,7 +345,7 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
@@ -290,13 +355,195 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
*/
}
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User LTDC Callback
+ * To be used instead of the weak predefined callback
+ * @param hltdc ltdc handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+ * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+ * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ if (hltdc->State == HAL_LTDC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_LINE_EVENT_CB_ID :
+ hltdc->LineEventCallback = pCallback;
+ break;
+
+ case HAL_LTDC_RELOAD_EVENT_CB_ID :
+ hltdc->ReloadEventCallback = pCallback;
+ break;
+
+ case HAL_LTDC_ERROR_CB_ID :
+ hltdc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hltdc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an LTDC Callback
+ * LTDC callabck is redirected to the weak predefined callback
+ * @param hltdc ltdc handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
+ * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
+ * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hltdc);
+
+ if (hltdc->State == HAL_LTDC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_LINE_EVENT_CB_ID :
+ hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
+ break;
+
+ case HAL_LTDC_RELOAD_EVENT_CB_ID :
+ hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
+ break;
+
+ case HAL_LTDC_ERROR_CB_ID :
+ hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hltdc->State == HAL_LTDC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LTDC_MSPINIT_CB_ID :
+ hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
+ break;
+
+ case HAL_LTDC_MSPDEINIT_CB_ID :
+ hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hltdc);
+
+ return status;
+}
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -319,7 +566,7 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
uint32_t itsources = READ_REG(hltdc->Instance->IER);
/* Transfer Error Interrupt management ***************************************/
- if(((isrflags & LTDC_ISR_TERRIF) != RESET) && ((itsources & LTDC_IER_TERRIE) != RESET))
+ if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
@@ -337,11 +584,17 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
__HAL_UNLOCK(hltdc);
/* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hltdc->ErrorCallback(hltdc);
+#else
+ /* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
- if(((isrflags & LTDC_ISR_FUIF) != RESET) && ((itsources & LTDC_IER_FUIE) != RESET))
+ if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
@@ -359,11 +612,17 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
__HAL_UNLOCK(hltdc);
/* Transfer error Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ hltdc->ErrorCallback(hltdc);
+#else
+ /* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
- if(((isrflags & LTDC_ISR_LIF) != RESET) && ((itsources & LTDC_IER_LIE) != RESET))
+ if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
@@ -378,11 +637,17 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
__HAL_UNLOCK(hltdc);
/* Line interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered Line Event callback */
+ hltdc->LineEventCallback(hltdc);
+#else
+ /*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
- if(((isrflags & LTDC_ISR_RRIF) != RESET) && ((itsources & LTDC_IER_RRIE) != RESET))
+ if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
@@ -396,8 +661,14 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
/* Process unlocked */
__HAL_UNLOCK(hltdc);
- /* Register reload interrupt Callback */
+ /* Reload interrupt Callback */
+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
+ /*Call registered reload Event callback */
+ hltdc->ReloadEventCallback(hltdc);
+#else
+ /*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
@@ -454,8 +725,8 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
*/
/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -502,7 +773,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
- assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
@@ -579,10 +850,9 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t
*/
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
{
- uint32_t tmp = 0U;
- uint32_t counter = 0U;
- uint32_t pcounter = 0U;
-
+ uint32_t tmp;
+ uint32_t counter;
+ uint32_t *pcolorlut = pCLUT;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -592,18 +862,18 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
- for(counter = 0U; (counter < CLUTSize); counter++)
+ for (counter = 0U; (counter < CLUTSize); counter++)
{
- if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
+ if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
{
- tmp = (((counter + 16U*counter) << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
+ tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
else
{
- tmp = ((counter << 24U) | ((uint32_t)(*pCLUT) & 0xFFU) | ((uint32_t)(*pCLUT) & 0xFF00U) | ((uint32_t)(*pCLUT) & 0xFF0000U));
+ tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
- pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);
- pCLUT = (uint32_t *)pcounter;
+
+ pcolorlut++;
/* Specifies the C-LUT address and RGB value */
LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
@@ -1068,9 +1338,9 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
- uint32_t tmp = 0U;
- uint32_t pitchUpdate = 0U;
- uint32_t pixelFormat = 0U;
+ uint32_t tmp;
+ uint32_t pitchUpdate;
+ uint32_t pixelFormat;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -1084,7 +1354,7 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
@@ -1092,10 +1362,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc
{
tmp = 3U;
}
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
@@ -1226,7 +1496,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
- assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
+ assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
@@ -1241,8 +1511,6 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1297,8 +1565,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1349,8 +1615,6 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc,
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1394,8 +1658,6 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1439,8 +1701,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1483,8 +1743,6 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1510,9 +1768,9 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
- uint32_t tmp = 0U;
- uint32_t pitchUpdate = 0U;
- uint32_t pixelFormat = 0U;
+ uint32_t tmp;
+ uint32_t pitchUpdate;
+ uint32_t pixelFormat;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -1526,7 +1784,7 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
- if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
@@ -1534,10 +1792,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
{
tmp = 3U;
}
- else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
@@ -1554,8 +1812,6 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1592,8 +1848,6 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc,
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1627,8 +1881,6 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc,
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1662,8 +1914,6 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1697,8 +1947,6 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1732,8 +1980,6 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
- /* Do not set the Immediate Reload */
-
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@@ -1748,8 +1994,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3
*/
/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1778,8 +2024,8 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
* @brief Return the LTDC handle error code.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
-* @retval LTDC Error Code
-*/
+ * @retval LTDC Error Code
+ */
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
{
return hltdc->ErrorCode;
@@ -1808,9 +2054,9 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
- uint32_t tmp = 0U;
- uint32_t tmp1 = 0U;
- uint32_t tmp2 = 0U;
+ uint32_t tmp;
+ uint32_t tmp1;
+ uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
@@ -1845,7 +2091,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
- if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
+ if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
@@ -1853,10 +2099,10 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
{
tmp = 3U;
}
- else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
- (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
+ else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
@@ -1868,7 +2114,6 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
-
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
@@ -1880,15 +2125,18 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/**
* @}
*/
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-#endif /* HAL_LTDC_MODULE_ENABLED */
+
/**
* @}
*/
+
/**
* @}
*/
+#endif /* LTDC */
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc_ex.c
index 296adfa80652980dd4ab41cac9fd01ec36c37729..af7558746b89d6fc76d01e96631d63fbedd44e5d 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_ltdc_ex.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -39,12 +23,15 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+
+#if defined (LTDC) && defined (DSI)
+
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
-#ifdef HAL_LTDC_MODULE_ENABLED
+#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -58,8 +45,8 @@
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
@@ -70,7 +57,7 @@
@endverbatim
* @{
*/
-#if defined(STM32F469xx) || defined(STM32F479xx)
+
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
@@ -81,7 +68,7 @@
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
@@ -117,7 +104,7 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
@@ -138,7 +125,6 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
return HAL_OK;
}
-#endif /* STM32F469xx || STM32F479xx */
/**
* @}
@@ -148,11 +134,14 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
* @}
*/
-#endif /* HAL_DCMI_MODULE_ENABLED */
+#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
+
/**
* @}
*/
+#endif /* LTDC && DSI */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_mmc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_mmc.c
index d23f48b8904ad6fa43ea86197eb992c5979e88cc..57e33db949bcde3fb8bfc793971749cc612e42cf 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_mmc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_mmc.c
@@ -192,33 +192,63 @@
[..]
(@) You can refer to the MMC HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : MMC MspInit.
+ (+) MspDeInitCallback : MMC MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
+ and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL__RegisterCallback before calling @ref HAL_MMC_DeInit
+ or @ref HAL_MMC_Init function.
+
+ When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -321,8 +351,24 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_MMC_STATE_RESET only */
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+
+ if(hmmc->MspInitCallback == NULL)
+ {
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hmmc->MspInitCallback(hmmc);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
+#endif
}
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -420,8 +466,18 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
/* Set SD power state to off */
MMC_PowerOFF(hmmc);
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ if(hmmc->MspDeInitCallback == NULL)
+ {
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hmmc->MspDeInitCallback(hmmc);
+#else
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
+#endif
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
@@ -1084,7 +1140,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
@@ -1203,7 +1259,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
hmmc->Instance->DCTRL = 0U;
/* Enable MMC Error interrupts */
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
@@ -1412,7 +1468,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
@@ -1422,11 +1482,19 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
hmmc->State = HAL_MMC_STATE_READY;
if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->RxCpltCallback(hmmc);
+#else
HAL_MMC_RxCpltCallback(hmmc);
+#endif
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->TxCpltCallback(hmmc);
+#else
HAL_MMC_TxCpltCallback(hmmc);
+#endif
}
}
else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
@@ -1437,7 +1505,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
@@ -1448,7 +1520,11 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->TxCpltCallback(hmmc);
+#else
HAL_MMC_TxCpltCallback(hmmc);
+#endif
}
}
}
@@ -1591,14 +1667,22 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->AbortCpltCallback(hmmc);
+#else
HAL_MMC_AbortCallback(hmmc);
+#endif
}
}
else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
#endif /* SDIO_STA_STBITERR */
@@ -1685,6 +1769,180 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
*/
}
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User MMC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackID : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = pCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = pCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = pCallback;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+
+/**
+ * @brief Unregister a User MMC Callback
+ * MMC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hmmc : MMC handle
+ * @param CallbackID : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
+ * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
+ * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
+ * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
+ * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
+ * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hmmc);
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_TX_CPLT_CB_ID :
+ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
+ break;
+ case HAL_MMC_RX_CPLT_CB_ID :
+ hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
+ break;
+ case HAL_MMC_ERROR_CB_ID :
+ hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
+ break;
+ case HAL_MMC_ABORT_CB_ID :
+ hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
+ break;
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_MMC_MSP_INIT_CB_ID :
+ hmmc->MspInitCallback = HAL_MMC_MspInit;
+ break;
+ case HAL_MMC_MSP_DEINIT_CB_ID :
+ hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmmc);
+ return status;
+}
+#endif
+
/**
* @}
@@ -2233,7 +2491,11 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
@@ -2246,7 +2508,11 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hmmc->State = HAL_MMC_STATE_READY;
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->RxCpltCallback(hmmc);
+#else
HAL_MMC_RxCpltCallback(hmmc);
+#endif
}
/**
@@ -2278,7 +2544,12 @@ static void MMC_DMAError(DMA_HandleTypeDef *hdma)
hmmc->State= HAL_MMC_STATE_READY;
}
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
+
}
/**
@@ -2312,7 +2583,11 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
}
@@ -2349,7 +2624,11 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
}
else
{
+#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1)
+ hmmc->ErrorCallback(hmmc);
+#else
HAL_MMC_ErrorCallback(hmmc);
+#endif
}
}
}
@@ -2541,7 +2820,7 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
*/
static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count = 0U;
+ uint32_t count;
uint32_t* tmp;
tmp = (uint32_t*)hmmc->pRxBuffPtr;
@@ -2565,7 +2844,7 @@ static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
*/
static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
- uint32_t count = 0U;
+ uint32_t count;
uint32_t* tmp;
tmp = (uint32_t*)hmmc->pTxBuffPtr;
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_msp_template.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_msp_template.c
index 04ee2adb3564ae15c086cdcfe867b2f8f82cd17c..003ea4cc7757e0584e36742f79aeb07396a650d8 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_msp_template.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_msp_template.c
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nand.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nand.c
index 65c7b64fd061737806f1c5434475a7f5ebc7428a..a4dd9b1e11bae336f43873b9e2d21bb2eb87e9a1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nand.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nand.c
@@ -52,33 +52,56 @@
If a NAND flash device contains different operations and/or implementations,
it should be implemented separately.
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NAND MspInit.
+ (+) MspDeInitCallback : NAND MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
+ and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
+ or @ref HAL_NAND_Init function.
+
+ When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -162,8 +185,20 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if(hnand->MspInitCallback == NULL)
+ {
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ }
+ hnand->ItCallback = HAL_NAND_ITCallback;
+
+ /* Init the low level hardware */
+ hnand->MspInitCallback(hnand);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
+#endif
}
/* Initialize NAND control Interface */
@@ -192,8 +227,18 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ if(hnand->MspDeInitCallback == NULL)
+ {
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnand->MspDeInitCallback(hnand);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
+#endif
/* Configure the NAND registers with their reset values */
FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
@@ -250,7 +295,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
@@ -260,7 +309,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
@@ -270,7 +323,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
@@ -280,7 +337,11 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
{
/* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+ hnand->ItCallback(hnand);
+#else
HAL_NAND_ITCallback(hnand);
+#endif
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
@@ -1659,6 +1720,143 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
return (status);
}
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NAND Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if(hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NAND Callback
+ * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnand : NAND handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
+ * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
+ * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hnand);
+
+ if(hnand->State == HAL_NAND_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+ return status;
+}
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nor.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nor.c
index 962685aee5bb0d24c85b9848e0dc830ad0554add..3d423f915a6d4e97226ca1520dcf01a0bf89516c 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nor.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_nor.c
@@ -49,33 +49,56 @@
(+) NOR_WRITE : NOR memory write data to specified address
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : NOR MspInit.
+ (+) MspDeInitCallback : NOR MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
+ and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
+ or @ref HAL_NOR_Init function.
+
+ When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -189,8 +212,19 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
{
/* Allocate lock resource and initialize it */
hnor->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if(hnor->MspInitCallback == NULL)
+ {
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hnor->MspInitCallback(hnor);
+#else
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
}
/* Initialize NOR control Interface */
@@ -229,8 +263,18 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+ if(hnor->MspDeInitCallback == NULL)
+ {
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hnor->MspDeInitCallback(hnor);
+#else
/* De-Initialize the low level hardware (MSP) */
HAL_NOR_MspDeInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/* Configure the NOR registers with their reset values */
FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
@@ -863,6 +907,105 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
return HAL_OK;
}
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User NOR Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+
+/**
+ * @brief Unregister a User NOR Callback
+ * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * @param hnor : NOR handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
+ * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_NOR_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hnor);
+
+ state = hnor->State;
+ if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+ return status;
+}
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pccard.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pccard.c
index a7f3f02c429e90e835cee0f8c7d5f9512b4c7dd7..205776002d9a17da984f09ae87a4768233b9fba2 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pccard.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pccard.c
@@ -44,33 +44,56 @@
operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_PCCARD_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : PCCARD MspInit.
+ (+) MspDeInitCallback : PCCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_PCCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : PCCARD MspInit.
+ (+) MspDeInitCallback : PCCARD MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_PCCARD_Init
+ and @ref HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_PCCARD_Init and @ref HAL_PCCARD_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_PCCARD_RegisterCallback before calling @ref HAL_PCCARD_DeInit
+ or @ref HAL_PCCARD_Init function.
+
+ When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -150,8 +173,19 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
{
/* Allocate lock resource and initialize it */
hpccard->Lock = HAL_UNLOCKED;
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ if(hpccard->MspInitCallback == NULL)
+ {
+ hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+ }
+ hpccard->ItCallback = HAL_PCCARD_ITCallback;
+
+ /* Init the low level hardware */
+ hpccard->MspInitCallback(hpccard);
+#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
+#endif
}
/* Initialize the PCCARD state */
@@ -187,8 +221,18 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
*/
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
{
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ if(hpccard->MspDeInitCallback == NULL)
+ {
+ hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hpccard->MspDeInitCallback(hpccard);
+#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
+#endif
/* Configure the PCCARD registers with their reset values */
FMC_PCCARD_DeInit(hpccard->Instance);
@@ -572,7 +616,11 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
{
/* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ hpccard->ItCallback(hpccard);
+#else
HAL_PCCARD_ITCallback(hpccard);
+#endif
/* Clear PCCARD interrupt Rising edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
@@ -582,7 +630,11 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
{
/* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ hpccard->ItCallback(hpccard);
+#else
HAL_PCCARD_ITCallback(hpccard);
+#endif
/* Clear PCCARD interrupt Level pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
@@ -592,7 +644,11 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
{
/* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ hpccard->ItCallback(hpccard);
+#else
HAL_PCCARD_ITCallback(hpccard);
+#endif
/* Clear PCCARD interrupt Falling edge pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
@@ -602,7 +658,11 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
{
/* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+ hpccard->ItCallback(hpccard);
+#else
HAL_PCCARD_ITCallback(hpccard);
+#endif
/* Clear PCCARD interrupt FIFO empty pending bit */
__FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
@@ -624,6 +684,142 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
*/
}
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User PCCARD Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hpccard : PCCARD handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
+ * @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
+ * @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpccard);
+
+ if(hpccard->State == HAL_PCCARD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_PCCARD_MSP_INIT_CB_ID :
+ hpccard->MspInitCallback = pCallback;
+ break;
+ case HAL_PCCARD_MSP_DEINIT_CB_ID :
+ hpccard->MspDeInitCallback = pCallback;
+ break;
+ case HAL_PCCARD_IT_CB_ID :
+ hpccard->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_PCCARD_MSP_INIT_CB_ID :
+ hpccard->MspInitCallback = pCallback;
+ break;
+ case HAL_PCCARD_MSP_DEINIT_CB_ID :
+ hpccard->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+ return status;
+}
+
+/**
+ * @brief Unregister a User PCCARD Callback
+ * PCCARD Callback is redirected to the weak (surcharged) predefined callback
+ * @param hpccard : PCCARD handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
+ * @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
+ * @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpccard);
+
+ if(hpccard->State == HAL_PCCARD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_PCCARD_MSP_INIT_CB_ID :
+ hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+ break;
+ case HAL_PCCARD_MSP_DEINIT_CB_ID :
+ hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+ break;
+ case HAL_PCCARD_IT_CB_ID :
+ hpccard->ItCallback = HAL_PCCARD_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_PCCARD_MSP_INIT_CB_ID :
+ hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+ break;
+ case HAL_PCCARD_MSP_DEINIT_CB_ID :
+ hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+ return status;
+}
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd.c
index 5fd348cf73593e98037e1a783656fc7f6b0a4e06..cc5081ffebdd69a11a05b20e685b051e844bd635 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd.c
@@ -43,29 +43,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -83,11 +67,9 @@
*/
#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -105,7 +87,11 @@
/** @defgroup PCD_Private_Functions PCD Private Functions
* @{
*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
@@ -136,10 +122,11 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
- uint32_t i = 0U;
+ USB_OTG_GlobalTypeDef *USBx;
+ uint8_t i;
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
@@ -147,71 +134,106 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+ USBx = hpcd->Instance;
+
+ if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+ if (hpcd->MspInitCallback == NULL)
+ {
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hpcd->MspInitCallback(hpcd);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+ }
+
hpcd->State = HAL_PCD_STATE_BUSY;
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
+ /* Disable DMA mode for FS instance */
+ if ((USBx->CID & (0x1U << 8)) == 0U)
+ {
+ hpcd->Init.dma_enable = 0U;
+ }
/* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
-
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
-
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
-
- /* Init endpoints structures */
- for (i = 0U; i < 15U; i++)
- {
- /* Init ep structure */
- hpcd->IN_ep[i].is_in = 1U;
- hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is activated */
- hpcd->IN_ep[i].type = EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0U;
- hpcd->IN_ep[i].xfer_buff = 0U;
- hpcd->IN_ep[i].xfer_len = 0U;
- }
-
- for (i = 0U; i < 15U; i++)
- {
- hpcd->OUT_ep[i].is_in = 0U;
- hpcd->OUT_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
- /* Control until ep is activated */
- hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0U;
- hpcd->OUT_ep[i].xfer_buff = 0U;
- hpcd->OUT_ep[i].xfer_len = 0U;
-
- hpcd->Instance->DIEPTXF[i] = 0U;
- }
-
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
-
- hpcd->State= HAL_PCD_STATE_READY;
-
-#ifdef USB_OTG_GLPMCFG_LPMEN
- /* Activate LPM */
- if (hpcd->Init.lpm_enable == 1U)
- {
- HAL_PCDEx_ActivateLPM(hpcd);
- }
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-
-#ifdef USB_OTG_GCCFG_BCDEN
- /* Activate Battery charging */
- if (hpcd->Init.battery_charging_enable == 1U)
- {
- HAL_PCDEx_ActivateBCD(hpcd);
- }
-#endif /* USB_OTG_GCCFG_BCDEN */
-
- USB_DevDisconnect (hpcd->Instance);
- return HAL_OK;
+ __HAL_PCD_DISABLE(hpcd);
+
+ /*Init the Core (common init.) */
+ if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Force Device Mode*/
+ (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ hpcd->IN_ep[i].tx_fifo_num = i;
+ /* Control until ep is activated */
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+
+ /* Init Device */
+ if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hpcd->USB_Address = 0U;
+ hpcd->State = HAL_PCD_STATE_READY;
+ #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1U)
+ {
+ (void)HAL_PCDEx_ActivateLPM(hpcd);
+ }
+ #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+ (void)USB_DevDisconnect(hpcd->Instance);
+
+ return HAL_OK;
}
/**
@@ -222,7 +244,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
@@ -230,10 +252,20 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
- HAL_PCD_Stop(hpcd);
+ (void)HAL_PCD_Stop(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ if (hpcd->MspDeInitCallback == NULL)
+ {
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
/* DeInit the low level hardware */
+ hpcd->MspDeInitCallback(hpcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
hpcd->State = HAL_PCD_STATE_RESET;
@@ -249,24 +281,687 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes PCD MSP.
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB PCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = pCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = pCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB PCD Callback
+ * USB PCD callabck is redirected to the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data OUT Stage Callback
+ * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data OUT Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data IN Stage Callback
+ * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data IN Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data IN Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso OUT incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso OUT incomplete Callback
+ * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso IN incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso IN incomplete Callback
+ * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD BCD Callback
+ * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD BCD Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD BCD Callback
+ * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD LPM Callback
+ * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD LPM Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD LPM Callback
+ * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
- * @retval None
+ * @retval HAL status
*/
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PCD_MspDeInit could be implemented in the user file
- */
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
@@ -288,21 +983,33 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Start The USB OTG Device.
+ * @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
__HAL_LOCK(hpcd);
- USB_DevConnect (hpcd->Instance);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+ if ((hpcd->Init.battery_charging_enable == 1U) &&
+ (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+ {
+ /* Enable USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+ (void)USB_DevConnect(hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Stop The USB OTG Device.
+ * @brief Stop the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -310,12 +1017,19 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
- USB_StopDevice(hpcd->Instance);
- USB_DevDisconnect(hpcd->Instance);
+
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ {
+ __HAL_UNLOCK(hpcd);
+ return HAL_ERROR;
+ }
+
+ (void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Handles PCD interrupt request.
* @param hpcd PCD handle
@@ -324,101 +1038,94 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- uint32_t i = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
- uint32_t fifoemptymsk = 0U, temp = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i, ep_intr, epint, epnum;
+ uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
- uint32_t hclk = 180000000U;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
- if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
- while ( ep_intr )
+ while (ep_intr != 0U)
{
- if (ep_intr & 0x1U)
+ if ((ep_intr & 0x1U) != 0U)
{
- epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
+ epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
- if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+ if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
- if(hpcd->Init.dma_enable == 1U)
- {
- hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
- hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
- }
-
- HAL_PCD_DataOutStageCallback(hpcd, epnum);
- if(hpcd->Init.dma_enable == 1U)
- {
- if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
- {
- /* this is ZLP, so prepare EP0 for next setup */
- USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
- }
- }
+ (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
}
- if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+ if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
- /* Inform the upper layer that a setup packet is available */
- HAL_PCD_SetupStageCallback(hpcd);
+ /* Class B setup phase done for previous decoded setup */
+ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
- if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+ if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
-#ifdef USB_OTG_DOEPINT_OTEPSPR
/* Clear Status Phase Received interrupt */
- if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
+
+ /* Clear OUT NAK interrupt */
+ if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+ }
}
epnum++;
ep_intr >>= 1U;
}
}
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
epnum = 0U;
- while ( ep_intr )
+ while (ep_intr != 0U)
{
- if (ep_intr & 0x1U) /* In ITR */
+ if ((ep_intr & 0x1U) != 0U) /* In ITR */
{
- epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+ epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
- if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+ if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
- fifoemptymsk = 0x1U << epnum;
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@@ -428,37 +1135,41 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
}
- HAL_PCD_DataInStageCallback(hpcd, epnum);
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if (hpcd->Init.dma_enable == 1U)
{
/* this is ZLP, so prepare EP0 for next setup */
- if((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
/* prepare to rx more setup packets */
- USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
}
- if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+ if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
}
- if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+ if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
}
- if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+ if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
}
- if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+ if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
- if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+ if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
{
- PCD_WriteEmptyTxFifo(hpcd , epnum);
+ (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
}
}
epnum++;
@@ -467,186 +1178,143 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/* Handle Resume Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-#ifdef USB_OTG_GLPMCFG_LPMEN
- if(hpcd->LPM_State == LPM_L1)
+ if (hpcd->LPM_State == LPM_L1)
{
hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
-#endif /* USB_OTG_GLPMCFG_LPMEN */
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResumeCallback(hpcd);
+#else
HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
-
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
-#ifdef USB_OTG_GLPMCFG_LPMEN
+ #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Handle LPM Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
- if( hpcd->LPM_State == LPM_L0)
+
+ if (hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
-#endif /* USB_OTG_GLPMCFG_LPMEN */
-
+ #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
/* Handle Reset Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
- USB_FlushTxFifo(hpcd->Instance , 0x10U);
+ (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
- USBx_INEP(i)->DIEPINT = 0xFFU;
- USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
+ USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+ USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
}
- USBx_DEVICE->DAINT = 0xFFFFFFFFU;
USBx_DEVICE->DAINTMSK |= 0x10001U;
- if(hpcd->Init.use_dedicated_ep1)
+ if (hpcd->Init.use_dedicated_ep1 != 0U)
{
- USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM;
+
+ USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
}
else
{
-#ifdef USB_OTG_DOEPINT_OTEPSPR
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
-#else
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-#endif /* USB_OTG_DOEPINT_OTEPSPR */
- USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+ USB_OTG_DOEPMSK_XFRCM |
+ USB_OTG_DOEPMSK_EPDM |
+ USB_OTG_DOEPMSK_OTEPSPRM |
+ USB_OTG_DOEPMSK_NAKM;
+
+ USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+ USB_OTG_DIEPMSK_XFRCM |
+ USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
/* setup EP0 to receive SETUP packets */
- USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+ (uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
/* Handle Enumeration done Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
- USB_ActivateSetup(hpcd->Instance);
- hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
- if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
- {
- hpcd->Init.speed = USB_OTG_SPEED_HIGH;
- hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
- else
- {
- hpcd->Init.speed = USB_OTG_SPEED_FULL;
- hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
-
- /* The USBTRD is configured according to the tables below, depending on AHB frequency
- used by application. In the low AHB frequency range it is used to stretch enough the USB response
- time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
- latency to the Data FIFO */
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- if((hclk >= 14200000U)&&(hclk < 15000000U))
- {
- /* hclk Clock Range between 14.2-15 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 15000000U)&&(hclk < 16000000U))
- {
- /* hclk Clock Range between 15-16 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 16000000U)&&(hclk < 17200000U))
- {
- /* hclk Clock Range between 16-17.2 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 17200000U)&&(hclk < 18500000U))
- {
- /* hclk Clock Range between 17.2-18.5 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 18500000U)&&(hclk < 20000000U))
- {
- /* hclk Clock Range between 18.5-20 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 20000000U)&&(hclk < 21800000U))
- {
- /* hclk Clock Range between 20-21.8 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 21800000U)&&(hclk < 24000000U))
- {
- /* hclk Clock Range between 21.8-24 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
+ (void)USB_ActivateSetup(hpcd->Instance);
+ hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
- else if((hclk >= 24000000U)&&(hclk < 27700000U))
- {
- /* hclk Clock Range between 24-27.7 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else if((hclk >= 27700000U)&&(hclk < 32000000U))
- {
- /* hclk Clock Range between 27.7-32 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
-
- else /* if(hclk >= 32000000) */
- {
- /* hclk Clock Range between 32-180 MHz */
- hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT);
- }
- }
+ /* Set USB Turnaround time */
+ (void)USB_SetTurnaroundTime(hpcd->Instance,
+ HAL_RCC_GetHCLKFreq(),
+ (uint8_t)hpcd->Init.speed);
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResetCallback(hpcd);
+#else
HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle RxQLevel Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
@@ -654,64 +1322,104 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
- if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
+ if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
- if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
- USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ (void)USB_ReadPacket(USBx, ep->xfer_buff,
+ (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ {
+ (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ }
+ else
{
- USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ /* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle SOF Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback(hpcd);
+#else
HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Incomplete ISO IN Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
- HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+ /* Keep application checking the corresponding Iso IN endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
/* Handle Incomplete ISO OUT Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
- HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+ /* Keep application checking the corresponding Iso OUT endpoint
+ causing the incomplete Interrupt */
+ epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
/* Handle Connection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ConnectCallback(hpcd);
+#else
HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
}
/* Handle Disconnection event Interrupt */
- if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
temp = hpcd->Instance->GOTGINT;
- if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DisconnectCallback(hpcd);
+#else
HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= temp;
}
}
}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
/**
* @brief Data OUT stage callback.
@@ -719,41 +1427,44 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
- * @brief Data IN stage callback.
+ * @brief Data IN stage callback
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
- * @brief Setup stage callback.
+ * @brief Setup stage callback
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
@@ -763,11 +1474,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
@@ -777,11 +1489,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
@@ -791,11 +1504,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
@@ -805,11 +1519,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
@@ -820,12 +1535,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
@@ -836,12 +1552,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
@@ -851,11 +1568,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
@@ -865,11 +1583,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
@@ -894,14 +1613,26 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Connect the USB device.
+ * @brief Connect the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
__HAL_LOCK(hpcd);
- USB_DevConnect(hpcd->Instance);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+ if ((hpcd->Init.battery_charging_enable == 1U) &&
+ (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+ {
+ /* Enable USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+ (void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -914,7 +1645,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
- USB_DevDisconnect(hpcd->Instance);
+ (void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -928,7 +1659,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
__HAL_LOCK(hpcd);
- USB_SetDevAddress(hpcd->Instance, address);
+ hpcd->USB_Address = address;
+ (void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -943,39 +1675,41 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
- ep->num = ep_addr & 0x7F;
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->type = ep_type;
- if (ep->is_in)
+
+ if (ep->is_in != 0U)
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
}
/* Set initial data PID. */
- if (ep_type == EP_TYPE_BULK )
+ if (ep_type == EP_TYPE_BULK)
{
ep->data_pid_start = 0U;
}
__HAL_LOCK(hpcd);
- USB_ActivateEndpoint(hpcd->Instance , ep);
+ (void)USB_ActivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
+
return ret;
}
-
/**
* @brief Deactivate an endpoint.
* @param hpcd PCD handle
@@ -984,22 +1718,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
- ep->num = ep_addr & 0x7F;
-
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
- USB_DeactivateEndpoint(hpcd->Instance , ep);
+ (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -1015,46 +1749,46 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
- if ((ep_addr & 0x7F) == 0)
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
return HAL_OK;
}
/**
- * @brief Get Received Data Size.
+ * @brief Get Received Data Size
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
+ return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
/**
- * @brief Send an amount of data.
+ * @brief Send an amount of data
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param pBuf pointer to the transmission buffer
@@ -1063,63 +1797,69 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
- if ((ep_addr & 0x7F) == 0)
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
return HAL_OK;
}
/**
- * @brief Set a STALL condition over an endpoint.
+ * @brief Set a STALL condition over an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
+ ep->is_in = 0U;
}
ep->is_stall = 1U;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
-
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
- USB_EPSetStall(hpcd->Instance , ep);
- if((ep_addr & 0x7F) == 0)
+
+ (void)USB_EPSetStall(hpcd->Instance, ep);
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
@@ -1127,37 +1867,43 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Clear a STALL condition over in an endpoint.
+ * @brief Clear a STALL condition over in an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- USB_OTG_EPTypeDef *ep;
+ PCD_EPTypeDef *ep;
+
+ if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
ep->is_stall = 0U;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
- USB_EPClearStall(hpcd->Instance , ep);
+ (void)USB_EPClearStall(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Flush an endpoint.
+ * @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
@@ -1166,13 +1912,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+ (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
}
else
{
- USB_FlushRxFifo(hpcd->Instance);
+ (void)USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
@@ -1181,20 +1927,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Activate remote wakeup signalling.
+ * @brief Activate remote wakeup signalling
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
- {
- /* Activate Remote wakeup signaling */
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
- }
- return HAL_OK;
+ return (USB_ActivateRemoteWakeup(hpcd->Instance));
}
/**
@@ -1204,12 +1943,9 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
- /* De-activate Remote wakeup signaling */
- USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
- return HAL_OK;
+ return (USB_DeActivateRemoteWakeup(hpcd->Instance));
}
+
/**
* @}
*/
@@ -1238,6 +1974,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
{
return hpcd->State;
}
+
/**
* @}
*/
@@ -1250,22 +1987,29 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
/** @addtogroup PCD_Private_Functions
* @{
*/
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Check FIFO for the next packet to be loaded.
* @param hpcd PCD handle
- * @param epnum endpoint number
+ * @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
USB_OTG_EPTypeDef *ep;
- int32_t len = 0U;
+ uint32_t len;
uint32_t len32b;
- uint32_t fifoemptymsk = 0U;
+ uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
+
+ if (ep->xfer_count > ep->xfer_len)
+ {
+ return HAL_ERROR;
+ }
+
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
@@ -1273,12 +2017,10 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
len = ep->maxpacket;
}
-
len32b = (len + 3U) / 4U;
- while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&
- (ep->xfer_count < ep->xfer_len) &&
- (ep->xfer_len != 0U))
+ while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+ (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
@@ -1289,29 +2031,187 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
}
len32b = (len + 3U) / 4U;
- USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
+ (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+ (uint8_t)hpcd->Init.dma_enable);
ep->xfer_buff += len;
ep->xfer_count += len;
}
- if(len <= 0U)
+ if (ep->xfer_len <= ep->xfer_count)
{
- fifoemptymsk = 0x1U << epnum;
+ fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief process EP OUT transfer complete interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+
+ /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+ }
+ else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+ else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ /* out data packet received over EP0 */
+ hpcd->OUT_ep[epnum].xfer_count =
+ hpcd->OUT_ep[epnum].maxpacket -
+ (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ }
+ }
+ else
+ {
+ /* ... */
+ }
+ }
+ else
+ {
+ if (gSNPSiD == USB_OTG_CORE_ID_310A)
+ {
+ /* StupPktRcvd = 1 this is a setup packet */
+ if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ else
+ {
+ if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief process EP OUT setup packet received interrupt.
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+ if (hpcd->Init.dma_enable == 1U)
+ {
+ /* StupPktRcvd = 1 pending setup packet int */
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ }
+ else
+ {
+ if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
+ ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+ }
+ }
+
+ /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
+ HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+ {
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
return HAL_OK;
}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd_ex.c
index 3d05b017de189dd2c8cc2993e7bf3d5499b7e32c..cd0a5bb5c9750db2aadbccb3d63c234d38c0bb26 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pcd_ex.c
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @brief PCD HAL module driver.
+ * @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -48,12 +32,10 @@
* @brief PCD Extended HAL module driver
* @{
*/
+
#ifdef HAL_PCD_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -61,13 +43,13 @@
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -78,7 +60,7 @@
@endverbatim
* @{
*/
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
@@ -88,8 +70,8 @@
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
- uint8_t i = 0;
- uint32_t Tx_Offset = 0U;
+ uint8_t i;
+ uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
@@ -103,20 +85,20 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
Tx_Offset = hpcd->Instance->GRXFSIZ;
- if(fifo == 0)
+ if (fifo == 0U)
{
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
- Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
- for (i = 0; i < (fifo - 1); i++)
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+ for (i = 0U; i < (fifo - 1U); i++)
{
- Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16U);
+ Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16U) | Tx_Offset);
+ hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
@@ -134,11 +116,9 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
return HAL_OK;
}
-
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
- * @brief Activate LPM feature
+ * @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -146,7 +126,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- hpcd->lpm_active = ENABLE;
+ hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
@@ -163,30 +143,16 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- hpcd->lpm_active = DISABLE;
+ hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
-
-/**
- * @brief Send LPM message to user layer callback.
- * @param hpcd PCD handle
- * @param msg LPM message
- * @retval HAL status
- */
-__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hpcd);
- UNUSED(msg);
-}
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
- * @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
+ * @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -195,69 +161,95 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
- /* Start BCD When device is connected */
- if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
- {
- /* Enable DCD : Data Contact Detect */
- USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+ /* Enable DCD : Data Contact Detect */
+ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
- /* Wait Detect flag or a timeout is happen*/
- while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+ /* Wait Detect flag or a timeout is happen*/
+ while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > 1000U)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > 1000U)
- {
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
- return;
- }
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
+ }
- /* Right response got */
- HAL_Delay(100U);
+ /* Right response got */
+ HAL_Delay(200U);
- /* Check Detect flag*/
- if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
- {
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
- }
+ /* Check Detect flag*/
+ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
- /*Primary detection: checks if connected to Standard Downstream Port
- (without charging capability) */
- USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
- USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
- HAL_Delay(100U);
+ /*Primary detection: checks if connected to Standard Downstream Port
+ (without charging capability) */
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+ HAL_Delay(50U);
+ USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
+ HAL_Delay(50U);
- if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
+ if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
+ {
+ /* Case of Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* start secondary detection to check connection to Charging Downstream
+ Port or Dedicated Charging Port */
+ USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
+ HAL_Delay(50U);
+ USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
+ HAL_Delay(50U);
+
+ if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
- /* Case of Standard Downstream Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+ /* case Dedicated Charging Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
- /* start secondary detection to check connection to Charging Downstream
- Port or Dedicated Charging Port */
- USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
- USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
- HAL_Delay(100U);
-
- if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
- {
- /* case Dedicated Charging Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
- }
- else
- {
- /* case Charging Downstream Port */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
- }
+ /* case Charging Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- /* Battery Charging capability discovery finished */
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
}
+
+ /* Battery Charging capability discovery finished */
+ (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
/**
- * @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature
+ * @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
@@ -265,39 +257,75 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- hpcd->battery_charging_active = ENABLE;
- USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+
+ /* Power Down USB tranceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+ /* Enable Battery charging */
+ USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
+
+ hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
- * @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
+ * @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- hpcd->battery_charging_active = DISABLE;
+
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+
+ /* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+
+ hpcd->battery_charging_active = 0U;
+
return HAL_OK;
}
+#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
- * @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
+ * @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
-__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ */
}
-#endif /* STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+ * @brief Send BatteryCharging message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_BCD_Callback could be implemented in the user file
+ */
+}
/**
* @}
@@ -306,11 +334,9 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
/**
* @}
*/
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr.c
index 2f6eb1dba0864b4d1fa72f08f3787544a6e91a5b..1f7c98015bf43857fdcd7e1438497e6c9ec489c5 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr.c
@@ -11,29 +11,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr_ex.c
index 8d56ab4a149b490a8edc1fde051793fa152a72c5..a94f9e11cfb8b19b9c98e96fd526fa9505b2c4e1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_pwr_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -365,26 +349,6 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
}
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/**
- * @brief Enables Wakeup Pin Detection on high level (rising edge).
- * @retval None
- */
-void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
-{
- *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
-}
-
-/**
- * @brief Enables Wakeup Pin Detection on low level (falling edge).
- * @retval None
- */
-void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
-{
- *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
-}
-#endif /* STM32F469xx || STM32F479xx */
-
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_qspi.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_qspi.c
index 0037b26edf8875f55994e0080dcff843deefdda0..78d3da6947bd2690ddda20934079d4f64f776ca5 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_qspi.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_qspi.c
@@ -126,6 +126,65 @@
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : QSPI MspInit.
+ (+) MspDeInitCallback : QSPI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : QSPI MspInit.
+ (+) MspDeInitCallback : QSPI MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
+ and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
+ or @ref HAL_QSPI_Init function.
+
+ When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
*** Workarounds linked to Silicon Limitation ***
====================================================
[..]
@@ -136,29 +195,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -283,8 +326,30 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/* Allocate lock resource and initialize it */
hqspi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
+ hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+ hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+ hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+ hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+ hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+ hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+ hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+ hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+ hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+ hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+
+ if(hqspi->MspInitCallback == NULL)
+ {
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hqspi->MspInitCallback(hqspi);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
+#endif
/* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
@@ -342,8 +407,18 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ if(hqspi->MspDeInitCallback == NULL)
+ {
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hqspi->MspDeInitCallback(hqspi);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_QSPI_MspDeInit(hqspi);
+#endif
/* Set QSPI error code to none */
hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
@@ -469,7 +544,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* FIFO Threshold callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->FifoThresholdCallback(hqspi);
+#else
HAL_QSPI_FifoThresholdCallback(hqspi);
+#endif
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
@@ -500,7 +579,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* TX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TxCpltCallback(hqspi);
+#else
HAL_QSPI_TxCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
@@ -537,7 +620,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* RX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->RxCpltCallback(hqspi);
+#else
HAL_QSPI_RxCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY)
{
@@ -545,7 +632,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* Command Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->CmdCpltCallback(hqspi);
+#else
HAL_QSPI_CmdCpltCallback(hqspi);
+#endif
}
else if(hqspi->State == HAL_QSPI_STATE_ABORT)
{
@@ -557,14 +648,22 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Abort called by the user */
/* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
}
else
{
/* Abort due to an error (eg : DMA error) */
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
}
@@ -586,7 +685,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* Status match callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->StatusMatchCallback(hqspi);
+#else
HAL_QSPI_StatusMatchCallback(hqspi);
+#endif
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
@@ -608,7 +711,21 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Disable the DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_DMA_Abort_IT(hqspi->hdma);
+ if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
+ HAL_QSPI_ErrorCallback(hqspi);
+#endif
+ }
}
else
{
@@ -616,7 +733,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
/* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->ErrorCallback(hqspi);
+#else
HAL_QSPI_ErrorCallback(hqspi);
+#endif
}
}
@@ -626,8 +747,12 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
- /* Time out callback */
+ /* Timeout callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TimeOutCallback(hqspi);
+#else
HAL_QSPI_TimeOutCallback(hqspi);
+#endif
}
}
@@ -1423,7 +1548,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/* Configure the direction of the DMA */
hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
- MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
+ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
/* Enable the DMA Channel */
tmp = (uint32_t*)&pData;
@@ -1919,6 +2044,227 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
the HAL_QSPI_TimeOutCallback could be implemented in the user file
*/
}
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User QSPI Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hqspi : QSPI handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
+ * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
+ * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
+ * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
+ * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
+ * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_ERROR_CB_ID :
+ hqspi->ErrorCallback = pCallback;
+ break;
+ case HAL_QSPI_ABORT_CB_ID :
+ hqspi->AbortCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+ hqspi->FifoThresholdCallback = pCallback;
+ break;
+ case HAL_QSPI_CMD_CPLT_CB_ID :
+ hqspi->CmdCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_RX_CPLT_CB_ID :
+ hqspi->RxCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_TX_CPLT_CB_ID :
+ hqspi->TxCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+ hqspi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+ hqspi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_QSPI_STATUS_MATCH_CB_ID :
+ hqspi->StatusMatchCallback = pCallback;
+ break;
+ case HAL_QSPI_TIMEOUT_CB_ID :
+ hqspi->TimeOutCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = pCallback;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+ return status;
+}
+
+/**
+ * @brief Unregister a User QSPI Callback
+ * QSPI Callback is redirected to the weak (surcharged) predefined callback
+ * @param hqspi : QSPI handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
+ * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
+ * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
+ * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
+ * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
+ * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
+ * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
+ * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
+ * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hqspi);
+
+ if(hqspi->State == HAL_QSPI_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_ERROR_CB_ID :
+ hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
+ break;
+ case HAL_QSPI_ABORT_CB_ID :
+ hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
+ break;
+ case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
+ hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
+ break;
+ case HAL_QSPI_CMD_CPLT_CB_ID :
+ hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
+ break;
+ case HAL_QSPI_RX_CPLT_CB_ID :
+ hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
+ break;
+ case HAL_QSPI_TX_CPLT_CB_ID :
+ hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
+ break;
+ case HAL_QSPI_RX_HALF_CPLT_CB_ID :
+ hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
+ break;
+ case HAL_QSPI_TX_HALF_CPLT_CB_ID :
+ hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
+ break;
+ case HAL_QSPI_STATUS_MATCH_CB_ID :
+ hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
+ break;
+ case HAL_QSPI_TIMEOUT_CB_ID :
+ hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
+ break;
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hqspi->State == HAL_QSPI_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_QSPI_MSP_INIT_CB_ID :
+ hqspi->MspInitCallback = HAL_QSPI_MspInit;
+ break;
+ case HAL_QSPI_MSP_DEINIT_CB_ID :
+ hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hqspi);
+ return status;
+}
+#endif
/**
* @}
@@ -2043,7 +2389,18 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
/* Abort DMA channel */
hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
- HAL_DMA_Abort_IT(hqspi->hdma);
+ if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
+ HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
+ }
}
else
{
@@ -2156,7 +2513,11 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->RxHalfCpltCallback(hqspi);
+#else
HAL_QSPI_RxHalfCpltCallback(hqspi);
+#endif
}
/**
@@ -2168,7 +2529,11 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->TxHalfCpltCallback(hqspi);
+#else
HAL_QSPI_TxHalfCpltCallback(hqspi);
+#endif
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc.c
index 1f833074f6a0757611b325cd71a08d9642eba430..7fe1db65a571e21692872ef7a56c63783a98b808 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc.c
@@ -54,29 +54,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc_ex.c
index bbebe74a499481d209083ba087fdae786d734aa3..16eab050c1e3757afb2c9acc37a9a845412fb7c3 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rcc_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rng.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rng.c
index c4d42f176535f726afc06be9a25a9382af92b86c..fca4240f63281c1e32b9372b364363361db9c22b 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rng.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rng.c
@@ -5,7 +5,7 @@
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
- * + Initialization/de-initialization functions
+ * + Initialization and configuration functions
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -23,33 +23,71 @@
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
+ Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ErrorCallback : RNG Error Callback.
+ (+) MspInitCallback : RNG MspInit.
+ (+) MspDeInitCallback : RNG MspDeInit.
+
+ [..]
+ For specific callback ReadyDataCallback, use dedicated register callbacks:
+ respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+
+ [..]
+ By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ example @ref HAL_RNG_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
+ and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
+ or @ref HAL_RNG_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -61,24 +99,20 @@
* @{
*/
+#if defined (RNG)
+
/** @addtogroup RNG
+ * @brief RNG HAL module driver.
* @{
*/
#ifdef HAL_RNG_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\
- defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
- defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
-
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
+/** @defgroup RNG_Private_Constants RNG Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -95,11 +129,11 @@
*/
/** @addtogroup RNG_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
+ * @brief Initialization and configuration functions
*
@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the RNG according to the specified parameters
@@ -121,28 +155,54 @@
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
- if(hrng == NULL)
+ if (hrng == NULL)
{
return HAL_ERROR;
}
+ /* Check the parameters */
+ assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->State == HAL_RNG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrng->Lock = HAL_UNLOCKED;
+
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
- if(hrng->State == HAL_RNG_STATE_RESET)
+ if (hrng->MspInitCallback == NULL)
+ {
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hrng->MspInitCallback(hrng);
+ }
+#else
+ if (hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
+
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
/* Return function status */
return HAL_OK;
}
@@ -156,22 +216,36 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
- if(hrng == NULL)
+ if (hrng == NULL)
{
return HAL_ERROR;
}
+
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ if (hrng->MspDeInitCallback == NULL)
+ {
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hrng->MspDeInitCallback(hrng);
+#else
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_RESET;
+ /* Initialise the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
/* Release Lock */
__HAL_UNLOCK(hrng);
@@ -209,6 +283,233 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
*/
}
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RNG Callback
+ * To be used instead of the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Unregister an RNG Callback
+ * RNG callabck is redirected to the weak predefined callback
+ * @param hrng RNG handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RNG_STATE_RESET == hrng->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief Register Data Ready RNG Callback
+ * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @param pCallback pointer to the Data Ready Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Data Ready RNG Callback
+ * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+ * @param hrng RNG handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ if (HAL_RNG_STATE_READY == hrng->State)
+ {
+ hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrng);
+ return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -241,14 +542,14 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
+ if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@@ -257,16 +558,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
- while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
{
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
- hrng->State = HAL_RNG_STATE_ERROR;
-
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
-
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -278,6 +578,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
}
else
{
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
@@ -301,14 +602,11 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
+ if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
- /* Process Unlocked */
- __HAL_UNLOCK(hrng);
-
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
}
@@ -317,12 +615,59 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
/* Process Unlocked */
__HAL_UNLOCK(hrng);
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
+/**
+ * @brief Returns generated random number in polling mode (Obsolete)
+ * Use HAL_RNG_GenerateRandomNumber() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval Random value
+ */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+ if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+ {
+ return hrng->RandomNumber;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+/**
+ * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
+ * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
+ * @retval 32-bit random number
+ */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+ uint32_t random32bit = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hrng);
+
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* Get a 32bit Random number */
+ random32bit = hrng->Instance->DR;
+
+ /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+ __HAL_RNG_ENABLE_IT(hrng);
+
+ /* Return the 32 bit random number */
+ return random32bit;
+}
+
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
@@ -346,21 +691,45 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
+ uint32_t rngclockerror = 0U;
+
/* RNG clock error interrupt occurred */
- if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ rngclockerror = 1U;
+ }
+ else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+ rngclockerror = 1U;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if (rngclockerror == 1U)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Clear the clock error flag */
- __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-
+ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
}
/* Check RNG data ready interrupt occurred */
- if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -368,63 +737,24 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
- if(hrng->State != HAL_RNG_STATE_ERROR)
+ if (hrng->State != HAL_RNG_STATE_ERROR)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
-
- /* Data Ready callback */
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Data Ready callback */
+ hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+ /* Call legacy weak Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
}
}
}
-/**
- * @brief Returns generated random number in polling mode (Obsolete)
- * Use HAL_RNG_GenerateRandomNumber() API instead.
- * @param hrng pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval Random value
- */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
-{
- if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
- {
- return hrng->RandomNumber;
- }
- else
- {
- return 0U;
- }
-}
-
-/**
- * @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
- * Use HAL_RNG_GenerateRandomNumber_IT() API instead.
- * @param hrng pointer to a RNG_HandleTypeDef structure that contains
- * the configuration information for RNG.
- * @retval 32-bit random number
- */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
-{
- uint32_t random32bit = 0U;
-
- /* Process locked */
- __HAL_LOCK(hrng);
-
- /* Change RNG peripheral state */
- hrng->State = HAL_RNG_STATE_BUSY;
-
- /* Get a 32bit Random number */
- random32bit = hrng->Instance->DR;
-
- /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
- __HAL_RNG_ENABLE_IT(hrng);
-
- /* Return the 32 bit random number */
- return random32bit;
-}
-
/**
* @brief Read latest generated random number.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
@@ -433,7 +763,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
*/
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
- return(hrng->RandomNumber);
+ return (hrng->RandomNumber);
}
/**
@@ -498,6 +828,16 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
return hrng->State;
}
+/**
+ * @brief Return the RNG handle error code.
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval RNG Error Code
+*/
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+{
+ /* Return RNG Error Code */
+ return hrng->ErrorCode;
+}
/**
* @}
*/
@@ -506,16 +846,14 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
- STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#endif /* HAL_RNG_MODULE_ENABLED */
-
/**
* @}
*/
+#endif /* RNG */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc.c
index 0f31b3939ff86f1497c43d30b6476f17c5bef909..f7fe5f1a0a1edaca24cc07dd707e6e715f957f51 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc.c
@@ -102,33 +102,71 @@
Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) AlarmBEventCallback : RTC Alarm B Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+
+ By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions :
+ examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+ Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+ in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+ or @ref HAL_RTC_Init() function.
+
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -152,7 +190,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
@@ -214,13 +252,41 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+
+ if(hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if(hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+ }
+#else
if(hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
+
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
@@ -370,8 +436,19 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if(hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+
+#else
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
hrtc->State = HAL_RTC_STATE_RESET;
@@ -381,6 +458,204 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
return HAL_OK;
}
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RTC Callback
+ * To be used instead of the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if(HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an RTC Callback
+ * RTC callabck is redirected to the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if(HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ break;
+
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ break;
+
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ break;
+
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ break;
+
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @brief Initializes the RTC MSP.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
@@ -478,8 +753,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sTime->Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
@@ -650,8 +924,8 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- assert_param(IS_RTC_MONTH(datetmpreg));
- assert_param(IS_RTC_DATE(datetmpreg));
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
(((uint32_t)sDate->Month) << 8U) | \
@@ -836,8 +1110,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
@@ -851,13 +1124,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
@@ -1021,8 +1292,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
@@ -1036,13 +1306,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
@@ -1310,7 +1578,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
{
/* AlarmA callback */
+ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback(hrtc);
+ #else
HAL_RTC_AlarmAEventCallback(hrtc);
+ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
@@ -1323,7 +1595,11 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
{
/* AlarmB callback */
+ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmBEventCallback(hrtc);
+ #else
HAL_RTCEx_AlarmBEventCallback(hrtc);
+ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
@@ -1347,7 +1623,7 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc_ex.c
index a621600370cfc3c008e6b94309a807e614bebb42..5b25ed7b3c80504dfd2b9f48219c46460752570d 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_rtc_ex.c
@@ -23,24 +23,24 @@
*** RTC Wake-up configuration ***
================================
[..]
- (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
function. You can also configure the RTC Wake-up timer in interrupt mode
- using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer()
+ using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer()
function.
*** TimeStamp configuration ***
===============================
[..]
(+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
- HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
function.
(+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in
- RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
- or HAL_RTC_SetTimeStamp_IT() function.
+ RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp()
+ or HAL_RTCEx_SetTimeStamp_IT() function.
*** Tamper configuration ***
============================
@@ -48,48 +48,32 @@
(+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
or Level according to the Tamper filter (if equal to 0 Edge else Level)
value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
- mode using HAL_RTC_SetTamper_IT() function.
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
+ mode using HAL_RTCEx_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in
- RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
- or HAL_RTC_SetTamper_IT() function.
+ RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTamper()
+ or HAL_RTCEx_SetTamper_IT() function.
*** Backup Data Registers configuration ***
===========================================
[..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
function.
- (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -521,7 +505,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
{
/* TIMESTAMP callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->TimeStampEventCallback(hrtc);
+#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the TIMESTAMP interrupt pending bit */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
@@ -535,7 +523,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
{
/* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper1EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
@@ -549,7 +541,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
{
/* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper2EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
@@ -1014,7 +1010,11 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
{
/* WAKEUPTIMER callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->WakeUpTimerEventCallback(hrtc);
+#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai.c
index b817ed223a00e7aa6bf8fd9a51baad22385671e0..5d181e1a2b76e86663f272475568bedc94459a67 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai.c
@@ -139,33 +139,69 @@
enabled or disabled
(+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not
+ *** Callback registration ***
+ =============================
+
+ The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+
+ Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the callback ID.
+ This function allows to reset following callbacks:
+ (+) RxCpltCallback : SAI receive complete.
+ (+) RxHalfCpltCallback : SAI receive half complete.
+ (+) TxCpltCallback : SAI transmit complete.
+ (+) TxHalfCpltCallback : SAI transmit half complete.
+ (+) ErrorCallback : SAI error.
+ (+) MspInitCallback : SAI MspInit.
+ (+) MspDeInitCallback : SAI MspDeInit.
+
+ By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
+ and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
+ or @ref HAL_SAI_Init function.
+
+ When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -213,7 +249,6 @@ typedef enum {
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
/** @defgroup SAI_Private_Functions SAI Private Functions
* @{
*/
@@ -241,14 +276,13 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma);
*/
/* Exported functions ---------------------------------------------------------*/
-
/** @defgroup SAI_Exported_Functions SAI Exported Functions
* @{
*/
/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -383,8 +417,24 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
/* Allocate lock resource and initialize it */
hsai->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ /* Reset callback pointers to the weak predefined callbacks */
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ if (hsai->MspInitCallback == NULL)
+ {
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ }
+ hsai->MspInitCallback(hsai);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_SAI_MspInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
hsai->State = HAL_SAI_STATE_BUSY;
@@ -520,7 +570,15 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ if (hsai->MspDeInitCallback == NULL)
+ {
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ }
+ hsai->MspDeInitCallback(hsai);
+#else
HAL_SAI_MspDeInit(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/* Initialize the error code */
hsai->ErrorCode = HAL_SAI_ERROR_NONE;
@@ -566,13 +624,189 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
*/
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a user SAI callback
+ * to be used instead of the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be registered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @param pCallback pointer to the callback function.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID,
+ pSAI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = pCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = pCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = pCallback;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Unregister a user SAI callback.
+ * SAI callback is redirected to the weak predefined callback.
+ * @param hsai SAI handle.
+ * @param CallbackID ID of the callback to be unregistered.
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID.
+ * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID.
+ * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID.
+ * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID.
+ * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID.
+ * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID.
+ * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
+ HAL_SAI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_SAI_STATE_READY == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_RX_COMPLETE_CB_ID :
+ hsai->RxCpltCallback = HAL_SAI_RxCpltCallback;
+ break;
+ case HAL_SAI_RX_HALFCOMPLETE_CB_ID :
+ hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback;
+ break;
+ case HAL_SAI_TX_COMPLETE_CB_ID :
+ hsai->TxCpltCallback = HAL_SAI_TxCpltCallback;
+ break;
+ case HAL_SAI_TX_HALFCOMPLETE_CB_ID :
+ hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback;
+ break;
+ case HAL_SAI_ERROR_CB_ID :
+ hsai->ErrorCallback = HAL_SAI_ErrorCallback;
+ break;
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SAI_STATE_RESET == hsai->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SAI_MSPINIT_CB_ID :
+ hsai->MspInitCallback = HAL_SAI_MspInit;
+ break;
+ case HAL_SAI_MSPDEINIT_CB_ID :
+ hsai->MspDeInitCallback = HAL_SAI_MspDeInit;
+ break;
+ default :
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update the error code */
+ hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup SAI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -1338,7 +1572,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
uint32_t cr1config = hsai->Instance->CR1;
uint32_t tmperror;
- /* SAI Fifo request interrupt occured ------------------------------------*/
+ /* SAI Fifo request interrupt occurred ------------------------------------*/
if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))
{
hsai->InterruptServiceRoutine(hsai);
@@ -1356,7 +1590,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= tmperror;
/* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/* SAI mutedet interrupt occurred ----------------------------------*/
else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))
@@ -1404,7 +1642,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
HAL_SAI_Abort(hsai);
/* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI LFSDET interrupt occurred ----------------------------------*/
@@ -1440,7 +1682,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
HAL_SAI_Abort(hsai);
/* Set error callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI WCKCFG interrupt occurred ----------------------------------*/
@@ -1484,7 +1730,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->XferCount = 0U;
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
/* SAI CNRDY interrupt occurred ----------------------------------*/
@@ -1497,7 +1747,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;
/* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1528,7 +1782,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
* the configuration information for SAI module.
* @retval None
*/
- __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
+__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsai);
@@ -1590,10 +1844,9 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
* @}
*/
-
/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1618,11 +1871,11 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
}
/**
-* @brief Return the SAI error code.
-* @param hsai pointer to a SAI_HandleTypeDef structure that contains
- * the configuration information for the specified SAI Block.
-* @retval SAI Error Code
-*/
+ * @brief Return the SAI error code.
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for the specified SAI Block.
+ * @retval SAI Error Code
+ */
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
{
return hsai->ErrorCode;
@@ -1636,7 +1889,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
*/
/** @addtogroup SAI_Private_Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
@@ -1912,7 +2165,11 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1936,7 +2193,11 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1961,7 +2222,11 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)
/* Disable FREQ and OVRUDR interrupts */
__HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
else
{
@@ -1994,7 +2259,11 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
@@ -2021,7 +2290,11 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
@@ -2048,7 +2321,11 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);
hsai->State = HAL_SAI_STATE_READY;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
}
@@ -2074,7 +2351,11 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
hsai->State= HAL_SAI_STATE_READY;
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxCpltCallback(hsai);
+#else
HAL_SAI_TxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2087,7 +2368,11 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->TxHalfCpltCallback(hsai);
+#else
HAL_SAI_TxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2110,7 +2395,11 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
hsai->State = HAL_SAI_STATE_READY;
}
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxCpltCallback(hsai);
+#else
HAL_SAI_RxCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2123,7 +2412,11 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->RxHalfCpltCallback(hsai);
+#else
HAL_SAI_RxHalfCpltCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
@@ -2154,11 +2447,15 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma)
hsai->XferCount = 0U;
}
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
- * @brief DMA SAI Abort callback.
+ * @brief DMA SAI Abort callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
@@ -2189,7 +2486,11 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
hsai->XferCount = 0U;
/* SAI error Callback */
+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
+ hsai->ErrorCallback(hsai);
+#else
HAL_SAI_ErrorCallback(hsai);
+#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
}
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai_ex.c
index 42c0b3583e4b55e1c50df578d91a3fa807a3f076..63eebaf8302ecce3801e313259026f6e8342f18e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sai_ex.c
@@ -25,29 +25,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -113,7 +97,7 @@
*/
void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
{
- uint32_t tmpregisterGCR = 0U;
+ uint32_t tmpregisterGCR;
#if defined(STM32F446xx)
/* This setting must be done with both audio block (A & B) disabled */
@@ -129,6 +113,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
break;
default:
+ tmpregisterGCR = 0U;
break;
}
@@ -161,6 +146,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai)
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
break;
default:
+ tmpregisterGCR = 0U;
break;
}
SAI1->GCR = tmpregisterGCR;
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sd.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sd.c
index 31fd8cbb7479a1852f56d07d111c3fa62075b676..dbcbb7b6868e7c9ae01d23c1e2ebe6a6565757d7 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sd.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sd.c
@@ -192,33 +192,64 @@
[..]
(@) You can refer to the SD HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) MspInitCallback : SD MspInit.
+ (+) MspDeInitCallback : SD MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+ and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+ or @ref HAL_SD_Init function.
+
+ When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -325,8 +356,24 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+
+ if(hsd->MspInitCallback == NULL)
+ {
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsd->MspInitCallback(hsd);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
+#endif
}
hsd->State = HAL_SD_STATE_BUSY;
@@ -424,8 +471,18 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
/* Set SD power state to off */
SD_PowerOFF(hsd);
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ if(hsd->MspDeInitCallback == NULL)
+ {
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsd->MspDeInitCallback(hsd);
+#else
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
+#endif
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
@@ -890,7 +947,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
hsd->pRxBuffPtr = (uint32_t *)pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
@@ -996,7 +1053,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
/* Enable transfer interrupts */
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
@@ -1098,7 +1155,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
@@ -1216,7 +1273,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
hsd->Instance->DCTRL = 0U;
/* Enable SD Error interrupts */
-#ifdef SDIO_STA_STBITER
+#ifdef SDIO_STA_STBITERR
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
@@ -1428,7 +1485,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
@@ -1438,11 +1499,19 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
hsd->State = HAL_SD_STATE_READY;
if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->RxCpltCallback(hsd);
+#else
HAL_SD_RxCpltCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->TxCpltCallback(hsd);
+#else
HAL_SD_TxCpltCallback(hsd);
+#endif
}
}
else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
@@ -1453,7 +1522,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
@@ -1464,7 +1537,11 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->TxCpltCallback(hsd);
+#else
HAL_SD_TxCpltCallback(hsd);
+#endif
}
}
}
@@ -1542,14 +1619,22 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
}
else if((hsd->Context & SD_CONTEXT_IT) != RESET)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
#else /* SDIO_STA_STBITERR not defined */
@@ -1701,6 +1786,179 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
*/
}
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SD Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackId : Id of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = pCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = pCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = pCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = pCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = pCallback;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SD Callback
+ * SD Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsd : SD handle
+ * @param CallbackId : Id of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
+ * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
+ * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
+ * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
+ * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
+ * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsd);
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_TX_CPLT_CB_ID :
+ hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+ break;
+ case HAL_SD_RX_CPLT_CB_ID :
+ hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+ break;
+ case HAL_SD_ERROR_CB_ID :
+ hsd->ErrorCallback = HAL_SD_ErrorCallback;
+ break;
+ case HAL_SD_ABORT_CB_ID :
+ hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+ break;
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsd->State == HAL_SD_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SD_MSP_INIT_CB_ID :
+ hsd->MspInitCallback = HAL_SD_MspInit;
+ break;
+ case HAL_SD_MSP_DEINIT_CB_ID :
+ hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsd);
+ return status;
+}
+#endif
/**
* @}
@@ -2263,7 +2521,11 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
}
@@ -2313,7 +2575,11 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
@@ -2326,7 +2592,11 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
hsd->State = HAL_SD_STATE_READY;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->RxCpltCallback(hsd);
+#else
HAL_SD_RxCpltCallback(hsd);
+#endif
}
/**
@@ -2358,7 +2628,11 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma)
hsd->State= HAL_SD_STATE_READY;
}
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
/**
@@ -2388,11 +2662,19 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
}
@@ -2425,11 +2707,19 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->AbortCpltCallback(hsd);
+#else
HAL_SD_AbortCallback(hsd);
+#endif
}
else
{
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+ hsd->ErrorCallback(hsd);
+#else
HAL_SD_ErrorCallback(hsd);
+#endif
}
}
}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sdram.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sdram.c
index 4d9cc2439f5412a3f696c59aaa86d3489d709dec..2489e7e4163a78cab74924d80695cfc1d48abd9f 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sdram.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sdram.c
@@ -57,33 +57,56 @@
(#) You can continuously monitor the SDRAM device HAL state by calling the function
HAL_SDRAM_GetState()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : SDRAM MspInit.
+ (+) MspDeInitCallback : SDRAM MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : SDRAM MspInit.
+ (+) MspDeInitCallback : SDRAM MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
+ and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
+ or @ref HAL_SDRAM_Init function.
+
+ When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -147,8 +170,21 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ if(hsdram->MspInitCallback == NULL)
+ {
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ }
+ hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+ hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+
+ /* Init the low level hardware */
+ hsdram->MspInitCallback(hsdram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
+#endif
}
/* Initialize the SDRAM controller state */
@@ -174,8 +210,18 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy
*/
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
{
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ if(hsdram->MspDeInitCallback == NULL)
+ {
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsdram->MspDeInitCallback(hsdram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspDeInit(hsdram);
+#endif
/* Configure the SDRAM registers with their reset values */
FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
@@ -231,7 +277,11 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
{
/* SDRAM refresh error interrupt callback */
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+ hsdram->RefreshErrorCallback(hsdram);
+#else
HAL_SDRAM_RefreshErrorCallback(hsdram);
+#endif
/* Clear SDRAM refresh error interrupt pending bit */
__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
@@ -629,6 +679,207 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
return HAL_OK;
}
+
+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SDRAM Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
+ * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
+ * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = pCallback;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SDRAM Callback
+ * SDRAM Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
+ * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
+ * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ case HAL_SDRAM_REFRESH_ERR_CB_ID :
+ hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hsdram->State == HAL_SDRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_MSP_INIT_CB_ID :
+ hsdram->MspInitCallback = HAL_SDRAM_MspInit;
+ break;
+ case HAL_SDRAM_MSP_DEINIT_CB_ID :
+ hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+
+/**
+ * @brief Register a User SDRAM Callback for DMA transfers
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsdram : SDRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SDRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsdram);
+
+ state = hsdram->State;
+ if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
+ hsdram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
+ hsdram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsdram);
+ return status;
+}
+#endif
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smartcard.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smartcard.c
index 2772a6723bd06f93b2ebe88139a7b0713e36c6a9..6b79f9ae2180f8dfcfffe1a9d744ef796cfdd2c5 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smartcard.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smartcard.c
@@ -7,7 +7,8 @@
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
*
@verbatim
==============================================================================
@@ -18,10 +19,10 @@
(#) Declare a SMARTCARD_HandleTypeDef handle structure.
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (##) Enable the USARTx interface clock.
+ (##) Enable the interface clock of the USARTx associated to the SMARTCARD.
(##) SMARTCARD pins configuration:
(+++) Enable the clock for the SMARTCARD GPIOs.
- (+++) Configure these SMARTCARD pins as alternate function pull-up.
+ (+++) Configure SMARTCARD pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -31,9 +32,11 @@
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx stream.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
@@ -80,7 +83,7 @@
add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
*** SMARTCARD HAL driver macros list ***
- =============================================
+ ========================================
[..]
Below the list of most used macros in SMARTCARD HAL driver.
@@ -94,33 +97,77 @@
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
+ and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
+ or @ref HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -133,7 +180,7 @@
*/
/** @defgroup SMARTCARD SMARTCARD
- * @brief HAL USART SMARTCARD module driver
+ * @brief HAL SMARTCARD module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
@@ -145,17 +192,21 @@
/**
* @}
*/
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -169,6 +220,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
@@ -220,7 +272,11 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
between the two configurations.
[..]
The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
- procedure (details for the procedure are available in reference manual (RM0329)).
+ procedures (details for the procedures are available in reference manual
+ (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
+ RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
+ RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
+ RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
@endverbatim
@@ -234,9 +290,9 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
*/
/**
- * @brief Initializes the SmartCard mode according to the specified
- * parameters in the SMARTCARD_InitTypeDef and create the associated handle .
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Initializes the SmartCard mode according to the specified
+ * parameters in the SMARTCARD_InitTypeDef and create the associated handle.
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -256,8 +312,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
{
/* Allocate lock resource and initialize it */
hsc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsc);
+
+ if (hsc->MspInitCallback == NULL)
+ {
+ hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsc->MspInitCallback(hsc);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_SMARTCARD_MspInit(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
}
hsc->gState = HAL_SMARTCARD_STATE_BUSY;
@@ -302,7 +371,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief DeInitializes the USART SmartCard peripheral
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -323,7 +392,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
__HAL_SMARTCARD_DISABLE(hsc);
/* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsc->MspDeInitCallback == NULL)
+ {
+ hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsc->MspDeInitCallback(hsc);
+#else
HAL_SMARTCARD_MspDeInit(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState = HAL_SMARTCARD_STATE_RESET;
@@ -336,47 +414,271 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
}
/**
- * @brief SMARTCARD MSP Init
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief SMARTCARD MSP Init
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
*/
}
/**
* @brief SMARTCARD MSP DeInit
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
*/
}
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsc smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsc);
+
+ if (hsc->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsc->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsc->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsc->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsc->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsc->AbortReceiveCpltCallback = pCallback;
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsc->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsc smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsc);
+
+ if (HAL_SMARTCARD_STATE_READY == hsc->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsc->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsc->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsc);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
+ * @brief SMARTCARD Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
(#) Smartcard is a single wire half duplex communication protocol.
@@ -417,17 +719,41 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_SMARTCARD_Abort()
+ (+) HAL_SMARTCARD_AbortTransmit()
+ (+) HAL_SMARTCARD_AbortReceive()
+ (+) HAL_SMARTCARD_Abort_IT()
+ (+) HAL_SMARTCARD_AbortTransmit_IT()
+ (+) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_SMARTCARD_AbortCpltCallback()
+ (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
* @brief Send an amount of data in blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
- * @param Timeout Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -437,7 +763,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -486,11 +812,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
/**
* @brief Receive an amount of data in blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
- * @param Timeout Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -500,7 +826,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -546,10 +872,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -557,7 +883,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -594,10 +920,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -605,7 +931,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -639,10 +965,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -652,7 +978,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -676,7 +1002,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
/* Set the DMA abort callback */
hsc->hdmatx->XferAbortCallback = NULL;
- /* Enable the SMARTCARD transmit DMA Stream */
+ /* Enable the SMARTCARD transmit DMA stream */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
@@ -700,10 +1026,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData pointer to data buffer
- * @param Size amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
* @retval HAL status
*/
@@ -714,7 +1040,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -737,7 +1063,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
/* Set the DMA abort callback */
hsc->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA Stream */
+ /* Enable the DMA stream */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
@@ -834,7 +1160,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1030,7 +1356,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsc->AbortCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
@@ -1040,7 +1372,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1082,7 +1414,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsc->AbortTransmitCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
@@ -1094,7 +1432,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsc->AbortTransmitCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1105,7 +1449,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable SMARTCARD Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1148,7 +1492,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsc->AbortReceiveCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
@@ -1160,7 +1510,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsc->AbortReceiveCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1168,7 +1524,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief This function handles SMARTCARD interrupt request.
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1218,10 +1574,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
- /* Call the Error call Back in case of Errors */
+ /* Call the Error call Back in case of Errors --------------------------*/
if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
- /* SMARTCARD in mode Receiver -----------------------------------------------*/
+ /* SMARTCARD in mode Receiver ----------------------------------------*/
if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
SMARTCARD_Receive_IT(hsc);
@@ -1256,34 +1612,51 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsc->ErrorCallback(hsc);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsc->ErrorCallback(hsc);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsc->ErrorCallback(hsc);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
- /* SMARTCARD in mode Transmitter -------------------------------------------*/
+ /* SMARTCARD in mode Transmitter ------------------------------------------*/
if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
SMARTCARD_Transmit_IT(hsc);
return;
}
- /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ /* SMARTCARD in mode Transmitter (transmission end) -----------------------*/
if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
@@ -1293,22 +1666,23 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Tx Transfer completed callbacks
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Transfer completed callbacks
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Rx Transfer completed callback
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1316,23 +1690,25 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief SMARTCARD error callbacks
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief SMARTCARD error callback
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
*/
}
@@ -1361,13 +1737,13 @@ __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hs
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief SMARTCARD Abort ReceiveComplete callback.
+ * @brief SMARTCARD Abort Receive Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
@@ -1376,9 +1752,9 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
}
/**
@@ -1401,8 +1777,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc
*/
/**
- * @brief return the SMARTCARD state
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Return the SMARTCARD handle state
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL state
*/
@@ -1417,7 +1793,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Return the SMARTCARD error code
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD.
* @retval SMARTCARD Error Code
*/
@@ -1430,9 +1806,36 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
* @}
*/
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param hsc SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @brief DMA SMARTCARD transmit process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1443,7 +1846,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
hsc->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
+ in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Enable the SMARTCARD Transmit Complete Interrupt */
@@ -1452,7 +1855,7 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SMARTCARD receive process complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1467,18 +1870,24 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
+ in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsc->RxCpltCallback(hsc);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD communication error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1504,16 +1913,23 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
SMARTCARD_EndRxTransfer(hsc);
}
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsc->ErrorCallback(hsc);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief This function handles SMARTCARD Communication Timeout.
- * @param hsc SMARTCARD handle
- * @param Flag specifies the SMARTCARD flag to check.
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
@@ -1545,7 +1961,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
/**
* @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsc SMARTCARD handle.
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
@@ -1560,7 +1977,8 @@ static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
- * @param hsc SMARTCARD handle.
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
@@ -1575,7 +1993,7 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -1609,29 +2027,35 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
/**
* @brief Wraps up transmission in non blocking mode.
- * @param hsmartcard pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ /* Tx process is ended, restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsc->TxCpltCallback(hsc);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
return HAL_OK;
}
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -1656,10 +2080,16 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
- /* Rx process is completed, restore hsc->RxState to Ready */
+ /* Rx process is completed, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsc->RxCpltCallback(hsc);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
return HAL_OK;
}
@@ -1683,7 +2113,13 @@ static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
hsc->RxXferCount = 0x00U;
hsc->TxXferCount = 0x00U;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsc->ErrorCallback(hsc);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1720,8 +2156,13 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsc->AbortCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1758,8 +2199,13 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsc->AbortCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1779,8 +2225,13 @@ static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsc->AbortTransmitCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1800,13 +2251,18 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsc->AbortReceiveCpltCallback(hsc);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief Configure the SMARTCARD peripheral
- * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smbus.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smbus.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e7c5088176e57b40f7ddbd3298e831369994c94
--- /dev/null
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_smbus.c
@@ -0,0 +1,2791 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_smbus.c
+ * @author MCD Application Team
+ * @brief SMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on SMBUS principals of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State, Mode and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
+ Dual Addressing mode, Own Address2, General call and Nostretch mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver :
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/Host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
+ (++) End of abort process, @ref HAL_SMBUS_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_AbortCpltCallback()
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+ (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() and @ref HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function @ref HAL_SMBUS_GetError()
+
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) @ref __HAL_SMBUS_ENABLE : Enable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_DISABLE : Disable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
+ (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) @ref __HAL_SMBUS_ENABLE_IT : Enable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback().
+
+ Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback().
+
+ By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_SMBUS_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in @ref HAL_SMBUS_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_SMBUS_STATE_READY or @ref HAL_SMBUS_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
+ or @ref HAL_SMBUS_Init() function.
+
+ When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup SMBUS_Private_Define
+ * @{
+ */
+#define SMBUS_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
+#define SMBUS_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
+#define SMBUS_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
+
+#define SMBUS_SENDPEC_MODE I2C_CR1_PEC
+#define SMBUS_GET_PEC(__HANDLE__) (((__HANDLE__)->Instance->SR2 & I2C_SR2_PEC) >> 8)
+
+/* Private define for @ref PreviousState usage */
+#define SMBUS_STATE_MSK ((uint32_t)((HAL_SMBUS_STATE_BUSY_TX | HAL_SMBUS_STATE_BUSY_RX) & (~(uint32_t)HAL_SMBUS_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
+#define SMBUS_STATE_NONE ((uint32_t)(HAL_SMBUS_MODE_NONE)) /*!< Default Value */
+#define SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_SMBUS_STATE_BUSY_TX & SMBUS_STATE_MSK) | HAL_SMBUS_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_SMBUS_STATE_BUSY_RX & SMBUS_STATE_MSK) | HAL_SMBUS_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_SMBUS_STATE_BUSY_TX & SMBUS_STATE_MSK) | HAL_SMBUS_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_SMBUS_STATE_BUSY_RX & SMBUS_STATE_MSK) | HAL_SMBUS_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @addtogroup SMBUS_Private_Functions
+ * @{
+ */
+
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private functions for SMBUS transfer IRQ handler */
+static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_MasterReceive_RXNE(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_MasterReceive_BTF(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Master_SB(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Master_ADD10(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Master_ADDR(SMBUS_HandleTypeDef *hsmbus);
+
+static HAL_StatusTypeDef SMBUS_SlaveTransmit_TXE(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_SlaveTransmit_BTF(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_SlaveReceive_RXNE(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_SlaveReceive_BTF(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ADDR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_STOPF(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_AF(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Communication Speed
+ (++) Addressing mode
+ (++) Own Address 1
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t freqrange = 0U;
+ uint32_t pclk1 = 0U;
+
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+#if defined(I2C_FLTR_ANOFF)
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+#endif
+ assert_param(IS_SMBUS_CLOCK_SPEED(hsmbus->Init.ClockSpeed));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ /* Init the SMBUS Callback settings */
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmbus->AbortCpltCallback = HAL_SMBUS_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hsmbus->MspInitCallback == NULL)
+ {
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ hsmbus->MspInitCallback(hsmbus);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get PCLK1 frequency */
+ pclk1 = HAL_RCC_GetPCLK1Freq();
+
+ /* Calculate frequency range */
+ freqrange = SMBUS_FREQRANGE(pclk1);
+
+ /*---------------------------- SMBUSx CR2 Configuration ----------------------*/
+ /* Configure SMBUSx: Frequency range */
+ MODIFY_REG(hsmbus->Instance->CR2, I2C_CR2_FREQ, freqrange);
+
+ /*---------------------------- SMBUSx TRISE Configuration --------------------*/
+ /* Configure SMBUSx: Rise Time */
+ MODIFY_REG(hsmbus->Instance->TRISE, I2C_TRISE_TRISE, SMBUS_RISE_TIME(freqrange));
+
+ /*---------------------------- SMBUSx CCR Configuration ----------------------*/
+ /* Configure SMBUSx: Speed */
+ MODIFY_REG(hsmbus->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), SMBUS_SPEED_STANDARD(pclk1, hsmbus->Init.ClockSpeed));
+
+ /*---------------------------- SMBUSx CR1 Configuration ----------------------*/
+ /* Configure SMBUSx: Generalcall , PEC , Peripheral mode and NoStretch mode */
+ MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_PEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode));
+
+ /*---------------------------- SMBUSx OAR1 Configuration ---------------------*/
+ /* Configure SMBUSx: Own Address1 and addressing mode */
+ MODIFY_REG(hsmbus->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hsmbus->Init.AddressingMode | hsmbus->Init.OwnAddress1));
+
+ /*---------------------------- SMBUSx OAR2 Configuration ---------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ MODIFY_REG(hsmbus->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2));
+#if defined(I2C_FLTR_ANOFF)
+ /*---------------------------- SMBUSx FLTR Configuration ------------------------*/
+ /* Configure SMBUSx: Analog noise filter */
+ SET_BIT(hsmbus->Instance->FLTR, hsmbus->Init.AnalogFilter);
+#endif
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+ hsmbus->XferPEC = 0x00;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the SMBUS peripheral.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if (hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ if (hsmbus->MspDeInitCallback == NULL)
+ {
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hsmbus->MspDeInitCallback(hsmbus);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMBUS MSP.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMBUS MSP.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS
+ * @retval None
+ */
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
+/**
+ * @brief Configures SMBUS Analog noise filter.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @param AnalogFilter new state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset SMBUSx ANOFF bit */
+ hsmbus->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
+
+ /* Disable the analog filter */
+ hsmbus->Instance->FLTR |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configures SMBUS Digital noise filter.
+ * @param hsmbus pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->FLTR;
+
+ /* Reset SMBUSx DNF bit [3:0] */
+ tmpreg &= ~(I2C_FLTR_DNF);
+
+ /* Set SMBUSx DNF coefficient */
+ tmpreg |= DigitalFilter;
+
+ /* Store the new register value */
+ hsmbus->Instance->FLTR = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+#endif
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ABORT_CB_ID :
+ hsmbus->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an SMBUS Callback
+ * SMBUS callback is redirected to the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMBUS_ABORT_CB_ID :
+ hsmbus->AbortCpltCallback = HAL_SMBUS_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match SMBUS Callback
+ * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match SMBUS Callback
+ * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) Non Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Master_Abort_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+ (++) HAL_SMBUS_AbortCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t count = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (XferOptions == SMBUS_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = SMBUS_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ if (count-- == 0U)
+ {
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_MASTER;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+ hsmbus->XferSize = hsmbus->XferCount;
+ hsmbus->Devaddress = DevAddress;
+
+ /* Generate Start */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of hsmbus interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in non blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if ((XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (XferOptions == SMBUS_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = SMBUS_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+ do
+ {
+ if (count-- == 0U)
+ {
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_MASTER;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+ hsmbus->XferSize = hsmbus->XferCount;
+ hsmbus->Devaddress = DevAddress;
+
+ if ((hsmbus->PreviousState == SMBUS_STATE_MASTER_BUSY_TX) || (hsmbus->PreviousState == SMBUS_STATE_NONE))
+ {
+ /* Generate Start condition if first transfer */
+ if ((XferOptions == SMBUS_NEXT_FRAME) || (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (XferOptions == SMBUS_FIRST_FRAME) || (XferOptions == SMBUS_NO_OPTION_FRAME))
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+ }
+
+ if ((XferOptions == SMBUS_LAST_FRAME_NO_PEC) || (XferOptions == SMBUS_LAST_FRAME_WITH_PEC))
+ {
+ if (hsmbus->PreviousState == SMBUS_STATE_NONE)
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+ }
+
+ if (hsmbus->PreviousState == SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Start */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+ }
+ }
+ }
+
+
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(DevAddress);
+ if (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_ABORT;
+
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ hsmbus->XferCount = 0U;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ SMBUS_ITError(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY_TX_LISTEN;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_SLAVE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+ hsmbus->XferSize = hsmbus->XferCount;
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY_RX_LISTEN;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_SLAVE;
+
+
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+ hsmbus->XferSize = hsmbus->XferCount;
+
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Enable Address Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hsmbus->State) & SMBUS_STATE_MSK;
+ hsmbus->PreviousState = tmp | (uint32_t)(hsmbus->Mode);
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+ /* Disable Address Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ALERT);
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_SMBALERT);
+
+ /* Enable Alert Interrupt */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, SMBUS_IT_ERR);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable SMBus alert */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ALERT);
+
+ /* Disable Alert Interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ERR);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, SMBUS_Trials = 1U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Wait until BUSY flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_BUSY, SET, SMBUS_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Check if the SMBUS is already enabled */
+ if ((hsmbus->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+ }
+
+ /* Disable Pos */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->XferOptions = SMBUS_NO_OPTION_FRAME;
+
+ do
+ {
+ /* Generate Start */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+
+ /* Wait until SB flag is set */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Send slave address */
+ hsmbus->Instance->DR = SMBUS_7BIT_ADD_WRITE(DevAddress);
+
+ /* Wait until ADDR or AF flag are set */
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+ tmp3 = hsmbus->State;
+ while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_SMBUS_STATE_TIMEOUT))
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hsmbus->State = HAL_SMBUS_STATE_TIMEOUT;
+ }
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+ tmp3 = hsmbus->State;
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Check if the ADDR flag has been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) == SET)
+ {
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear ADDR Flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Wait until BUSY flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_BUSY, SET, SMBUS_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ /* Clear AF Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Wait until BUSY flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_BUSY, SET, SMBUS_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ while (SMBUS_Trials++ < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles SMBUS event interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t sr2itflags = READ_REG(hsmbus->Instance->SR2);
+ uint32_t sr1itflags = READ_REG(hsmbus->Instance->SR1);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR2);
+
+ uint32_t CurrentMode = hsmbus->Mode;
+
+ /* Master mode selected */
+ if (CurrentMode == HAL_SMBUS_MODE_MASTER)
+ {
+ /* SB Set ----------------------------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_SB) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_Master_SB(hsmbus);
+ }
+ /* ADD10 Set -------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_ADD10) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_Master_ADD10(hsmbus);
+ }
+ /* ADDR Set --------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_ADDR) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_Master_ADDR(hsmbus);
+ }
+ /* SMBUS in mode Transmitter -----------------------------------------------*/
+ if ((sr2itflags & SMBUS_FLAG_TRA) != RESET)
+ {
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_TXE) != RESET) && ((itsources & SMBUS_IT_BUF) != RESET) && ((sr1itflags & SMBUS_FLAG_BTF) == RESET))
+ {
+ SMBUS_MasterTransmit_TXE(hsmbus);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_BTF) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_MasterTransmit_BTF(hsmbus);
+ }
+ }
+ /* SMBUS in mode Receiver --------------------------------------------------*/
+ else
+ {
+ /* RXNE set and BTF reset -----------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_RXNE) != RESET) && ((itsources & SMBUS_IT_BUF) != RESET) && ((sr1itflags & SMBUS_FLAG_BTF) == RESET))
+ {
+ SMBUS_MasterReceive_RXNE(hsmbus);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_BTF) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_MasterReceive_BTF(hsmbus);
+ }
+ }
+ }
+ /* Slave mode selected */
+ else
+ {
+ /* ADDR set --------------------------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_ADDR) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_Slave_ADDR(hsmbus);
+ }
+ /* STOPF set --------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_STOPF) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_Slave_STOPF(hsmbus);
+ }
+ /* SMBUS in mode Transmitter -----------------------------------------------*/
+ else if ((sr2itflags & SMBUS_FLAG_TRA) != RESET)
+ {
+ /* TXE set and BTF reset -----------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_TXE) != RESET) && ((itsources & SMBUS_IT_BUF) != RESET) && ((sr1itflags & SMBUS_FLAG_BTF) == RESET))
+ {
+ SMBUS_SlaveTransmit_TXE(hsmbus);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_BTF) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_SlaveTransmit_BTF(hsmbus);
+ }
+ }
+ /* SMBUS in mode Receiver --------------------------------------------------*/
+ else
+ {
+ /* RXNE set and BTF reset ----------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_RXNE) != RESET) && ((itsources & SMBUS_IT_BUF) != RESET) && ((sr1itflags & SMBUS_FLAG_BTF) == RESET))
+ {
+ SMBUS_SlaveReceive_RXNE(hsmbus);
+ }
+ /* BTF set -------------------------------------------------------------*/
+ else if (((sr1itflags & SMBUS_FLAG_BTF) != RESET) && ((itsources & SMBUS_IT_EVT) != RESET))
+ {
+ SMBUS_SlaveReceive_BTF(hsmbus);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles SMBUS error interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+ uint32_t sr1itflags = READ_REG(hsmbus->Instance->SR1);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR2);
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Acknowledge failure error interrupt occurred ------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_AF) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ tmp1 = hsmbus->Mode;
+ tmp2 = hsmbus->XferCount;
+ tmp3 = hsmbus->State;
+ tmp4 = hsmbus->PreviousState;
+
+ if ((tmp1 == HAL_SMBUS_MODE_SLAVE) && (tmp2 == 0U) && \
+ ((tmp3 == HAL_SMBUS_STATE_BUSY_TX) || (tmp3 == HAL_SMBUS_STATE_BUSY_TX_LISTEN) || \
+ ((tmp3 == HAL_SMBUS_STATE_LISTEN) && (tmp4 == SMBUS_STATE_SLAVE_BUSY_TX))))
+ {
+ SMBUS_Slave_AF(hsmbus);
+ }
+ else
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_AF;
+
+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+ if (hsmbus->Mode == HAL_SMBUS_MODE_MASTER)
+ {
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ }
+
+ /* Clear AF flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+ }
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_TIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_SMBALERT) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_SMBALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((sr1itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET))
+ {
+ hsmbus->ErrorCode |= SMBUS_FLAG_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected -----------------------*/
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ SMBUS_ITError(hsmbus);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterTxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MasterRxCpltCallback can be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveTxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_SlaveRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref SMBUS_XferOptions_definition
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS abort callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_AbortCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmbus);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AbortCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL state
+ */
+HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Return SMBUS handle state */
+ return hsmbus->State;
+}
+
+/**
+ * @brief Return the SMBUS Master, Slave or no mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL mode
+ */
+HAL_SMBUS_ModeTypeDef HAL_SMBUS_GetMode(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->Mode;
+}
+
+/**
+ * @brief Return the SMBUS error code
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval SMBUS Error Code
+ */
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Handle TXE flag for Master
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+ uint32_t CurrentMode = hsmbus->Mode;
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+
+ if ((hsmbus->XferSize == 0U) && (CurrentState == HAL_SMBUS_STATE_BUSY_TX))
+ {
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if (((CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)) && \
+ ((CurrentXferOptions != SMBUS_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_LAST_FRAME_WITH_PEC)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
+ {
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ hsmbus->PreviousState = SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ else if ((CurrentState == HAL_SMBUS_STATE_BUSY_TX))
+ {
+
+ if ((hsmbus->XferCount == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC)))
+ {
+ hsmbus->XferCount--;
+ }
+
+ if (hsmbus->XferCount == 0U)
+ {
+
+ /* Disable BUF interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+
+ if ((SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC)))
+ {
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_PEC);
+ }
+
+ }
+ else
+ {
+ /* Write data to DR */
+ hsmbus->Instance->DR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master transmitter
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_BUSY_TX)
+ {
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hsmbus->Instance->DR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ }
+ else
+ {
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if (((CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)) && ((CurrentXferOptions != SMBUS_LAST_FRAME_NO_PEC) || (CurrentXferOptions != SMBUS_LAST_FRAME_WITH_PEC)) && (CurrentXferOptions != SMBUS_NO_OPTION_FRAME))
+ {
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ hsmbus->PreviousState = SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Master
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_MasterReceive_RXNE(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_BUSY_RX)
+ {
+ uint32_t tmp = hsmbus->XferCount;
+
+ if (tmp > 3U)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ if (hsmbus->XferCount == 3)
+ {
+ /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
+ on BTF subroutine */
+ /* Disable BUF interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+ }
+ }
+
+ else if (tmp == 2U)
+ {
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ if ((CurrentXferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (CurrentXferOptions == SMBUS_LAST_FRAME_WITH_PEC))
+ {
+ /* PEC of slave */
+ hsmbus->XferPEC = SMBUS_GET_PEC(hsmbus);
+
+ }
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+ }
+
+ else if ((tmp == 1U) || (tmp == 0U))
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Master receiver
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_MasterReceive_BTF(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+
+ if (hsmbus->XferCount == 4U)
+ {
+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+ on BTF subroutine if there is a reception delay between N-1 and N byte */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+ hsmbus->XferPEC = SMBUS_GET_PEC(hsmbus);
+ }
+ else if (hsmbus->XferCount == 3U)
+ {
+ /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+ on BTF subroutine if there is a reception delay between N-1 and N byte */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+ hsmbus->XferPEC = SMBUS_GET_PEC(hsmbus);
+ }
+ else if (hsmbus->XferCount == 2U)
+ {
+ /* Prepare next transfer or stop current transfer */
+ if ((CurrentXferOptions == SMBUS_NEXT_FRAME) || (CurrentXferOptions == SMBUS_FIRST_FRAME) || (CurrentXferOptions == SMBUS_LAST_FRAME_NO_PEC))
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Generate ReStart */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+ }
+ else
+ {
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+ }
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_ERR);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SB flag for Master
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_SB(SMBUS_HandleTypeDef *hsmbus)
+{
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave 7 Bits address */
+ if (hsmbus->State == HAL_SMBUS_STATE_BUSY_TX)
+ {
+ hsmbus->Instance->DR = SMBUS_7BIT_ADD_WRITE(hsmbus->Devaddress);
+ }
+ else
+ {
+ hsmbus->Instance->DR = SMBUS_7BIT_ADD_READ(hsmbus->Devaddress);
+ }
+ }
+ else
+ {
+ if (hsmbus->EventCount == 0U)
+ {
+ /* Send header of slave address */
+ hsmbus->Instance->DR = SMBUS_10BIT_HEADER_WRITE(hsmbus->Devaddress);
+ }
+ else if (hsmbus->EventCount == 1U)
+ {
+ /* Send header of slave address */
+ hsmbus->Instance->DR = SMBUS_10BIT_HEADER_READ(hsmbus->Devaddress);
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD10 flag for Master
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ADD10(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Send slave address */
+ hsmbus->Instance->DR = SMBUS_10BIT_ADDRESS(hsmbus->Devaddress);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADDR flag for Master
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ADDR(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentMode = hsmbus->Mode;
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+ uint32_t Prev_State = hsmbus->PreviousState;
+
+ if (hsmbus->State == HAL_SMBUS_STATE_BUSY_RX)
+ {
+ if ((hsmbus->EventCount == 0U) && (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT))
+ {
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Generate Restart */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_START);
+
+ hsmbus->EventCount++;
+ }
+ else
+ {
+ /* In the case of the Quick Command, the ADDR flag is cleared and a stop is generated */
+ if (hsmbus->XferCount == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+ }
+ else if (hsmbus->XferCount == 1U)
+ {
+ /* Prepare next transfer or stop current transfer */
+ if ((hsmbus->XferOptions == SMBUS_FIRST_FRAME) && (Prev_State != SMBUS_STATE_MASTER_BUSY_RX))
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+ }
+ else if ((hsmbus->XferOptions == SMBUS_NEXT_FRAME) && (Prev_State != SMBUS_STATE_MASTER_BUSY_RX))
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+ }
+ else
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+
+ /* Generate Stop */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP);
+ }
+ }
+ else if (hsmbus->XferCount == 2U)
+ {
+ if (hsmbus->XferOptions != SMBUS_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Enable Pos */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+ }
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+ }
+
+ /* Reset Event counter */
+ hsmbus->EventCount = 0U;
+ }
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_ADDRFLAG(hsmbus);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TXE flag for Slave
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_SlaveTransmit_TXE(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hsmbus->Instance->DR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+
+ if ((hsmbus->XferCount == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC)))
+ {
+ hsmbus->XferCount--;
+ }
+
+ if ((hsmbus->XferCount == 0U) && (CurrentState == (HAL_SMBUS_STATE_BUSY_TX_LISTEN)))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+
+ /* Set state at HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = SMBUS_STATE_SLAVE_BUSY_TX;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave transmitter
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_SlaveTransmit_BTF(SMBUS_HandleTypeDef *hsmbus)
+{
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hsmbus->Instance->DR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ }
+
+
+
+ else if ((hsmbus->XferCount == 0U) && (SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC)))
+ {
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_PEC);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Slave
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_SlaveReceive_RXNE(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+
+ if ((hsmbus->XferCount == 1U) && (SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC)))
+ {
+ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_PEC);
+ hsmbus->XferPEC = SMBUS_GET_PEC(hsmbus);
+ }
+ if ((hsmbus->XferCount == 0U) && (CurrentState == HAL_SMBUS_STATE_BUSY_RX_LISTEN))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_BUF);
+
+ /* Set state at HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = SMBUS_STATE_SLAVE_BUSY_RX;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BTF flag for Slave receiver
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_SlaveReceive_BTF(SMBUS_HandleTypeDef *hsmbus)
+{
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ hsmbus->XferCount--;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD flag for Slave
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ADDR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint8_t TransferDirection = SMBUS_DIRECTION_RECEIVE ;
+ uint16_t SlaveAddrCode = 0U;
+
+ /* Transfer Direction requested by Master */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TRA) == RESET)
+ {
+ TransferDirection = SMBUS_DIRECTION_TRANSMIT;
+ }
+
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_DUALF) == RESET)
+ {
+ SlaveAddrCode = hsmbus->Init.OwnAddress1;
+ }
+ else
+ {
+ SlaveAddrCode = hsmbus->Init.OwnAddress2;
+ }
+
+ /* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle STOPF flag for Slave
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_STOPF(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Clear STOPF flag */
+ __HAL_SMBUS_CLEAR_STOPFLAG(hsmbus);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ /* All data are not transferred, so set error code accordingly */
+ if (hsmbus->XferCount != 0U)
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+
+ if (hsmbus->XferCount > 0)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+
+ if (hsmbus->XferCount > 0)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ SMBUS_ITError(hsmbus);
+ }
+ else
+ {
+ if ((CurrentState == HAL_SMBUS_STATE_LISTEN) || (CurrentState == HAL_SMBUS_STATE_BUSY_RX_LISTEN) || \
+ (CurrentState == HAL_SMBUS_STATE_BUSY_TX_LISTEN))
+ {
+ hsmbus->XferOptions = SMBUS_NO_OPTION_FRAME;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_AF(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+ uint32_t CurrentXferOptions = hsmbus->XferOptions;
+
+ if (((CurrentXferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || (CurrentXferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ (CurrentXferOptions == SMBUS_LAST_FRAME_NO_PEC) || (CurrentXferOptions == SMBUS_LAST_FRAME_WITH_PEC)) && \
+ (CurrentState == HAL_SMBUS_STATE_LISTEN))
+ {
+ hsmbus->XferOptions = SMBUS_NO_OPTION_FRAME;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR);
+
+ /* Clear AF flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Disable Acknowledge */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_ACK);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief SMBUS interrupts error process
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hsmbus->State;
+
+ if ((CurrentState == HAL_SMBUS_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_SMBUS_STATE_BUSY_RX_LISTEN))
+ {
+ /* keep HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ else
+ {
+ /* If state is an abort treatment on going, don't change state */
+ /* This change will be done later */
+ if (hsmbus->State != HAL_SMBUS_STATE_ABORT)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ }
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+ }
+
+ /* Disable Pos bit in SMBUS CR1 when error occurred in Master/Mem Receive IT Process */
+ CLEAR_BIT(hsmbus->Instance->CR1, I2C_CR1_POS);
+
+ if (hsmbus->State == HAL_SMBUS_STATE_ABORT)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ }
+
+ /* Disable SMBUS peripheral to prevent dummy data in buffer */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AbortCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_AbortCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Store Last receive data if any */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->DR;
+ }
+
+ /* Call user error callback */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
+ HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ /* STOP Flag is not set after a NACK reception */
+ /* So may inform upper layer that listen phase is stopped */
+ /* during NACK error treatment */
+ if ((hsmbus->State == HAL_SMBUS_STATE_LISTEN) && ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_AF) == HAL_SMBUS_ERROR_AF))
+ {
+ hsmbus->XferOptions = SMBUS_NO_OPTION_FRAME;
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief This function handles SMBUS Communication Timeout.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for SMBUS module
+ * @param Flag specifies the SMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Wait until flag is set */
+ if (Status == RESET)
+ {
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = SMBUS_STATE_NONE;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->Mode = HAL_SMBUS_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spdifrx.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spdifrx.c
index 47ab55c3895f46545ba5dc84f1c46a87a5c6c76e..1ba1c4d7e32de0c524d7984db6e163f80603b8cd 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spdifrx.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spdifrx.c
@@ -10,7 +10,7 @@
* + Interrupts and flags management
@verbatim
===============================================================================
- ##### How to use this driver #####
+ ##### How to use this driver #####
===============================================================================
[..]
The SPDIFRX HAL driver can be used as follow:
@@ -32,7 +32,7 @@
(+++) Configure the DMA Channel.
(+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA CtrlRx/DataRx channel.
+ DMA CtrlRx/DataRx channel.
(#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
using HAL_SPDIFRX_Init() function.
@@ -47,7 +47,7 @@
================================================================
[..]
(+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()
- (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
+ (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()
*** Interrupt mode for reception operation ***
=========================================
@@ -88,33 +88,70 @@
[..]
(@) You can refer to the SPDIFRX HAL driver header file for more useful macros
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback.
+
+ The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks:
+ (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
+ (+) RxCpltCallback : SPDIFRX Data flow completed callback.
+ (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback.
+ (+) CxCpltCallback : SPDIFRX Control flow completed callback.
+ (+) ErrorCallback : SPDIFRX error callback.
+ (+) MspInitCallback : SPDIFRX MspInit.
+ (+) MspDeInitCallback : SPDIFRX MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default
+ weak function.
+ The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset the following callbacks:
+ (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback.
+ (+) RxCpltCallback : SPDIFRX Data flow completed callback.
+ (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback.
+ (+) CxCpltCallback : SPDIFRX Control flow completed callback.
+ (+) ErrorCallback : SPDIFRX error callback.
+ (+) MspInitCallback : SPDIFRX MspInit.
+ (+) MspDeInitCallback : SPDIFRX MspDeInit.
+
+ By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(),
+ HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback()
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when
+ these callbacks pointers are NULL (not registered beforehand).
+ If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit()
+ or HAL_SPDIFRX_Init() function.
+
+ When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -125,23 +162,22 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+
/** @defgroup SPDIFRX SPDIFRX
* @brief SPDIFRX HAL module driver
* @{
*/
#ifdef HAL_SPDIFRX_MODULE_ENABLED
-
+#if defined (SPDIFRX)
#if defined(STM32F446xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define SPDIFRX_TIMEOUT_VALUE 0xFFFF
+#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
/** @addtogroup SPDIFRX_Private_Functions
* @{
*/
@@ -152,8 +188,7 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
/**
* @}
*/
@@ -168,26 +203,26 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
*
@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialize the SPDIFRX peripheral:
-
- (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
- all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
- (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
- the selected configuration:
- (++) Input Selection (IN0, IN1,...)
- (++) Maximum allowed re-tries during synchronization phase
- (++) Wait for activity on SPDIF selected input
- (++) Channel status selection (from channel A or B)
- (++) Data format (LSB, MSB, ...)
- (++) Stereo mode
- (++) User bits masking (PT,C,U,V,...)
-
- (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
- of the selected SPDIFRXx peripheral.
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPDIFRX peripheral:
+
+ (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with
+ the selected configuration:
+ (++) Input Selection (IN0, IN1,...)
+ (++) Maximum allowed re-tries during synchronization phase
+ (++) Wait for activity on SPDIF selected input
+ (++) Channel status selection (from channel A or B)
+ (++) Data format (LSB, MSB, ...)
+ (++) Stereo mode
+ (++) User bits masking (PT,C,U,V,...)
+
+ (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration
+ of the selected SPDIFRXx peripheral.
@endverbatim
* @{
*/
@@ -200,7 +235,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *
*/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
@@ -220,6 +255,27 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspdif->Lock = HAL_UNLOCKED;
+
+ hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */
+ hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */
+ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if(hspdif->MspInitCallback == NULL)
+ {
+ hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hspdif->MspInitCallback(hspdif);
+ }
+#else
if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -227,9 +283,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SPDIFRX_MspInit(hspdif);
}
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
- /* SPDIFRX peripheral state is BUSY*/
- hspdif->State = HAL_SPDIFRX_STATE_BUSY;
+ /* SPDIFRX peripheral state is BUSY */
+ hspdif->State = HAL_SPDIFRX_STATE_BUSY;
/* Disable SPDIFRX interface (IDLE State) */
__HAL_SPDIFRX_IDLE(hspdif);
@@ -237,28 +294,30 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
/* Reset the old SPDIFRX CR configuration */
tmpreg = hspdif->Instance->CR;
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
- SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
- SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
- SPDIFRX_CR_INSEL);
+ tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
+ SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA |
+ SPDIFRX_CR_INSEL);
/* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
- hspdif->Init.InputSelection |
- hspdif->Init.Retries |
- hspdif->Init.WaitForActivity |
- hspdif->Init.ChannelSelection |
- hspdif->Init.DataFormat |
- hspdif->Init.PreambleTypeMask |
- hspdif->Init.ChannelStatusMask |
- hspdif->Init.ValidityBitMask |
- hspdif->Init.ParityErrorMask);
+ tmpreg |= (hspdif->Init.StereoMode |
+ hspdif->Init.InputSelection |
+ hspdif->Init.Retries |
+ hspdif->Init.WaitForActivity |
+ hspdif->Init.ChannelSelection |
+ hspdif->Init.DataFormat |
+ hspdif->Init.PreambleTypeMask |
+ hspdif->Init.ChannelStatusMask |
+ hspdif->Init.ValidityBitMask |
+ hspdif->Init.ParityErrorMask
+ );
+
hspdif->Instance->CR = tmpreg;
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
- /* SPDIFRX peripheral state is READY*/
+ /* SPDIFRX peripheral state is READY*/
hspdif->State = HAL_SPDIFRX_STATE_READY;
return HAL_OK;
@@ -285,8 +344,18 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
/* Disable SPDIFRX interface (IDLE state) */
__HAL_SPDIFRX_IDLE(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ if(hspdif->MspDeInitCallback == NULL)
+ {
+ hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hspdif->MspDeInitCallback(hspdif);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPDIFRX_MspDeInit(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
@@ -308,8 +377,9 @@ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_MspInit could be implemented in the user file
+ the HAL_SPDIFRX_MspInit could be implemented in the user file
*/
}
@@ -322,21 +392,213 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPDIFRX_MspDeInit could be implemented in the user file
+ the HAL_SPDIFRX_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
/**
- * @brief Sets the SPDIFRX dtat format according to the specified parameters
- * in the SPDIFRX_InitTypeDef.
+ * @brief Register a User SPDIFRX Callback
+ * To be used instead of the weak predefined callback
+ * @param hspdif SPDIFRX handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
+ * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspdif);
+
+ if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_RX_HALF_CB_ID :
+ hspdif->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_RX_CPLT_CB_ID :
+ hspdif->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_HALF_CB_ID :
+ hspdif->CxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_CPLT_CB_ID :
+ hspdif->CxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_ERROR_CB_ID :
+ hspdif->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+ return status;
+}
+
+/**
+ * @brief Unregister a SPDIFRX Callback
+ * SPDIFRX callabck is redirected to the weak predefined callback
+ * @param hspdif SPDIFRX handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID
+ * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID
+ * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID
+ * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
+{
+HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspdif);
+
+ if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_RX_HALF_CB_ID :
+ hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_RX_CPLT_CB_ID :
+ hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_HALF_CB_ID :
+ hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_CX_CPLT_CB_ID :
+ hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback;
+ break;
+
+ case HAL_SPDIFRX_ERROR_CB_ID :
+ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPDIFRX_MSPINIT_CB_ID :
+ hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPDIFRX_MSPDEINIT_CB_ID :
+ hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspdif);
+ return status;
+}
+
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
+
+/**
+ * @brief Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef.
* @param hspdif SPDIFRX handle
* @param sDataFormat SPDIFRX data format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
@@ -356,22 +618,22 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
tmpreg = hspdif->Instance->CR;
if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
- (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
- ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
- tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
- SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
+ tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
+ SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
- /* Sets the new configuration of the SPDIFRX peripheral */
- tmpreg |= ((uint16_t) sDataFormat.StereoMode |
- sDataFormat.DataFormat |
- sDataFormat.PreambleTypeMask |
- sDataFormat.ChannelStatusMask |
- sDataFormat.ValidityBitMask |
- sDataFormat.ParityErrorMask);
+ /* Configure the new data format */
+ tmpreg |= (sDataFormat.StereoMode |
+ sDataFormat.DataFormat |
+ sDataFormat.PreambleTypeMask |
+ sDataFormat.ChannelStatusMask |
+ sDataFormat.ValidityBitMask |
+ sDataFormat.ParityErrorMask);
hspdif->Instance->CR = tmpreg;
@@ -387,7 +649,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
*
@verbatim
===============================================================================
- ##### IO operation functions #####
+ ##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the SPDIFRX data
@@ -418,11 +680,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
(++) HAL_SPDIFRX_RxCpltCallback()
- (++) HAL_SPDIFRX_ErrorCallback()
+ (++) HAL_SPDIFRX_CxCpltCallback()
@endverbatim
- * @{
- */
+* @{
+*/
/**
* @brief Receives an amount of data (Data Flow) in blocking mode.
@@ -435,7 +697,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tickstart;
+ uint16_t sizeCounter = Size;
+ uint32_t *pTmpBuf = pData;
+
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -450,8 +716,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
/* Start synchronisation */
__HAL_SPDIFRX_SYNC(hspdif);
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -460,16 +729,20 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
__HAL_SPDIFRX_RCV(hspdif);
/* Receive data flow */
- while(Size > 0)
+ while(sizeCounter > 0U)
{
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until RXNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- (*pData++) = hspdif->Instance->DR;
- Size--;
+ (*pTmpBuf) = hspdif->Instance->DR;
+ pTmpBuf++;
+ sizeCounter--;
}
/* SPDIFRX ready */
@@ -497,7 +770,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tickstart;
+ uint16_t sizeCounter = Size;
+ uint32_t *pTmpBuf = pData;
+
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -512,8 +789,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout) != HAL_OK)
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -522,16 +802,20 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_RCV(hspdif);
/* Receive control flow */
- while(Size > 0)
+ while(sizeCounter > 0U)
{
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait until CSRNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout) != HAL_OK)
+ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- (*pData++) = hspdif->Instance->CSR;
- Size--;
+ (*pTmpBuf) = hspdif->Instance->CSR;
+ pTmpBuf++;
+ sizeCounter--;
}
/* SPDIFRX ready */
@@ -547,6 +831,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
return HAL_BUSY;
}
}
+
/**
* @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt
* @param hspdif SPDIFRX handle
@@ -556,11 +841,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif,
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -583,13 +870,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
/* Enable the SPDIFRX OVR Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
/* Enable the SPDIFRX RXNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -597,7 +881,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
/* Wait until SYNCD flag is set */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
@@ -615,13 +899,16 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
return HAL_TIMEOUT;
}
- }
- while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
return HAL_OK;
}
else
@@ -634,16 +921,18 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
* @brief Receive an amount of data (Control Flow) with Interrupt
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data sample (Control Flow) to be received :
+ * @param Size number of data sample (Control Flow) to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -666,13 +955,10 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
/* Enable the SPDIFRX OVR Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
/* Enable the SPDIFRX CSRNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -680,7 +966,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
/* Wait until SYNCD flag is set */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
@@ -698,13 +984,16 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
return HAL_TIMEOUT;
}
- }
- while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
return HAL_OK;
}
else
@@ -717,27 +1006,29 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi
* @brief Receive an amount of data (Data Flow) mode with DMA
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be received :
+ * @param Size number of data sample to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
- if((pData == NULL) || (Size == 0))
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
+
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
+ /* Process Locked */
+ __HAL_LOCK(hspdif);
+
hspdif->pRxBuffPtr = pData;
hspdif->RxXferSize = Size;
hspdif->RxXferCount = Size;
- /* Process Locked */
- __HAL_LOCK(hspdif);
-
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;
@@ -751,12 +1042,24 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);
+ if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set SPDIFRX error */
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+ /* Set SPDIFRX state */
+ hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_ERROR;
+ }
/* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
- if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -764,7 +1067,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
/* Wait until SYNCD flag is set */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
@@ -782,8 +1085,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
return HAL_TIMEOUT;
}
- }
- while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
@@ -804,19 +1107,21 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
* @brief Receive an amount of data (Control Flow) with DMA
* @param hspdif SPDIFRX handle
* @param pData a 32-bit pointer to the Receive data buffer.
- * @param Size number of data (Control Flow) sample to be received :
+ * @param Size number of data (Control Flow) sample to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
- __IO uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+ register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U);
+
+ const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
+ if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
hspdif->pCsBuffPtr = pData;
hspdif->CsXferSize = Size;
@@ -838,12 +1143,24 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd
hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
+ if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
+ {
+ /* Set SPDIFRX error */
+ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
+
+ /* Set SPDIFRX state */
+ hspdif->State = HAL_SPDIFRX_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
+
+ return HAL_ERROR;
+ }
/* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
- if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC || (SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)
+ if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -851,7 +1168,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd
/* Wait until SYNCD flag is set */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
@@ -869,8 +1186,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd
return HAL_TIMEOUT;
}
- }
- while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
+ count--;
+ } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET);
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
@@ -923,24 +1240,27 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
*/
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
{
- /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))
+ uint32_t itFlag = hspdif->Instance->SR;
+ uint32_t itSource = hspdif->Instance->IMR;
+
+ /* SPDIFRX in mode Data Flow Reception */
+ if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
SPDIFRX_ReceiveDataFlow_IT(hspdif);
}
- /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))
+ /* SPDIFRX in mode Control Flow Reception */
+ if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
SPDIFRX_ReceiveControlFlow_IT(hspdif);
}
- /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))
+ /* SPDIFRX Overrun error interrupt occurred */
+ if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
{
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
/* Change the SPDIFRX error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;
@@ -949,10 +1269,10 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
HAL_SPDIFRX_ErrorCallback(hspdif);
}
- /* SPDIFRX Parity error interrupt occurred ---------------------------------*/
- if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))
+ /* SPDIFRX Parity error interrupt occurred */
+ if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
{
- __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);
+ __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
/* Change the SPDIFRX error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;
@@ -971,9 +1291,10 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -985,9 +1306,10 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -999,9 +1321,10 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1013,9 +1336,10 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1027,9 +1351,10 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspdif);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SPDIFRX_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1041,11 +1366,11 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
*
@verbatim
===============================================================================
- ##### Peripheral State and Errors functions #####
+##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
+This subsection permit to get in run-time the status of the peripheral
+and the data flow.
@endverbatim
* @{
@@ -1053,20 +1378,20 @@ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)
/**
* @brief Return the SPDIFRX state
- * @param hspdif SPDIFRX handle
+ * @param hspdif SPDIFRX handle
* @retval HAL state
*/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif)
{
return hspdif->State;
}
/**
* @brief Return the SPDIFRX error code
- * @param hspdif SPDIFRX handle
+ * @param hspdif SPDIFRX handle
* @retval SPDIFRX Error Code
*/
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
{
return hspdif->ErrorCode;
}
@@ -1077,7 +1402,7 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)
/**
* @brief DMA SPDIFRX receive process (Data flow) complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -1085,28 +1410,39 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Disable Rx DMA Request */
- hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
- hspdif->RxXferCount = 0U;
-
- hspdif->State = HAL_SPDIFRX_STATE_READY;
+ if(hdma->Init.Mode != DMA_CIRCULAR)
+ {
+ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
+ hspdif->RxXferCount = 0;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
+ }
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxCpltCallback(hspdif);
+#else
HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX receive process (Data flow) half complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxHalfCpltCallback(hspdif);
+#else
HAL_SPDIFRX_RxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
+
/**
* @brief DMA SPDIFRX receive process (Control flow) complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
@@ -1115,27 +1451,35 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
/* Disable Cb DMA Request */
hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
- hspdif->CsXferCount = 0U;
+ hspdif->CsXferCount = 0;
hspdif->State = HAL_SPDIFRX_STATE_READY;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxCpltCallback(hspdif);
+#else
HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX receive process (Control flow) half complete callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
{
SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxHalfCpltCallback(hspdif);
+#else
HAL_SPDIFRX_CxHalfCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
* @brief DMA SPDIFRX communication error callback
- * @param hdma DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
@@ -1144,13 +1488,20 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
/* Disable Rx and Cb DMA Request */
hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
- hspdif->RxXferCount = 0U;
+ hspdif->RxXferCount = 0;
hspdif->State= HAL_SPDIFRX_STATE_READY;
/* Set the error code and execute error callback*/
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
+
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ /* The transfer is not stopped */
+ hspdif->ErrorCallback(hspdif);
+#else
+ /* The transfer is not stopped */
HAL_SPDIFRX_ErrorCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
/**
@@ -1161,7 +1512,8 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
{
/* Receive data */
- (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;
+ (*hspdif->pRxBuffPtr) = hspdif->Instance->DR;
+ hspdif->pRxBuffPtr++;
hspdif->RxXferCount--;
if(hspdif->RxXferCount == 0U)
@@ -1174,7 +1526,11 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
- HAL_SPDIFRX_RxCpltCallback(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->RxCpltCallback(hspdif);
+#else
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1186,7 +1542,8 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
{
/* Receive data */
- (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;
+ (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR;
+ hspdif->pCsBuffPtr++;
hspdif->CsXferCount--;
if(hspdif->CsXferCount == 0U)
@@ -1199,7 +1556,11 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
- HAL_SPDIFRX_CxCpltCallback(hspdif);
+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
+ hspdif->CxCpltCallback(hspdif);
+#else
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1209,72 +1570,38 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
* @param Flag Flag checked
* @param Status Value of the flag expected
* @param Timeout Duration of the timeout
+ * @param tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
{
- uint32_t tickstart = 0U;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
{
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
+ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State= HAL_SPDIFRX_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspdif);
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
- else
- {
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
- __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspdif);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
return HAL_OK;
}
@@ -1283,6 +1610,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
*/
#endif /* STM32F446xx */
+#endif /* SPDIFRX */
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
/**
* @}
@@ -1293,4 +1621,3 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spi.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spi.c
index 4aef1cd4fd432827b10d258c06eb7a49dfabd1e1..fbe57f4aed0cd65a491a87a3f71cfa736b531441 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spi.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_spi.c
@@ -29,12 +29,12 @@
(+++) Configure the SPIx interrupt priority
(+++) Enable the NVIC SPI IRQ handle
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx stream
- (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -52,100 +52,145 @@
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
[..]
Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
does not initiate a new transfer the following procedure has to be respected:
(##) HAL_SPI_DeInit()
(##) HAL_SPI_Init()
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
@endverbatim
- Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
- the following tables resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
-
- DataSize = SPI_DATASIZE_8BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
- +----------------------------------------------------------------------------------------------+
-
- DataSize = SPI_DATASIZE_16BIT:
- +----------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==============================================================================================|
- | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
- | R |----------------|----------|----------|-----------|----------|-----------|----------|
- | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
- |=========|================|==========|==========|===========|==========|===========|==========|
- | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
- | |----------------|----------|----------|-----------|----------|-----------|----------|
- | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
- | X |----------------|----------|----------|-----------|----------|-----------|----------|
- | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
- +----------------------------------------------------------------------------------------------+
- [..]
- (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- (@)
- (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+ Additional table :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128|
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (8bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -156,6 +201,7 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+
/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
@@ -168,6 +214,7 @@
* @{
*/
#define SPI_DEFAULT_TIMEOUT 100U
+#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */
/**
* @}
*/
@@ -175,7 +222,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
+/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -188,7 +235,8 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
@@ -208,7 +256,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
@@ -261,7 +310,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
@@ -275,14 +324,14 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
- if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
}
#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
@@ -290,13 +339,33 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
#endif /* USE_SPI_CRC */
- if(hspi->State == HAL_SPI_STATE_RESET)
+ if (hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
@@ -309,15 +378,15 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
- /* Configure : NSS management */
+ /* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
#if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
}
@@ -326,7 +395,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* USE_SPI_CRC */
+#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_READY;
@@ -335,7 +404,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
}
/**
- * @brief De Initialize the SPI peripheral.
+ * @brief De-Initialize the SPI peripheral.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
@@ -343,7 +412,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
@@ -356,8 +425,18 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
@@ -378,9 +457,10 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspInit should be implemented in the user file
- */
+ */
}
/**
@@ -393,11 +473,227 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
}
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -446,8 +742,9 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ uint16_t initial_TxXferCount;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -457,14 +754,15 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
+ initial_TxXferCount = Size;
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -485,49 +783,49 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
hspi->RxISR = NULL;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
- hspi->TxXferCount--;
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -538,25 +836,25 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Transmit data in 8 Bit mode */
else
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
- pData += sizeof(uint8_t);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
- pData += sizeof(uint8_t);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -564,36 +862,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
}
}
}
-
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- errorcode = HAL_TIMEOUT;
- goto error;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- goto error;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
-#if (USE_SPI_CRC != 0U)
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -616,17 +905,14 @@ error:
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
/* Process Locked */
@@ -635,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -663,7 +949,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
@@ -672,36 +958,36 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
#endif /* USE_SPI_CRC */
/* Configure communication direction: 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
- /* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ /* Receive data in 8 Bit mode */
+ if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
{
/* Transfer loop */
- while(hspi->RxXferCount > 0U)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
- (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
- pData += sizeof(uint8_t);
+ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -712,19 +998,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
else
{
/* Transfer loop */
- while(hspi->RxXferCount > 0U)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- *((uint16_t*)pData) = hspi->Instance->DR;
- pData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -735,13 +1021,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
#if (USE_SPI_CRC != 0U)
/* Handle the CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* freeze the CRC before the latest data */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Read the latest data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
errorcode = HAL_TIMEOUT;
@@ -749,18 +1035,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
/* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- *((uint16_t*)pData) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
- (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
}
/* Wait the CRC data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
@@ -768,29 +1054,26 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(hspi->Instance->DR);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -811,16 +1094,17 @@ error :
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
{
- uint32_t tmp = 0U, tmp1 = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg1 = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
+ uint16_t initial_TxXferCount;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ uint32_t tickstart;
+
/* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -831,24 +1115,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+ initial_TxXferCount = Size;
- if(!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
@@ -868,42 +1154,42 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
@@ -911,15 +1197,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Check RXNE flag */
- if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -929,25 +1215,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
/* Transmit and Receive data in 8 Bit mode */
else
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
- pTxData += sizeof(uint8_t);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
hspi->TxXferCount--;
}
- while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
- /* check TXE flag */
- if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
@@ -955,14 +1242,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Wait until RXNE flag is reset */
- if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
- (*(uint8_t *)pRxData++) = hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -972,10 +1260,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
#if (USE_SPI_CRC != 0U)
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
@@ -983,13 +1271,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
goto error;
}
/* Read CRC */
- tmpreg1 = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg1);
+ READ_REG(hspi->Instance->DR);
}
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
@@ -999,15 +1285,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
#endif /* USE_SPI_CRC */
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
- {
- errorcode = HAL_TIMEOUT;
- goto error;
- }
-
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
errorcode = HAL_ERROR;
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
@@ -1015,7 +1294,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
@@ -1044,13 +1323,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Process Locked */
__HAL_LOCK(hspi);
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
@@ -1070,7 +1349,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
hspi->RxISR = NULL;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->TxISR = SPI_TxISR_16BIT;
}
@@ -1080,32 +1359,25 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- /* Enable TXE interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
- }
- else
- {
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- }
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1128,23 +1400,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
{
HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
}
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -1164,7 +1436,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
hspi->TxISR = NULL;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->RxISR = SPI_RxISR_16BIT;
}
@@ -1174,14 +1446,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -1195,7 +1467,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
process unlock */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1218,8 +1490,9 @@ error :
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1227,24 +1500,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
- if(!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
@@ -1259,7 +1533,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
hspi->RxXferCount = Size;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->RxISR = SPI_2linesRxISR_16BIT;
hspi->TxISR = SPI_2linesTxISR_16BIT;
@@ -1272,7 +1546,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -1282,7 +1556,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1306,19 +1580,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -1339,14 +1616,14 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
hspi->RxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -1364,18 +1641,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Set the DMA AbortCpltCallback */
hspi->hdmatx->XferAbortCallback = NULL;
- /* Enable the Tx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1388,6 +1673,7 @@ error :
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData pointer to data buffer
@@ -1399,23 +1685,30 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
{
HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
+ /* Check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* Check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -1435,14 +1728,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
hspi->TxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -1457,21 +1750,29 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
- /* Set the DMA AbortCpltCallback */
+ /* Set the DMA AbortCpltCallback */
hspi->hdmarx->XferAbortCallback = NULL;
- /* Enable the Rx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
@@ -1492,44 +1793,52 @@ error:
* @param Size amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
- if(!((tmp == HAL_SPI_STATE_READY) ||
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t*)pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t*)pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
@@ -1539,14 +1848,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
/* Set the SPI Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
@@ -1565,8 +1874,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
/* Set the DMA AbortCpltCallback */
hspi->hdmarx->XferAbortCallback = NULL;
- /* Enable the Rx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
@@ -1578,17 +1895,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->hdmatx->XferErrorCallback = NULL;
hspi->hdmatx->XferAbortCallback = NULL;
- /* Enable the Tx DMA Stream */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Enable the SPI Error Interrupt Bit */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1610,40 +1935,73 @@ error :
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
- * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
- * before starting new SPI receive process.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
- /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hspi->hdmatx != NULL)
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = NULL;
/* Abort DMA Tx Handle linked to SPI Peripheral */
- HAL_DMA_Abort(hspi->hdmatx);
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
@@ -1651,38 +2009,55 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
/* Wait until TXE flag is set */
do
{
- if(count-- == 0U)
+ if (count == 0U)
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
+ count--;
}
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
}
- /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hspi->hdmarx != NULL)
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = NULL;
/* Abort DMA Rx Handle linked to SPI Peripheral */
- HAL_DMA_Abort(hspi->hdmarx);
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
/* Disable peripheral */
__HAL_SPI_DISABLE(hspi);
/* Disable Rx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
-
}
}
/* Reset Tx and Rx transfer counters */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1691,7 +2066,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
/* Restore hspi->state to ready */
hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
+ return errorcode;
}
/**
@@ -1707,38 +2082,68 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
- * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
- * before starting new SPI receive process.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
- uint32_t abortcplt;
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
{
hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- abortcplt = 1U;
-
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hspi->hdmatx != NULL)
+ if (hspi->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
}
@@ -1748,11 +2153,11 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
/* DMA Rx Handle is valid */
- if(hspi->hdmarx != NULL)
+ if (hspi->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
}
@@ -1762,48 +2167,17 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- /* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
- /* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
{
/* Abort DMA Tx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
{
hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
else
{
@@ -1811,16 +2185,17 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
- /* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
{
/* Abort DMA Rx Handle linked to SPI Peripheral */
- if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
{
hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
else
{
@@ -1829,14 +2204,23 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
- if(abortcplt == 1U)
+ if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1846,9 +2230,14 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
hspi->State = HAL_SPI_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
- return HAL_OK;
+
+ return errorcode;
}
/**
@@ -1892,34 +2281,43 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
*/
- /* Abort the SPI DMA tx Stream */
- if(hspi->hdmatx != NULL)
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
{
- HAL_DMA_Abort(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
- /* Abort the SPI DMA rx Stream */
- if(hspi->hdmarx != NULL)
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
{
- HAL_DMA_Abort(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
+ return errorcode;
}
/**
@@ -1934,27 +2332,27 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
- if(((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
/* SPI in mode Transmitter -------------------------------------------------*/
- if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
/* SPI in Error Treatment --------------------------------------------------*/
- if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
- if((itflag & SPI_FLAG_OVR) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
{
- if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -1967,51 +2365,61 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
- if((itflag & SPI_FLAG_MODF) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
/* SPI Frame error interrupt occurred ------------------------------------*/
- if((itflag & SPI_FLAG_FRE) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
/* Disable all interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
hspi->State = HAL_SPI_STATE_READY;
/* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
{
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
/* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
+ if (hspi->hdmarx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
/* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
+ if (hspi->hdmatx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
@@ -2019,7 +2427,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Tx Transfer completed callback.
+ * @brief Tx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2028,13 +2436,14 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Transfer completed callback.
+ * @brief Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2043,13 +2452,14 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
+ */
}
/**
- * @brief Tx and Rx Transfer completed callback.
+ * @brief Tx and Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2058,13 +2468,14 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
+ */
}
/**
- * @brief Tx Half Transfer completed callback.
+ * @brief Tx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2073,13 +2484,14 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Half Transfer completed callback.
+ * @brief Rx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2088,13 +2500,14 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
+ */
}
/**
- * @brief Tx and Rx Half Transfer callback.
+ * @brief Tx and Rx Half Transfer callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2103,27 +2516,29 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
+ */
}
/**
- * @brief SPI error callback.
+ * @brief SPI error callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred
- */
+ */
}
/**
@@ -2198,33 +2613,36 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
*/
/**
- * @brief DMA SPI transmit process complete callback.
+ * @brief DMA SPI transmit process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t tickstart = 0U;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
@@ -2232,48 +2650,57 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
hspi->TxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
- * @brief DMA SPI receive process complete callback.
+ * @brief DMA SPI receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-#if (USE_SPI_CRC != 0U)
- uint32_t tickstart = 0U;
- __IO uint16_t tmpreg = 0U;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
-#endif /* USE_SPI_CRC */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
#if (USE_SPI_CRC != 0U)
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(hspi->Instance->DR);
}
#endif /* USE_SPI_CRC */
@@ -2281,10 +2708,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
hspi->RxXferCount = 0U;
@@ -2292,20 +2718,30 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2316,33 +2752,34 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
#if (USE_SPI_CRC != 0U)
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait the CRC data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(hspi->Instance->DR);
}
#endif /* USE_SPI_CRC */
+
/* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
@@ -2356,20 +2793,30 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2380,9 +2827,14 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2393,9 +2845,14 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxHalfCpltCallback(hspi);
+#else
HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2406,9 +2863,14 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2419,14 +2881,19 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
-/* Stop the disable DMA transfer on SPI side */
+ /* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2437,11 +2904,16 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2454,49 +2926,60 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ __IO uint32_t count;
hspi->hdmatx->XferAbortCallback = NULL;
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Wait until TXE flag is set */
do
{
- if(count-- == 0U)
+ if (count == 0U)
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
+ count--;
}
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check if an Abort process is still ongoing */
- if(hspi->hdmarx != NULL)
+ if (hspi->hdmarx != NULL)
{
- if(hspi->hdmarx->XferAbortCallback != NULL)
+ if (hspi->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
/* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
__HAL_SPI_CLEAR_FREFLAG(hspi);
/* Restore hspi->State to Ready */
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2509,7 +2992,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -2519,21 +3002,31 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
/* Disable Rx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ /* Check Busy flag */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+
/* Check if an Abort process is still ongoing */
- if(hspi->hdmatx != NULL)
+ if (hspi->hdmatx != NULL)
{
- if(hspi->hdmatx->XferAbortCallback != NULL)
+ if (hspi->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
- /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
- /* Reset errorCode */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
/* Clear the Error flags in the SR register */
__HAL_SPI_CLEAR_OVRFLAG(hspi);
@@ -2543,7 +3036,11 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2555,24 +3052,25 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 8bit mode */
- *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
- /* check end of the reception */
- if(hspi->RxXferCount == 0U)
+ /* Check end of the reception */
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
#endif /* USE_SPI_CRC */
- /* Disable RXNE interrupt */
+ /* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2588,19 +3086,13 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
-
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Regsiter */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
- /* Disable RXNE interrupt */
+ /* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2615,16 +3107,19 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
- /* check the end of the transmission */
- if(hspi->TxXferCount == 0U)
+ /* Check the end of the transmission */
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ /* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
@@ -2633,7 +3128,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0U)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2649,14 +3144,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
- if(hspi->RxXferCount == 0U)
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
@@ -2666,7 +3161,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2682,14 +3177,8 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- /* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Regsiter */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -2712,12 +3201,14 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ /* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
@@ -2726,7 +3217,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0U)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2742,13 +3233,8 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
SPI_CloseRx_ISR(hspi);
}
@@ -2762,21 +3248,22 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
- if(hspi->RxXferCount == 0U)
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_8BITCRC;
return;
@@ -2795,13 +3282,8 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Register */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -2818,22 +3300,22 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
- if(hspi->RxXferCount == 0U)
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
@@ -2851,13 +3333,14 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
@@ -2880,10 +3363,10 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0U)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
@@ -2894,22 +3377,23 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
}
/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout, uint32_t Tickstart)
{
- while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
+ if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2918,19 +3402,20 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -2942,25 +3427,99 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
return HAL_OK;
}
+
/**
- * @brief Handle to check BSY flag before start a new transaction.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- /* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
+ {
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ /* Wait the RXNE reset */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Wait the RXNE reset */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
}
return HAL_OK;
}
+/**
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Timeout in µs */
+ __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
+ /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
+ * If Timeout is reached, the transfer is considered as finish.
+ * User have to calculate the timeout value to fit with the time of 1 byte transfer.
+ * This time is directly link with the SPI clock from Master device.
+ */
+ do
+ {
+ if (count == 0U)
+ {
+ break;
+ }
+ count--;
+ } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
+ }
+
+ return HAL_OK;
+}
+
/**
* @brief Handle the end of the RXTX transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
@@ -2969,8 +3528,9 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -2980,55 +3540,76 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
/* Wait until TXE flag is set */
do
{
- if(count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;
}
+ count--;
}
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Check the end of the transaction */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->State = HAL_SPI_STATE_READY;
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
else
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
@@ -3043,44 +3624,58 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- /* Check the end of the transaction */
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
- /* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
- hspi->State = HAL_SPI_STATE_READY;
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
-#endif /* USE_SPI_CRC */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
-#if (USE_SPI_CRC != 0U)
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
+#if (USE_SPI_CRC != 0U)
+ }
#endif /* USE_SPI_CRC */
}
@@ -3092,7 +3687,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout management*/
@@ -3101,65 +3696,72 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
/* Wait until TXE flag is set */
do
{
- if(count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
break;
}
+ count--;
}
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- /* Check Busy flag */
- if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
/**
- * @}
- */
-
-/**
- * @brief Handle abort a Tx or Rx transaction.
+ * @brief Handle abort a Rx transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
{
- __IO uint32_t tmpreg = 0U;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Wait until TXE flag is set */
do
{
- if(count-- == 0U)
+ if (count == 0U)
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
+ count--;
}
- while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3167,30 +3769,33 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
- /* Flush DR Register */
- tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
+ /* Read CRC to flush Data Register */
+ READ_REG(hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ hspi->State = HAL_SPI_STATE_ABORT;
}
/**
- * @brief Handle abort a Tx or Rx transaction.
+ * @brief Handle abort a Tx or Rx/Tx transaction.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
{
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+ /* Disable TXEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
+
+ hspi->State = HAL_SPI_STATE_ABORT;
}
+
/**
* @}
*/
+
#endif /* HAL_SPI_MODULE_ENABLED */
/**
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sram.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sram.c
index 8af2ec101649f33dd55cf2b2dcd5fab21e469d47..2f38bfe6f38e1535d59092aa21ef2ae2f9899c3a 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sram.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_sram.c
@@ -58,33 +58,56 @@
(#) You can continuously monitor the SRAM device HAL state by calling the function
HAL_SRAM_GetState()
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) MspInitCallback : SRAM MspInit.
+ (+) MspDeInitCallback : SRAM MspDeInit.
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
+ and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
+ or @ref HAL_SRAM_Init function.
+
+ When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -151,8 +174,21 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if(hsram->MspInitCallback == NULL)
+ {
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ }
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Init the low level hardware */
+ hsram->MspInitCallback(hsram);
+#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
+#endif
}
/* Initialize SRAM control Interface */
@@ -178,8 +214,18 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
*/
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+ if(hsram->MspDeInitCallback == NULL)
+ {
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ }
+
+ /* DeInit the low level hardware */
+ hsram->MspDeInitCallback(hsram);
+#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
+#endif
/* Configure the SRAM registers with their reset values */
FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
@@ -572,6 +618,181 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
return HAL_OK;
}
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SRAM Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Unregister a User SRAM Callback
+ * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
+ * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(state == HAL_SRAM_STATE_RESET)
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+
+/**
+ * @brief Register a User SRAM Callback for DMA transfers
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hsram : SRAM handle
+ * @param CallbackId : ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
+ * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
+ * @param pCallback : pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_SRAM_StateTypeDef state;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsram);
+
+ state = hsram->State;
+ if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ {
+ switch (CallbackId)
+ {
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+ return status;
+}
+#endif
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim.c
index c42977185cde146f55950c0689c3fd2ce5c9d525..af264f058818ed5164e5b25e593e6dca78ba9c94 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim.c
@@ -5,30 +5,30 @@
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
* + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
@verbatim
==============================================================================
##### TIMER Generic features #####
@@ -42,12 +42,15 @@
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
+ depending on the selected feature:
(++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
@@ -56,10 +59,10 @@
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -68,17 +71,17 @@
any start function.
(#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
- Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
- PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
- external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
- (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
@@ -92,33 +95,81 @@
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -141,41 +192,38 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
/** @addtogroup TIM_Private_Functions
* @{
*/
-/* Private function prototypes -----------------------------------------------*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
*
@verbatim
@@ -198,15 +246,18 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/
/**
* @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -215,31 +266,44 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -252,8 +316,17 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -266,53 +339,59 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Base MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
}
+
/**
* @brief Starts the TIM Base generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -320,8 +399,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -330,13 +408,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -344,20 +422,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -365,8 +448,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -385,24 +467,25 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0U) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -411,20 +494,33 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Set the DMA Period elapsed callback */
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -432,8 +528,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -444,6 +539,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -453,42 +550,46 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
*
@verbatim
==============================================================================
- ##### Time Output Compare functions #####
+ ##### TIM Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
- (+) Start the Time Output Compare.
- (+) Stop the Time Output Compare.
- (+) Start the Time Output Compare and enable interrupt.
- (+) Stop the Time Output Compare and disable interrupt.
- (+) Start the Time Output Compare and enable DMA transfer.
- (+) Stop the Time Output Compare and disable DMA transfer.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -497,31 +598,44 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -529,13 +643,22 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -548,39 +671,38 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -590,20 +712,26 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -611,9 +739,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -629,7 +756,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -644,9 +771,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -656,6 +782,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -665,45 +793,49 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -711,9 +843,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -732,38 +863,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -778,9 +909,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -792,16 +922,18 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -810,87 +942,110 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -898,9 +1053,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -919,38 +1073,42 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -965,42 +1123,46 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
*
@verbatim
==============================================================================
- ##### Time PWM functions #####
+ ##### TIM PWM functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
+ (+) Initialize and configure the TIM PWM.
(+) De-initialize the TIM PWM.
- (+) Start the Time PWM.
- (+) Stop the Time PWM.
- (+) Start the Time PWM and enable interrupt.
- (+) Stop the Time PWM and disable interrupt.
- (+) Start the Time PWM and enable DMA transfer.
- (+) Stop the Time PWM and disable DMA transfer.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1009,31 +1171,44 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1046,8 +1221,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1060,39 +1244,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the PWM signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1102,20 +1285,26 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1123,9 +1312,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the PWM signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1141,7 +1329,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1159,9 +1347,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1171,6 +1358,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1180,45 +1368,49 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1226,9 +1418,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1236,7 +1427,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1247,38 +1438,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1293,9 +1484,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1307,16 +1497,18 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1325,87 +1517,109 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1413,9 +1627,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1434,38 +1647,42 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -1480,42 +1697,46 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
*
@verbatim
==============================================================================
- ##### Time Input Capture functions #####
+ ##### TIM Input Capture functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
- (+) Start the Time Input Capture.
- (+) Stop the Time Input Capture.
- (+) Start the Time Input Capture and enable interrupt.
- (+) Stop the Time Input Capture and disable interrupt.
- (+) Start the Time Input Capture and enable DMA transfer.
- (+) Stop the Time Input Capture and disable DMA transfer.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1524,31 +1745,44 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1561,8 +1795,17 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1574,40 +1817,39 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
}
/**
- * @brief Initializes the TIM INput Capture MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Input Capture measurement.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1615,16 +1857,22 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1632,9 +1880,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1659,9 +1906,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1669,8 +1915,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1680,38 +1928,42 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1719,9 +1971,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1740,32 +1991,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -1779,10 +2030,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
}
/**
- * @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1794,17 +2044,19 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0U) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1813,92 +2065,111 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1918,32 +2189,36 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -1962,32 +2237,35 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
*
@verbatim
==============================================================================
- ##### Time One Pulse functions #####
+ ##### TIM One Pulse functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
- (+) Start the Time One Pulse.
- (+) Stop the Time One Pulse.
- (+) Start the Time One Pulse and enable interrupt.
- (+) Stop the Time One Pulse and disable interrupt.
- (+) Start the Time One Pulse and enable DMA transfer.
- (+) Stop the Time One Pulse and disable DMA transfer.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
@@ -1997,7 +2275,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -2007,17 +2285,31 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL)
+ {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2029,15 +2321,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
htim->Instance->CR1 |= OnePulseMode;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -2050,8 +2341,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2064,39 +2364,38 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2119,7 +2418,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2131,9 +2430,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be disable.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2153,7 +2451,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@@ -2168,9 +2466,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2178,6 +2475,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2187,9 +2487,6 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
- /* Prevent unused argument(s) compilation warning */
- UNUSED(OutputChannel);
-
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -2199,7 +2496,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2211,9 +2508,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channels to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2238,63 +2534,73 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
*
@verbatim
==============================================================================
- ##### Time Encoder functions #####
+ ##### TIM Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
- (+) Start the Time Encoder.
- (+) Stop the Time Encoder.
- (+) Start the Time Encoder and enable interrupt.
- (+) Stop the Time Encoder and disable interrupt.
- (+) Start the Time Encoder and enable DMA transfer.
- (+) Stop the Time Encoder and disable DMA transfer.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
@endverbatim
* @{
*/
/**
- * @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
@@ -2306,19 +2612,32 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2360,15 +2679,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
htim->Instance->CCER = tmpccer;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
+
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2381,8 +2700,17 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2395,39 +2723,38 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2447,16 +2774,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
}
/* Enable the Peripheral */
@@ -2468,9 +2797,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2480,9 +2808,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1 and 2
+ /* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
@@ -2491,18 +2819,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
}
}
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -2512,9 +2843,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2536,19 +2866,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
break;
}
+
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
}
+
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
}
@@ -2561,9 +2893,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be disabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2577,19 +2908,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
else
{
@@ -2613,9 +2944,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2630,13 +2960,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -2645,20 +2975,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
@@ -2667,19 +3004,22 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
@@ -2688,30 +3028,37 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_ALL:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the Peripheral */
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
@@ -2722,11 +3069,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Return function status */
return HAL_OK;
@@ -2734,9 +3081,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2750,19 +3096,21 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
else
{
@@ -2772,6 +3120,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
/* Disable the Peripheral */
@@ -2783,12 +3133,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
+ * @brief TIM IRQ handler management
*
@verbatim
==============================================================================
@@ -2802,142 +3152,194 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
/* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
}
/* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- HAL_TIMEx_CommutationCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
*
@verbatim
==============================================================================
@@ -2945,11 +3347,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
==============================================================================
[..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the DMA Burst Mode.
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
@endverbatim
* @{
@@ -2958,10 +3360,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Output Compare handle
* @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channels to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2969,14 +3370,16 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- /* Check input state */
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -2985,39 +3388,48 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
default:
- break;
+ break;
}
+
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -3028,10 +3440,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM IC handle
* @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3039,7 +3450,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -3048,6 +3459,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3056,9 +3468,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
{
/* TI1 Configuration */
TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -3088,9 +3500,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC3PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
@@ -3104,9 +3516,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC4PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
@@ -3125,10 +3537,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM PWM handle
* @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be enabled.
+ * @param Channel TIM Channels to be configured
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3136,23 +3547,28 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
- __HAL_LOCK(htim);
-
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
htim->State = HAL_TIM_STATE_BUSY;
switch (Channel)
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
@@ -3162,12 +3578,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
@@ -3177,41 +3595,45 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
case TIM_CHANNEL_3:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3224,20 +3646,19 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM One Pulse handle
* @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM Channels to be enabled.
+ * @param OutputChannel TIM output channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM Channels to be enabled.
+ * @param InputChannel TIM input Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@@ -3245,8 +3666,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
- if(OutputChannel != InputChannel)
+ if (OutputChannel != InputChannel)
{
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3266,18 +3688,19 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
}
- break;
default:
- break;
+ break;
}
+
switch (InputChannel)
{
case TIM_CHANNEL_1:
@@ -3285,7 +3708,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ sConfig->ICSelection, sConfig->ICFilter);
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -3297,14 +3720,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
}
- break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ sConfig->ICSelection, sConfig->ICFilter);
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
@@ -3316,11 +3739,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3337,10 +3760,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
- * This parameters can be on of the following values:
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
@@ -3359,9 +3781,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources.
- * This parameters can be on of the following values:
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3371,11 +3792,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
- * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength)
+ uint32_t *BurstBuffer, uint32_t BurstLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -3383,13 +3805,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0U) && (BurstLength > 0U))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3398,102 +3820,134 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -3501,71 +3955,73 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ /* Abort the DMA transfer (at least disable the DMA stream) */
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
- * This parameters can be on of the following values:
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
@@ -3584,9 +4040,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources.
- * This parameters can be on of the following values:
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3596,7 +4051,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
- * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3608,13 +4064,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0U) && (BurstLength > 0U))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3623,98 +4079,130 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture/compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@@ -3727,69 +4215,71 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Stop the DMA burst reading
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
- /* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ /* Abort the DMA transfer (at least disable the DMA stream) */
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
* @brief Generate a software event
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param EventSource specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
@@ -3800,8 +4290,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
* @arg TIM_EVENTSOURCE_COM: Timer COM event source
* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
+ * supporting a break input.
* @retval HAL status
*/
@@ -3831,104 +4323,125 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
/**
* @brief Configures the OCRef clear feature
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel.
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
/* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
- if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+ switch (sClearInputConfig->ClearInputSource)
{
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ break;
+ }
+
+ default:
+ break;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
}
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
}
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
}
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
}
else
{
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
}
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3940,15 +4453,14 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp
/**
* @brief Configures the clock source to be used
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
@@ -3969,18 +4481,17 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_INTERNAL:
{
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ break;
}
- break;
case TIM_CLOCKSOURCE_ETRMODE1:
{
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ /* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
@@ -3988,23 +4499,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+
/* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
+ break;
}
- break;
case TIM_CLOCKSOURCE_ETRMODE2:
{
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ /* Check ETR input conditioning related parameters */
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
@@ -4014,78 +4525,71 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
}
- break;
case TIM_CLOCKSOURCE_TI1:
{
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_TI2:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
- /* Check TI1 input conditioning related parameters */
+ /* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_TI1ED:
{
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
- sClockSourceConfig->ClockFilter);
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
}
- break;
+
case TIM_CLOCKSOURCE_ITR0:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
- }
- break;
case TIM_CLOCKSOURCE_ITR1:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
case TIM_CLOCKSOURCE_ITR2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
case TIM_CLOCKSOURCE_ITR3:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -4097,11 +4601,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param TI1_Selection Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
* pins are connected to the TI1 input (XOR combination)
@@ -4109,7 +4612,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
@@ -4132,15 +4635,14 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
/**
* @brief Configures the TIM in Slave mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4151,7 +4653,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
htim->State = HAL_TIM_STATE_BUSY;
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
@@ -4171,12 +4678,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
* @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4187,7 +4694,12 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY;
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+ if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
@@ -4204,9 +4716,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channels to be enabled.
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4218,8 +4729,6 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0U;
- __HAL_LOCK(htim);
-
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -4228,7 +4737,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Return the capture 1 value */
- tmpreg = htim->Instance->CCR1;
+ tmpreg = htim->Instance->CCR1;
break;
}
@@ -4238,7 +4747,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Return the capture 2 value */
- tmpreg = htim->Instance->CCR2;
+ tmpreg = htim->Instance->CCR2;
break;
}
@@ -4249,7 +4758,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Return the capture 3 value */
- tmpreg = htim->Instance->CCR3;
+ tmpreg = htim->Instance->CCR3;
break;
}
@@ -4260,18 +4769,18 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Return the capture 4 value */
- tmpreg = htim->Instance->CCR4;
+ tmpreg = htim->Instance->CCR4;
break;
}
default:
- break;
+ break;
}
- __HAL_UNLOCK(htim);
return tmpreg;
}
+
/**
* @}
*/
@@ -4285,515 +4794,1052 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
==============================================================================
[..]
This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
@endverbatim
* @{
*/
/**
- * @brief Period elapsed callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
/**
- * @brief Output Compare callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Input Capture callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
* @retval None
*/
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
/**
- * @brief PWM Pulse finished callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
* @retval None
*/
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Trigger detection callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
* @retval None
*/
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_TriggerCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Timer error callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIM_ErrorCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
/**
- * @brief Return the TIM Base state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
*/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
{
- return htim->State;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
}
/**
- * @brief Return the TIM OC state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
*/
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
- return htim->State;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
}
/**
- * @brief Return the TIM PWM state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
*/
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
{
- return htim->State;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
}
/**
- * @brief Return the TIM Input Capture state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
*/
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
-}
-
-/**
- * @brief Return the TIM One Pulse Mode state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
{
- return htim->State;
-}
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
-/**
- * @brief Return the TIM Encoder Mode state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @retval HAL state
- */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
- return htim->State;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
}
-/**
- * @}
- */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
- * @brief Time Base configuration
- * @param TIMx TIM peripheral
- * @param Structure pointer on TIM Time Base required parameters
- * @retval None
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
{
- uint32_t tmpcr1 = 0U;
- tmpcr1 = TIMx->CR1;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Set TIM Time Base Unit parameters ---------------------------------------*/
- if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
+ if (pCallback == NULL)
{
- /* Select the Counter Mode */
- tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- tmpcr1 |= Structure->CounterMode;
+ return HAL_ERROR;
}
+ /* Process locked */
+ __HAL_LOCK(htim);
- if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ if (htim->State == HAL_TIM_STATE_READY)
{
- /* Set the clock division */
- tmpcr1 &= ~TIM_CR1_CKD;
- tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
}
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
- TIMx->CR1 = tmpcr1;
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
- /* Set the Auto-reload value */
- TIMx->ARR = (uint32_t)Structure->Period ;
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
- /* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
{
- /* Set the Repetition Counter value */
- TIMx->RCR = Structure->RepetitionCounter;
+ /* Return error status */
+ status = HAL_ERROR;
}
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediately */
- TIMx->EGR = TIM_EGR_UG;
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
}
/**
- * @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
- * protected against un-initialized filter and polarity values.
- * @retval None
- */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
+ /* Process locked */
+ __HAL_LOCK(htim);
- /* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ if (htim->State == HAL_TIM_STATE_READY)
{
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_ICSelection;
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
}
else
{
- tmpccmr1 &= ~TIM_CCMR1_CC1S;
- tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ /* Return error status */
+ status = HAL_ERROR;
}
- /* Set the filter */
- tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
+ return status;
}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
- * @brief Time Output Compare 2 configuration
- * @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
- * @retval None
+ * @}
*/
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= ~TIM_CCER_CC2E;
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+@endverbatim
+ * @{
+ */
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
+/**
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= ~TIM_CCMR1_OC2M;
- tmpccmrx &= ~TIM_CCMR1_CC2S;
+/**
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- /* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8U);
+/**
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- /* Reset the Output Polarity level */
- tmpccer &= ~TIM_CCER_CC2P;
- /* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4U);
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
- {
- assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+/**
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- /* Reset the Output N Polarity level */
- tmpccer &= ~TIM_CCER_CC2NP;
- /* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4U);
- /* Reset the Output N State */
- tmpccer &= ~TIM_CCER_CC2NE;
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
- /* Reset the Output Compare and Output Compare N IDLE State */
- tmpcr2 &= ~TIM_CR2_OIS2;
- tmpcr2 &= ~TIM_CR2_OIS2N;
- /* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2U);
- /* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
+/**
+ * @}
+ */
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
+/**
+ * @}
+ */
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = OC_Config->Pulse;
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief TIM DMA Delay Pulse complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
- if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
- * @brief TIM DMA error callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
- HAL_TIM_ErrorCallback(htim);
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Capture complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
- if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
}
- else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_TIM_CHANNELS(Channel));
-
- tmp = TIM_CCER_CC1E << Channel;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- /* Reset the CCxE Bit */
- TIMx->CCER &= ~tmp;
+ htim->State = HAL_TIM_STATE_READY;
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
- * @brief TIM DMA Period Elapse complete callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
- HAL_TIM_PeriodElapsedCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
- * @brief TIM DMA Trigger callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
* @retval None
*/
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
- htim->State= HAL_TIM_STATE_READY;
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
- HAL_TIM_TriggerCallback(htim);
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
}
/**
- * @brief Time Output Compare 1 configuration
+ * @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -4801,7 +5847,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
@@ -4817,15 +5863,24 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
-
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
{
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
@@ -4835,6 +5890,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4849,16 +5905,92 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 3 configuration
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -4866,7 +5998,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
@@ -4882,11 +6014,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
@@ -4894,6 +6024,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
tmpccer |= (OC_Config->OCNPolarity << 8U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
@@ -4903,6 +6040,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4917,16 +6055,16 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 4 configuration
+ * @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The output configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -4934,7 +6072,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
+ tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
@@ -4951,15 +6089,18 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
- /*if((TIMx == TIM1) || (TIMx == TIM8))*/
- if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
+ /* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
+
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4974,20 +6115,19 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
}
/**
- * @brief Time Output Compare 4 configuration
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sSlaveConfig The slave configuration structure
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
* @retval None
*/
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
- /* Get the TIMx SMCR register value */
+ /* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* Reset the Trigger Selection Bits */
@@ -5006,10 +6146,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
{
- case TIM_TS_ETRF:
+ case TIM_TS_ETRF:
{
/* Check the parameters */
- assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
@@ -5018,15 +6158,20 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
sSlaveConfig->TriggerPrescaler,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI1F_ED:
+ case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim->Instance->CCER;
htim->Instance->CCER &= ~TIM_CCER_CC1E;
@@ -5039,11 +6184,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
htim->Instance->CCER = tmpccer;
-
+ break;
}
- break;
- case TIM_TS_TI1FP1:
+ case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -5054,10 +6198,10 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_TI1_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI2FP2:
+ case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -5066,61 +6210,98 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_ITR0:
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
}
- break;
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
+ default:
+ break;
+ }
+ return HAL_OK;
+}
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
- default:
- break;
+ /* Select the Input */
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
}
-}
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
@@ -5143,28 +6324,28 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/**
* @brief Configure the TI2 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
- * @retval None
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5191,19 +6372,19 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the Polarity and Filter for TI2.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5226,28 +6407,28 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/**
* @brief Configure the TI3 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
- * protected against un-initialized filter and polarity values.
* @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5274,28 +6455,28 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the TI4 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5322,7 +6503,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param TIM_ITRx The Input Trigger source.
+ * @param InputTriggerSource The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -5334,41 +6515,40 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
- uint32_t tmpsmcr = 0U;
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
+ uint32_t tmpsmcr;
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
* This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
* @param TIM_ExtTRGPolarity The external Trigger Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
* @param ExtTRGFilter External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
@@ -5376,12 +6556,68 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
}
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim_ex.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim_ex.c
index 0fd72d7de30de23aa5586fc3662ae492fb284fbf..b116f95ab9711a912aaf3d0947e77388201e5944 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim_ex.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_tim_ex.c
@@ -4,19 +4,19 @@
* @author MCD Application Team
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Timer extension peripheral:
+ * functionalities of the Timer Extended peripheral:
* + Time Hall Sensor Interface Initialization
* + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
+ * + Time Complementary signal break and dead time configuration
* + Time Master and Slave synchronization configuration
+ * + Timer remapping capabilities configuration
@verbatim
==============================================================================
##### TIMER Extended features #####
==============================================================================
[..]
- The Timer Extension features include:
+ The Timer Extended features include:
(#) Complementary outputs with programmable dead-time for :
- (++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
@@ -26,21 +26,18 @@
(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
positioning purposes
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -48,51 +45,34 @@
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
- (#) Configure the TIM in the desired functioning mode using one of the
- initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
- (#) Activate the TIM peripheral using one of the start functions:
+ (#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -101,8 +81,8 @@
* @{
*/
-/** @defgroup TIMEx TIMEx
- * @brief TIM HAL module driver
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
* @{
*/
@@ -112,23 +92,17 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions
- * @{
- */
/* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/**
- * @}
- */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
@verbatim
==============================================================================
##### Timer Hall Sensor functions #####
@@ -148,34 +122,53 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
* @{
*/
/**
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
{
TIM_OC_InitTypeDef OC_Config;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- /* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -216,15 +209,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -237,8 +229,17 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -251,51 +252,56 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -303,17 +309,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
@@ -325,24 +330,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -350,17 +360,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts event */
@@ -375,24 +384,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @param pData The destination Buffer address.
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -401,23 +411,34 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ else
+ {
+ /* nothing to do */
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Set the DMA Input Capture 1 Callback */
+ /* Set the DMA Input Capture 1 Callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
+ /* Enable the DMA stream for Capture 1*/
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -425,36 +446,37 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 event */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
@verbatim
==============================================================================
##### Timer Complementary Output Compare functions #####
@@ -475,9 +497,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -486,17 +507,23 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -505,9 +532,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -519,11 +545,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Disable the Capture compare channel N */
+ /* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -535,9 +561,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -546,6 +571,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -555,32 +582,26 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
@@ -592,8 +613,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -602,9 +627,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -613,6 +637,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -622,39 +647,33 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
- if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -672,9 +691,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -685,16 +703,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -703,74 +723,72 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
+ {
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel N */
@@ -779,8 +797,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -789,9 +811,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -809,32 +830,28 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel N */
@@ -852,13 +869,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
@verbatim
==============================================================================
##### Timer Complementary PWM functions #####
@@ -888,9 +906,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -899,6 +916,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -908,8 +927,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -917,9 +940,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -947,9 +969,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -958,6 +979,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -967,32 +990,25 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
@@ -1004,8 +1020,12 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1014,17 +1034,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpccer;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1034,39 +1055,33 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
- if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1084,9 +1099,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be enabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1097,16 +1111,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if(htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if(htim->State == HAL_TIM_STATE_READY)
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U) && (Length > 0))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1115,84 +1131,85 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ /* Enable the DMA stream */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
/* Enable the Main Output */
- __HAL_TIM_MOE_ENABLE(htim);
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1201,9 +1218,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Channel TIM Channel to be disabled.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1221,39 +1237,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1269,9 +1281,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
@verbatim
==============================================================================
##### Timer Complementary One Pulse functions #####
@@ -1290,16 +1302,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
+{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@@ -1316,9 +1327,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be disabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1331,10 +1341,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
/* Disable the Main Output */
- __HAL_TIM_MOE_DISABLE(htim);
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1346,9 +1356,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be enabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1373,14 +1382,13 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Return function status */
return HAL_OK;
- }
+}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param OutputChannel TIM Channel to be disabled.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1404,34 +1412,36 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
}
+
/**
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
- (+) Configure External Clock source.
- (+) Configure Complementary channels, break features and dead time.
- (+) Configure Master and the Slave synchronization.
- (+) Configure the commutation event in case of use of the Hall sensor interface.
- (+) Configure the DMA Burst Mode.
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
@endverbatim
* @{
*/
+
/**
* @brief Configure the TIM commutation event sequence.
* @note This function is mandatory to use the commutation event in order to
@@ -1440,25 +1450,24 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1477,6 +1486,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -1490,25 +1505,24 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1527,7 +1541,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
- /* Enable the Commutation Interrupt Request */
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
__HAL_UNLOCK(htim);
@@ -1543,26 +1560,25 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource the Commutation Event source.
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
{
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
__HAL_LOCK(htim);
@@ -1584,9 +1600,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@@ -1597,34 +1617,52 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM in master mode.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @param htim TIM handle.
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+ /* Check input state */
__HAL_LOCK(htim);
+ /* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
/* Reset the MMS Bits */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ tmpcr2 &= ~TIM_CR2_MMS;
/* Select the TRGO source */
- htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Reset the MSM Bit */
- htim->Instance->SMCR &= ~TIM_SMCR_MSM;
- /* Set or Reset the MSM Bit */
- htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -1633,17 +1671,17 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
}
/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
/* Check the parameters */
@@ -1660,7 +1698,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
__HAL_LOCK(htim);
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
@@ -1670,7 +1708,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
@@ -1681,28 +1719,39 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
}
/**
- * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
- * @param Remap specifies the TIM input remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
- * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
- * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
- * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
- * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
- * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
- * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
- * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
- * (HSE divided by a programmable prescaler)
- * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 input is connected to TIM3 Trigger output(default)
- * @arg TIM_TIM9_LPTIM: TIM9 ITR1 input is connected to LPTIM.
- * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 input is connected to TIM3 Trigger output(default)
- * @arg TIM_TIM5_LPTIM: TIM5 ITR1 input is connected to LPTIM.
- * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 input is connected to TIM3 Trigger output(default)
- * @arg TIM_TIM1_LPTIM: TIM1 ITR2 input is connected to LPTIM.
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ * For TIM1, the parameter can have the following values: (**)
+ * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 is connected to TIM3 TRGO
+ * @arg TIM_TIM1_LPTIM: TIM1 ITR2 is connected to LPTIM1 output
+ *
+ * For TIM2, the parameter can have the following values: (**)
+ * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 is connected to TIM8 TRGO (*)
+ * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 is connected to PTP trigger output (*)
+ * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 is connected to OTG FS SOF
+ * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 is connected to OTG FS SOF
+ *
+ * For TIM5, the parameter can have the following values:
+ * @arg TIM_TIM5_GPIO: TIM5 TI4 is connected to GPIO
+ * @arg TIM_TIM5_LSI: TIM5 TI4 is connected to LSI
+ * @arg TIM_TIM5_LSE: TIM5 TI4 is connected to LSE
+ * @arg TIM_TIM5_RTC: TIM5 TI4 is connected to the RTC wakeup interrupt
+ * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 is connected to TIM3 TRGO (*)
+ * @arg TIM_TIM5_LPTIM: TIM5 ITR1 is connected to LPTIM1 output (*)
+ *
+ * For TIM9, the parameter can have the following values: (**)
+ * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO
+ * @arg TIM_TIM9_LPTIM: TIM9 ITR1 is connected to LPTIM1 output
+ *
+ * For TIM11, the parameter can have the following values:
+ * @arg TIM_TIM11_GPIO: TIM11 TI1 is connected to GPIO
+ * @arg TIM_TIM11_HSE: TIM11 TI1 is connected to HSE_RTC clock
+ * @arg TIM_TIM11_SPDIFRX: TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@@ -1710,27 +1759,26 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
__HAL_LOCK(htim);
/* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap));
+ assert_param(IS_TIM_REMAP(htim->Instance, Remap));
-#if defined(LPTIM_OR_TIM1_ITR2_RMP)
- if ((Remap == TIM_TIM9_TIM3_TRGO)|| (Remap == TIM_TIM9_LPTIM)||(Remap ==TIM_TIM5_TIM3_TRGO)||\
- (Remap == TIM_TIM5_LPTIM)||(Remap == TIM_TIM1_TIM3_TRGO)|| (Remap == TIM_TIM1_LPTIM))
+#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
+ if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK)
{
+ /* Connect TIMx internal trigger to LPTIM1 output */
__HAL_RCC_LPTIM1_CLK_ENABLE();
-
- LPTIM1->OR = (Remap& 0xEFFFFFFFU);
+ MODIFY_REG(LPTIM1->OR,
+ (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),
+ Remap & ~(LPTIM_REMAP_MASK));
}
else
{
/* Set the Timer remapping configuration */
- htim->Instance->OR = Remap;
+ WRITE_REG(htim->Instance->OR, Remap);
}
#else
/* Set the Timer remapping configuration */
- htim->Instance->OR = Remap;
-#endif
- htim->State = HAL_TIM_STATE_READY;
+ WRITE_REG(htim->Instance->OR, Remap);
+#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
__HAL_UNLOCK(htim);
@@ -1741,15 +1789,15 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
- * @brief Extension Callbacks functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
@verbatim
==============================================================================
- ##### Extension Callbacks functions #####
+ ##### Extended Callbacks functions #####
==============================================================================
[..]
- This section provides Extension TIM callback functions:
+ This section provides Extended TIM callback functions:
(+) Timer Commutation callback
(+) Timer Break callback
@@ -1758,31 +1806,45 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
*/
/**
- * @brief Hall commutation changed callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Break detection callback in non blocking mode
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
@@ -1790,12 +1852,12 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
- * @brief Extension Peripheral State functions
- *
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
@verbatim
==============================================================================
- ##### Extension Peripheral State functions #####
+ ##### Extended Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
@@ -1806,9 +1868,8 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
*/
/**
- * @brief Return the TIM Hall Sensor interface state
- * @param htim pointer to a TIM_HandleTypeDef structure that contains
- * the configuration information for TIM module.
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -1820,53 +1881,78 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* @}
*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
+ * @{
+ */
+
/**
* @brief TIM DMA Commutation callback.
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
- HAL_TIMEx_CommutationCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+
/**
- * @}
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
*/
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
* @param ChannelNState specifies the TIM Channel CCxNE bit new state.
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
{
- uint32_t tmp = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
+ uint32_t tmp;
- tmp = TIM_CCER_CC1NE << Channel;
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxNE Bit */
- TIMx->CCER &= ~tmp;
+ TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
-
/**
* @}
*/
@@ -1879,4 +1965,5 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
/**
* @}
*/
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_alarm_template.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_alarm_template.c
index 1c7c46aea0f048a71b153f2e9be7acb78f1c960c..20e5de9028fd0b8af64da4b45513ea5d11d9b426 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_alarm_template.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_alarm_template.c
@@ -32,29 +32,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_wakeup_template.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_wakeup_template.c
index 554443c74d9d1c5e004a0f55495707989e46790c..4ce22501faf99c83e22f50c0dd1b0787b125b9b2 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_wakeup_template.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_rtc_wakeup_template.c
@@ -33,29 +33,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_tim_template.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_tim_template.c
index fb0ad5203d1704ca413a55d3937f3c8c3e325d42..2ffdb254fd94909da80705a4754834c951df8484 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_tim_template.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_timebase_tim_template.c
@@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -116,6 +100,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
TimHandle.Init.Prescaler = uwPrescalerValue;
TimHandle.Init.ClockDivision = 0U;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_uart.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_uart.c
index a829a3681586f7c4f8a5277024b9407eafa18896..d7e2cf56f3e39482d8307a4f9b644000e7d40fe6 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_uart.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_uart.c
@@ -4,12 +4,11 @@
* @author MCD Application Team
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
- *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -17,13 +16,12 @@
[..]
The UART HAL driver can be used as follows:
- (#) Declare a UART_HandleTypeDef handle structure.
-
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
(#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
(##) Enable the USARTx interface clock.
(##) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
- (+++) Configure these UART pins as alternate function pull-up.
+ (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input).
(##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
and HAL_UART_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -34,13 +32,15 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required
Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx stream.
(+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Tx/Rx Stream.
+ interrupt on the DMA Tx/Rx stream.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the Init structure.
+ flow control and Mode(Receiver/Transmitter) in the huart Init structure.
(#) For the UART asynchronous mode, initialize the UART registers by calling
the HAL_UART_Init() API.
@@ -64,6 +64,70 @@
low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
HAL_UART_MspInit() API.
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+ or @ref HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
[..]
Three operation modes are available within this driver :
@@ -121,32 +185,32 @@
(@) You can refer to the UART HAL driver header file for more useful macros
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible UART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | UART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -175,9 +239,13 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
+/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -194,7 +262,8 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static void UART_SetConfig (UART_HandleTypeDef *huart);
+static void UART_SetConfig(UART_HandleTypeDef *huart);
+
/**
* @}
*/
@@ -208,7 +277,7 @@ static void UART_SetConfig (UART_HandleTypeDef *huart);
* @brief Initialization and Configuration functions
*
@verbatim
-===============================================================================
+ ===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
@@ -227,8 +296,12 @@ static void UART_SetConfig (UART_HandleTypeDef *huart);
(++) Over Sampling Method
[..]
The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
- follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
- configuration procedures (details for the procedures are available in reference manual (RM0329)).
+ follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
+ procedures (details for the procedures are available in reference manual
+ (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
+ RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
+ RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
+ RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
@endverbatim
* @{
@@ -237,20 +310,20 @@ static void UART_SetConfig (UART_HandleTypeDef *huart);
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
/* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
@@ -263,12 +336,25 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
/* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -290,8 +376,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -299,29 +385,42 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
/**
* @brief Initializes the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
/* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -346,8 +445,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/* Initialize the UART state*/
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -355,7 +454,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/**
* @brief Initializes the LIN mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param BreakDetectLength Specifies the LIN break detection length.
* This parameter can be one of the following values:
@@ -366,23 +465,38 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_UART_INSTANCE(huart->Instance));
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ /* Check the Break detection length parameter */
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
/* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -394,9 +508,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
UART_SetConfig(huart);
/* In LIN mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ - CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
@@ -411,8 +525,8 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/* Initialize the UART state*/
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -420,11 +534,11 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/**
* @brief Initializes the Multi-Processor mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param Address USART address
* @param WakeUpMethod specifies the USART wake-up method.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
* @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
* @retval HAL status
@@ -432,24 +546,39 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Check the Address & wake up method parameters */
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
assert_param(IS_UART_ADDRESS(Address));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
/* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -466,9 +595,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- /* Clear the USART address */
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
/* Set the USART address node */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
SET_BIT(huart->Instance->CR2, Address);
/* Set the wake up method by setting the WAKE bit in the CR1 register */
@@ -480,22 +608,22 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the UART peripheral.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -505,14 +633,26 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_BUSY;
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
- /* Process Lock */
+ /* Process Unlock */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -520,34 +660,272 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief UART MSP Init.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
- /* Prevent unused argument(s) compilation warning */
+ /* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_MspInit could be implemented in the user file
*/
}
/**
* @brief UART MSP DeInit.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -556,49 +934,74 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
* @brief UART Transmit and Receive functions
*
@verbatim
- ==============================================================================
+ ===============================================================================
##### IO operation functions #####
- ==============================================================================
- [..]
+ ===============================================================================
This subsection provides a set of functions allowing to manage the UART asynchronous
and Half duplex data transfers.
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non blocking mode: The communication is performed using Interrupts
- or DMA, these APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or receive process.
- The HAL_UART_ErrorCallback() user callback will be executed when
- a communication error is detected.
-
- (#) Blocking mode APIs are:
- (++) HAL_UART_Transmit()
- (++) HAL_UART_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are:
- (++) HAL_UART_Transmit_IT()
- (++) HAL_UART_Receive_IT()
- (++) HAL_UART_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are:
- (++) HAL_UART_Transmit_DMA()
- (++) HAL_UART_Receive_DMA()
-
- (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
- (++) HAL_UART_TxCpltCallback()
- (++) HAL_UART_RxCpltCallback()
- (++) HAL_UART_ErrorCallback()
-
- [..]
- (@) In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
- can't be useful.
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
@endverbatim
* @{
@@ -606,7 +1009,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief Sends an amount of data in blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -615,13 +1018,13 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -631,35 +1034,35 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
-
+
/* Init tickstart for timeout managment */
tickstart = HAL_GetTick();
huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0U)
+ while (huart->TxXferCount > 0U)
{
huart->TxXferCount--;
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData;
+ tmp = (uint16_t *) pData;
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(huart->Init.Parity == UART_PARITY_NONE)
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
- pData +=2U;
+ pData += 2U;
}
else
{
- pData +=1U;
+ pData += 1U;
}
}
else
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -667,13 +1070,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
}
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At end of Tx process, restore huart->gState to Ready */
- huart->gState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -688,7 +1091,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receives an amount of data in blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
@@ -697,13 +1100,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -713,7 +1116,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
-
+
/* Init tickstart for timeout managment */
tickstart = HAL_GetTick();
@@ -721,35 +1124,35 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
huart->RxXferCount = Size;
/* Check the remain data to be received */
- while(huart->RxXferCount > 0U)
+ while (huart->RxXferCount > 0U)
{
huart->RxXferCount--;
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData;
- if(huart->Init.Parity == UART_PARITY_NONE)
+ tmp = (uint16_t *) pData;
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- pData +=2U;
+ pData += 2U;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
- pData +=1U;
+ pData += 1U;
}
}
else
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(huart->Init.Parity == UART_PARITY_NONE)
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
@@ -777,7 +1180,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -786,9 +1189,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -807,7 +1210,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
__HAL_UNLOCK(huart);
/* Enable the UART Transmit data register empty Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
return HAL_OK;
}
@@ -818,8 +1221,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
}
/**
- * @brief Receives an amount of data in non blocking mode
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @brief Receives an amount of data in non blocking mode.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
@@ -828,9 +1231,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -848,11 +1251,14 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/* Process Unlocked */
__HAL_UNLOCK(huart);
+ /* Enable the UART Parity Error Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
- /* Enable the UART Parity Error and Data Register not empty Interrupts */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ /* Enable the UART Data Register not empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
return HAL_OK;
}
@@ -864,7 +1270,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -875,9 +1281,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -904,9 +1310,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Set the DMA abort callback */
huart->hdmatx->XferAbortCallback = NULL;
- /* Enable the UART transmit DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
+ /* Enable the UART transmit DMA stream */
+ tmp = (uint32_t *)&pData;
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
@@ -928,11 +1334,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
- * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -940,9 +1346,9 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -968,9 +1374,9 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/* Set the DMA abort callback */
huart->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
+ /* Enable the DMA stream */
+ tmp = (uint32_t *)&pData;
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_UART_CLEAR_OREFLAG(huart);
@@ -998,24 +1404,26 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Pauses the DMA Transfer.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
- uint32_t dmarequest = 0x00U;
+ uint32_t dmarequest = 0x00U;
/* Process Locked */
__HAL_LOCK(huart);
+
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
{
/* Disable the UART DMA Tx request */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
+
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
@@ -1033,7 +1441,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
/**
* @brief Resumes the DMA Transfer.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1042,12 +1450,13 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
/* Process Locked */
__HAL_LOCK(huart);
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
@@ -1068,7 +1477,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
/**
* @brief Stops the DMA Transfer.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1083,12 +1492,12 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
/* Stop UART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
+ /* Abort the UART DMA Tx stream */
+ if (huart->hdmatx != NULL)
{
HAL_DMA_Abort(huart->hdmatx);
}
@@ -1097,12 +1506,12 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
/* Stop UART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream */
+ if (huart->hdmarx != NULL)
{
HAL_DMA_Abort(huart->hdmarx);
}
@@ -1117,7 +1526,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1131,34 +1540,52 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
+ /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1179,9 +1606,9 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1194,18 +1621,27 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
+ /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1221,9 +1657,9 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1237,18 +1673,27 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1266,7 +1711,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
* @param huart UART handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1286,11 +1731,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
}
@@ -1300,11 +1745,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
}
}
/* DMA Rx Handle is valid */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
}
@@ -1315,19 +1760,19 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
}
/* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
+ /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
{
/* UART Tx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
huart->hdmatx->XferAbortCallback = NULL;
}
@@ -1339,18 +1784,18 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
}
/* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
{
/* UART Rx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
huart->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
@@ -1363,7 +1808,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
+ if (AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
huart->TxXferCount = 0x00U;
@@ -1377,7 +1822,13 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1386,9 +1837,9 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1403,19 +1854,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
+ /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
/* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
huart->hdmatx->XferAbortCallback(huart->hdmatx);
@@ -1430,7 +1881,13 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
@@ -1442,7 +1899,13 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1451,9 +1914,9 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
- * - Disable PPP Interrupts
+ * - Disable UART Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
@@ -1469,19 +1932,19 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
@@ -1496,7 +1959,13 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
@@ -1508,7 +1977,13 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1516,24 +1991,24 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
/**
* @brief This function handles UART interrupt request.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- uint32_t isrflags = READ_REG(huart->Instance->SR);
- uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its = READ_REG(huart->Instance->CR3);
- uint32_t errorflags = 0x00U;
- uint32_t dmarequest = 0x00U;
+ uint32_t isrflags = READ_REG(huart->Instance->SR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
+ if (errorflags == RESET)
{
/* UART in mode Receiver -------------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
UART_Receive_IT(huart);
return;
@@ -1541,37 +2016,37 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
}
/* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* UART parity error interrupt occurred ----------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
}
/* UART noise error interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
}
/* UART frame error interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
}
/* UART Over-Run interrupt occurred --------------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
/* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
{
/* UART in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
UART_Receive_IT(huart);
}
@@ -1579,7 +2054,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
@@ -1587,17 +2062,17 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
UART_EndRxTransfer(huart);
/* Disable the UART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
+ /* Abort the UART DMA Rx stream */
+ if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
@@ -1606,20 +2081,39 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
else
{
/* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
}
}
@@ -1627,14 +2121,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
} /* End if some error occurs */
/* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
UART_Transmit_IT(huart);
return;
}
/* UART in mode Transmitter end --------------------------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
UART_EndTransmit_IT(huart);
return;
@@ -1643,37 +2137,37 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/**
* @brief Tx Transfer completed callbacks.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callbacks.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1681,14 +2175,14 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callbacks.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1696,22 +2190,22 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief UART error callbacks.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
@@ -1721,7 +2215,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1730,12 +2224,13 @@ __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
the HAL_UART_AbortCpltCallback can be implemented in the user file.
*/
}
+
/**
* @brief UART Abort Complete callback.
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1750,7 +2245,7 @@ __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1776,6 +2271,8 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
(+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
(+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
(+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+ (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
+ (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
@endverbatim
* @{
@@ -1783,7 +2280,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
/**
* @brief Transmits break characters.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1810,7 +2307,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
/**
* @brief Enters the UART in mute mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1837,7 +2334,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Exits the UART mute mode: wake up software.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1864,7 +2361,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1899,7 +2396,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
/**
* @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1956,13 +2453,13 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
/**
* @brief Returns the UART state.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
temp1 = huart->gState;
temp2 = huart->RxState;
@@ -1971,8 +2468,8 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
/**
* @brief Return the UART error code
- * @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
* @retval UART Error Code
*/
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
@@ -1984,18 +2481,48 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
* @}
*/
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @brief DMA UART transmit process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode*/
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0x00U;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
@@ -2008,33 +2535,46 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Circular mode */
else
{
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
/**
* @brief DMA UART transmit process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
* @brief DMA UART receive process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode*/
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
huart->RxXferCount = 0U;
@@ -2045,59 +2585,78 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
}
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
* @brief DMA UART receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
* @brief DMA UART communication error callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop UART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
- if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
{
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0x00U;
UART_EndTxTransfer(huart);
}
/* Stop UART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
- if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
{
- huart->RxXferCount = 0U;
+ huart->RxXferCount = 0x00U;
UART_EndRxTransfer(huart);
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
* @brief This function handles UART Communication Timeout.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param Flag specifies the UART flag to check.
* @param Status The new Flag status (SET or RESET).
@@ -2108,12 +2667,12 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -2129,7 +2688,6 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
}
}
}
-
return HAL_OK;
}
@@ -2165,16 +2723,23 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
/**
* @brief DMA UART communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma DMA handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0U;
- huart->TxXferCount = 0U;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ huart->RxXferCount = 0x00U;
+ huart->TxXferCount = 0x00U;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2182,19 +2747,20 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
- * @param hdma DMA handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
huart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- if(huart->hdmarx->XferAbortCallback != NULL)
+ if (huart->hdmarx->XferAbortCallback != NULL)
{
return;
}
@@ -2212,7 +2778,13 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2220,19 +2792,20 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
- * @param hdma DMA handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
huart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- if(huart->hdmatx->XferAbortCallback != NULL)
+ if (huart->hdmatx->XferAbortCallback != NULL)
{
return;
}
@@ -2250,7 +2823,13 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2258,12 +2837,13 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
* HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
- * @param hdma DMA handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
huart->TxXferCount = 0x00U;
@@ -2271,7 +2851,13 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
huart->gState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2279,12 +2865,13 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
* HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
- * @param hdma DMA handle.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
huart->RxXferCount = 0x00U;
@@ -2292,27 +2879,33 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
+ uint16_t *tmp;
/* Check that a Tx process is ongoing */
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) huart->pTxBuffPtr;
+ tmp = (uint16_t *) huart->pTxBuffPtr;
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(huart->Init.Parity == UART_PARITY_NONE)
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
huart->pTxBuffPtr += 2U;
}
@@ -2326,13 +2919,13 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
- if(--huart->TxXferCount == 0U)
+ if (--huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
/* Enable the UART Transmit Complete Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
return HAL_OK;
}
@@ -2344,40 +2937,46 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
/**
* @brief Wraps up transmission in non blocking mode.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
- CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
}
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
+ uint16_t *tmp;
/* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+ if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) huart->pRxBuffPtr;
- if(huart->Init.Parity == UART_PARITY_NONE)
+ tmp = (uint16_t *) huart->pRxBuffPtr;
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
huart->pRxBuffPtr += 2U;
@@ -2390,7 +2989,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
}
else
{
- if(huart->Init.Parity == UART_PARITY_NONE)
+ if (huart->Init.Parity == UART_PARITY_NONE)
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
@@ -2400,18 +2999,27 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
}
}
- if(--huart->RxXferCount == 0U)
+ if (--huart->RxXferCount == 0U)
{
- /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
- CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ /* Disable the UART Data Register not empty Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
}
@@ -2425,13 +3033,13 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
/**
* @brief Configures the UART peripheral.
- * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@@ -2440,60 +3048,40 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = huart->Instance->CR2;
-
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
- tmpreg |= (uint32_t)huart->Init.StopBits;
-
- /* Write to USART CR2 */
- WRITE_REG(huart->Instance->CR2, (uint32_t)tmpreg);
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits
+ according to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
/*-------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = huart->Instance->CR1;
-
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE | USART_CR1_OVER8));
-
/* Configure the UART Word Length, Parity and mode:
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
- /* Write to USART CR1 */
- WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+ MODIFY_REG(huart->Instance->CR1,
+ (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = huart->Instance->CR3;
-
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
- tmpreg |= huart->Init.HwFlowCtl;
-
- /* Write to USART CR3 */
- WRITE_REG(huart->Instance->CR3, (uint32_t)tmpreg);
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
/* Check the Over Sampling */
- if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
/*-------------------------- USART BRR Configuration ---------------------*/
#if defined(USART6)
- if((huart->Instance == USART1) || (huart->Instance == USART6))
+ if ((huart->Instance == USART1) || (huart->Instance == USART6))
{
huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
#else
- if(huart->Instance == USART1)
+ if (huart->Instance == USART1)
{
huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
- }
+ }
#endif /* USART6 */
else
{
@@ -2504,15 +3092,15 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
{
/*-------------------------- USART BRR Configuration ---------------------*/
#if defined(USART6)
- if((huart->Instance == USART1) || (huart->Instance == USART6))
+ if ((huart->Instance == USART1) || (huart->Instance == USART6))
{
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
#else
- if(huart->Instance == USART1)
+ if (huart->Instance == USART1)
{
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
- }
+ }
#endif /* USART6 */
else
{
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_usart.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_usart.c
index 45f5abf8a91a1b8773f1bacceda2d22fe5ca1251..f5410522e2d511dd5fc0eee4ed93f81790a566d1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_usart.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_usart.c
@@ -4,7 +4,8 @@
* @author MCD Application Team
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+ * Peripheral (USART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
@@ -15,24 +16,26 @@
[..]
The USART HAL driver can be used as follows:
- (#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
(##) Enable the USARTx interface clock.
(##) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
- (+++) Configure these USART pins as alternate function pull-up.
+ (+++) Configure the USART pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx stream.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+ (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
@@ -99,33 +102,95 @@
[..]
(@) You can refer to the USART HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
+ Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
+ and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
+ or @ref HAL_USART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible USART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -159,13 +224,16 @@
/** @addtogroup USART_Private_Functions
* @{
*/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-static void USART_SetConfig (USART_HandleTypeDef *husart);
+static void USART_SetConfig(USART_HandleTypeDef *husart);
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -210,23 +278,27 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
[..]
The HAL_USART_Init() function follows the USART synchronous configuration
- procedure (details for the procedure are available in reference manual (RM0329)).
+ procedures (details for the procedures are available in reference manual
+ (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
+ RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
+ RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
+ RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
@endverbatim
* @{
*/
/**
- * @brief Initializes the USART mode according to the specified
- * parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Initialize the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == NULL)
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -234,12 +306,25 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
- if(husart->State == HAL_USART_STATE_RESET)
+ if (husart->State == HAL_USART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ USART_InitCallbacksToDefault(husart);
+
+ if (husart->MspInitCallback == NULL)
+ {
+ husart->MspInitCallback = HAL_USART_MspInit;
+ }
+
/* Init the low level hardware */
+ husart->MspInitCallback(husart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
husart->State = HAL_USART_STATE_BUSY;
@@ -258,21 +343,21 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* Initialize the USART state */
husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the USART peripheral.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == NULL)
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -285,8 +370,17 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
/* Disable the Peripheral */
__HAL_USART_DISABLE(husart);
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ if (husart->MspDeInitCallback == NULL)
+ {
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ husart->MspDeInitCallback(husart);
+#else
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_RESET;
@@ -299,34 +393,262 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
/**
* @brief USART MSP Init.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_MspInit could be implemented in the user file
*/
}
/**
* @brief USART MSP DeInit.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User USART Callback
+ * To be used instead of the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
++ */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param husart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -375,7 +697,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
(#) Non Blocking mode functions with DMA are :
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
- (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
@@ -388,13 +710,31 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
* @brief Simplex Send an amount of data in blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -403,12 +743,12 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -424,19 +764,19 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
husart->TxXferSize = Size;
husart->TxXferCount = Size;
- while(husart->TxXferCount > 0U)
+ while (husart->TxXferCount > 0U)
{
husart->TxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pTxData;
+ tmp = (uint16_t *) pTxData;
husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
pTxData += 2U;
}
@@ -447,7 +787,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
}
else
{
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -455,7 +795,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
}
}
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -475,7 +815,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pRxData Pointer to data buffer
* @param Size Amount of data to be received
@@ -484,12 +824,12 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if ((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -505,13 +845,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Check the remain data to be received */
- while(husart->RxXferCount > 0U)
+ while (husart->RxXferCount > 0U)
{
husart->RxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -519,26 +859,26 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pRxData ;
- if(husart->Init.Parity == USART_PARITY_NONE)
+ tmp = (uint16_t *) pRxData ;
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- pRxData +=2U;
+ pRxData += 2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- pRxData +=1U;
+ pRxData += 1U;
}
}
else
{
/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -547,11 +887,11 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
/* Wait until RXNE flag is set to receive the byte */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
@@ -580,22 +920,22 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data transmitted buffer
* @param pRxData Pointer to data received buffer
* @param Size Amount of data to be sent
- * @param Timeout Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint32_t tickstart = 0U;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -614,20 +954,20 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
husart->RxXferCount = Size;
/* Check the remain data to be received */
- while(husart->TxXferCount > 0U)
+ while (husart->TxXferCount > 0U)
{
husart->TxXferCount--;
husart->RxXferCount--;
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pTxData;
+ tmp = (uint16_t *) pTxData;
husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
pTxData += 2U;
}
@@ -637,12 +977,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
}
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pRxData ;
- if(husart->Init.Parity == USART_PARITY_NONE)
+ tmp = (uint16_t *) pRxData ;
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
pRxData += 2U;
@@ -656,18 +996,18 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
else
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
/* Receive data */
*pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
@@ -695,7 +1035,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -704,9 +1044,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -745,7 +1085,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pRxData Pointer to data buffer
* @param Size Amount of data to be received
@@ -753,9 +1093,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if ((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -791,7 +1131,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data transmitted buffer
* @param pRxData Pointer to data received buffer
@@ -800,9 +1140,9 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -844,7 +1184,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data buffer
* @param Size Amount of data to be sent
@@ -854,9 +1194,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
{
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -882,9 +1222,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
/* Set the DMA abort callback */
husart->hdmatx->XferAbortCallback = NULL;
- /* Enable the USART transmit DMA Stream */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Enable the USART transmit DMA stream */
+ tmp = (uint32_t *)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
@@ -906,7 +1246,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
/**
* @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pRxData Pointer to data buffer
* @param Size Amount of data to be received
@@ -918,9 +1258,9 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
{
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if ((pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -959,14 +1299,14 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/* Set the DMA AbortCpltCallback */
husart->hdmatx->XferAbortCallback = NULL;
- /* Enable the USART receive DMA Stream */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+ /* Enable the USART receive DMA stream */
+ tmp = (uint32_t *)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
- /* Enable the USART transmit DMA Stream: the transmit stream is used in order
+ /* Enable the USART transmit DMA stream: the transmit stream is used in order
to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive one */
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
__HAL_USART_CLEAR_OREFLAG(husart);
@@ -998,7 +1338,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData Pointer to data transmitted buffer
* @param pRxData Pointer to data received buffer
@@ -1010,9 +1350,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
{
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
@@ -1048,13 +1388,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
/* Set the DMA abort callback */
husart->hdmarx->XferAbortCallback = NULL;
- /* Enable the USART receive DMA Stream */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+ /* Enable the USART receive DMA stream */
+ tmp = (uint32_t *)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
- /* Enable the USART transmit DMA Stream */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+ /* Enable the USART transmit DMA stream */
+ tmp = (uint32_t *)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
@@ -1088,8 +1428,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
}
/**
- * @brief Pauses the DMA Transfer.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Pauses the DMA Transfer.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1108,8 +1448,8 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
}
/**
- * @brief Resumes the DMA Transfer.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Resumes the DMA Transfer.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1128,8 +1468,8 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
}
/**
- * @brief Stops the DMA Transfer.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Stops the DMA Transfer.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1144,12 +1484,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
/* Stop USART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
- if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
{
USART_EndTxTransfer(husart);
/* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
HAL_DMA_Abort(husart->hdmatx);
}
@@ -1160,12 +1500,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
/* Stop USART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
{
USART_EndRxTransfer(husart);
/* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
HAL_DMA_Abort(husart->hdmarx);
}
@@ -1197,12 +1537,12 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -1213,12 +1553,12 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
}
/* Disable the USART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
/* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
@@ -1267,11 +1607,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
}
@@ -1281,11 +1621,11 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
}
}
/* DMA Rx Handle is valid */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
}
@@ -1296,19 +1636,19 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
}
/* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
/* USART Tx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
{
husart->hdmatx->XferAbortCallback = NULL;
}
@@ -1320,18 +1660,18 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
}
/* Disable the USART DMA Rx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
/* USART Rx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
husart->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
@@ -1344,7 +1684,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
- if(AbortCplt == 0x01U)
+ if (AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
husart->TxXferCount = 0x00U;
@@ -1357,7 +1697,13 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
husart->State = HAL_USART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1365,7 +1711,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
/**
* @brief This function handles USART interrupt request.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1379,12 +1725,12 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
- if(errorflags == RESET)
+ if (errorflags == RESET)
{
/* USART in mode Receiver -------------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
USART_Receive_IT(husart);
}
@@ -1396,38 +1742,38 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
}
}
/* If some errors occur */
- if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* USART parity error interrupt occurred ----------------------------------*/
- if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
husart->ErrorCode |= HAL_USART_ERROR_PE;
}
/* USART noise error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
husart->ErrorCode |= HAL_USART_ERROR_NE;
}
/* USART frame error interrupt occurred --------------------------------*/
- if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
husart->ErrorCode |= HAL_USART_ERROR_FE;
}
/* USART Over-Run interrupt occurred -----------------------------------*/
- if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)
{
/* USART in mode Receiver -----------------------------------------------*/
- if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
USART_Receive_IT(husart);
}
@@ -1439,7 +1785,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
+ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
{
/* Set the USART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
@@ -1451,13 +1797,13 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
/* Set the USART DMA Abort callback :
will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
husart->hdmarx->XferAbortCallback(husart->hdmarx);
@@ -1466,19 +1812,37 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
}
}
@@ -1486,9 +1850,9 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
}
/* USART in mode Transmitter -----------------------------------------------*/
- if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
USART_Transmit_IT(husart);
}
@@ -1500,7 +1864,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
}
/* USART in mode Transmitter (transmission end) ----------------------------*/
- if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
USART_EndTransmit_IT(husart);
return;
@@ -1509,37 +1873,37 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/**
* @brief Tx Transfer completed callbacks.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1547,14 +1911,14 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callbacks.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1562,14 +1926,14 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1577,22 +1941,22 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback could be implemented in the user file
*/
}
/**
* @brief USART error callbacks.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
- /* NOTE: This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_ErrorCallback could be implemented in the user file
*/
}
@@ -1602,7 +1966,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
* @param husart USART handle.
* @retval None
*/
-__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -1637,7 +2001,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
/**
* @brief Returns the USART state.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL state
*/
@@ -1648,8 +2012,8 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
/**
* @brief Return the USART error code
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
* @retval USART Error Code
*/
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
@@ -1661,19 +2025,43 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
* @}
*/
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param husart USART handle.
+ * @retval none
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+ /* Init the USART Callback settings */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
/**
* @brief DMA USART transmit process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
husart->TxXferCount = 0U;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
@@ -1686,36 +2074,49 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/* DMA Circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief DMA USART transmit process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA USART transmit process half complete callback
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half Complete Callback */
+ husart->TxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Half Complete Callback */
HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
* @brief DMA USART receive process complete callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
husart->RxXferCount = 0x00U;
@@ -1724,87 +2125,124 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit
- in the USART CR3 register */
+ in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* The USART state is HAL_USART_STATE_BUSY_RX */
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
/* DMA circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief DMA USART receive process half complete callback
- * @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA USART receive process half complete callback
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Half Complete Callback */
+ husart->RxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Half Complete Callback */
HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
* @brief DMA USART communication error callback.
- * @param hdma DMA handle
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
husart->RxXferCount = 0x00U;
husart->TxXferCount = 0x00U;
/* Stop USART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
- if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
{
USART_EndTxTransfer(husart);
}
/* Stop USART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
- if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
{
USART_EndRxTransfer(husart);
}
husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
* @brief This function handles USART Communication Timeout.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param Flag specifies the USART flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Tickstart Tick start value.
@@ -1814,12 +2252,12 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma)
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
/* Disable the USART Transmit Complete Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
@@ -1833,7 +2271,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1882,11 +2320,17 @@ static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
*/
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
husart->RxXferCount = 0x00U;
husart->TxXferCount = 0x00U;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
@@ -1899,14 +2343,14 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
*/
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
husart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- if(husart->hdmarx->XferAbortCallback != NULL)
+ if (husart->hdmarx->XferAbortCallback != NULL)
{
return;
}
@@ -1923,7 +2367,13 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
@@ -1936,14 +2386,14 @@ static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
*/
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
husart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
- if(husart->hdmatx->XferAbortCallback != NULL)
+ if (husart->hdmatx->XferAbortCallback != NULL)
{
return;
}
@@ -1960,27 +2410,33 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp;
+ uint16_t *tmp;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) husart->pTxBuffPtr;
+ tmp = (uint16_t *) husart->pTxBuffPtr;
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
husart->pTxBuffPtr += 2U;
}
@@ -1994,7 +2450,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
- if(--husart->TxXferCount == 0U)
+ if (--husart->TxXferCount == 0U)
{
/* Disable the USART Transmit data register empty Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
@@ -2012,7 +2468,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
/**
* @brief Wraps up transmission in non blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -2026,26 +2482,32 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
return HAL_OK;
}
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp;
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ uint16_t *tmp;
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) husart->pRxBuffPtr;
- if(husart->Init.Parity == USART_PARITY_NONE)
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
husart->pRxBuffPtr += 2U;
@@ -2055,7 +2517,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
husart->pRxBuffPtr += 1U;
}
- if(--husart->RxXferCount != 0x00U)
+ if (--husart->RxXferCount != 0x00U)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
@@ -2063,7 +2525,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
}
else
{
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
@@ -2072,14 +2534,14 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
- if(--husart->RxXferCount != 0x00U)
+ if (--husart->RxXferCount != 0x00U)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
}
}
- if(husart->RxXferCount == 0U)
+ if (husart->RxXferCount == 0U)
{
/* Disable the USART RXNE Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
@@ -2091,7 +2553,13 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
return HAL_OK;
}
@@ -2105,25 +2573,25 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp;
+ uint16_t *tmp;
- if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
- if(husart->TxXferCount != 0x00U)
+ if (husart->TxXferCount != 0x00U)
{
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) husart->pTxBuffPtr;
+ tmp = (uint16_t *) husart->pTxBuffPtr;
husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
husart->pTxBuffPtr += 2U;
}
@@ -2139,21 +2607,21 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
husart->TxXferCount--;
/* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
+ if (husart->TxXferCount == 0U)
{
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
}
}
}
- if(husart->RxXferCount != 0x00U)
+ if (husart->RxXferCount != 0x00U)
{
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ if (husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- tmp = (uint16_t*) husart->pRxBuffPtr;
- if(husart->Init.Parity == USART_PARITY_NONE)
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
husart->pRxBuffPtr += 2U;
@@ -2166,7 +2634,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
}
else
{
- if(husart->Init.Parity == USART_PARITY_NONE)
+ if (husart->Init.Parity == USART_PARITY_NONE)
{
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
}
@@ -2180,7 +2648,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
}
/* Check the latest data received */
- if(husart->RxXferCount == 0U)
+ if (husart->RxXferCount == 0U)
{
/* Disable the USART RXNE Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
@@ -2193,7 +2661,13 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
return HAL_OK;
}
@@ -2207,8 +2681,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
}
/**
- * @brief Configures the USART pferipheral.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * @brief Configures the USART peripheral.
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -2240,8 +2714,8 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
/* Set CPHA bit according to husart->Init.CLKPhase value */
/* Set LBCL bit according to husart->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity |
- husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
+ tmpreg |= (uint32_t)(USART_CLOCK_ENABLE | husart->Init.CLKPolarity |
+ husart->Init.CLKPhase | husart->Init.CLKLastBit | husart->Init.StopBits);
/* Write to USART CR2 */
WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
@@ -2284,6 +2758,10 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
}
}
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_wwdg.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_wwdg.c
index 7cdbad33018982ae8efd10807f0b8b6b2b8c87f3..e117fa35716c6a078760d5e354eae2a2905fac1c 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_wwdg.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_hal_wwdg.c
@@ -5,112 +5,110 @@
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and de-initialization functions
+ * + Initialization and Configuration functions
* + IO operation functions
- * + Peripheral State functions
@verbatim
==============================================================================
- ##### WWDG specific features #####
+ ##### WWDG Specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
+ value rolls down from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
- (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
- (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
-
- (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: ~73.14µs
+ (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: ~599.18ms
+ ==============================================================================
##### How to use this driver #####
==============================================================================
[..]
+ *** Common driver usage ***
+ ===========================
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
+ (+) Set the WWDG prescaler, refresh window and counter value
+ using HAL_WWDG_Init() function.
+ (+) Start the WWDG using HAL_WWDG_Start() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
+ generated when the counter reaches 0x40, and then start the WWDG using
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
+ add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
+ the counter is lower than the refresh window value already programmed.
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
-
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+ [..]
+ *** Callback registration ***
+ =============================
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ @ref HAL_WWDG_RegisterCallback() to register a user callback.
+
+ (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -140,8 +138,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@@ -166,7 +164,7 @@
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
- if(hwwdg == NULL)
+ if (hwwdg == NULL)
{
return HAL_ERROR;
}
@@ -178,8 +176,24 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if(hwwdg->EwiCallback == NULL)
+ {
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ }
+
+ if(hwwdg->MspInitCallback == NULL)
+ {
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hwwdg->MspInitCallback(hwwdg);
+#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
+#endif
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -191,6 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
return HAL_OK;
}
+
/**
* @brief Initialize the WWDG MSP.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
@@ -210,6 +225,82 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
*/
}
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User WWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch(CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = pCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a WWDG Callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch(CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif
+
/**
* @}
*/
@@ -262,27 +353,33 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hwwdg->EwiCallback(hwwdg);
+#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif
}
}
}
+
/**
* @brief WWDG Early Wakeup callback.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_adc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_adc.c
index 6ac94cc15005555afc12e021870dca655beb1359..5093ec65cbf2428114fe2f275268632be6bc848d 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_adc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_adc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_crc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_crc.c
index e68f1e2168738d1b69704a711c3e0bd1ad5eb314..821b281e8ae6fa08b5d85f22369f2303463f439e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_crc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_crc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dac.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dac.c
index 5fca9d54daf8a77bf7778972a7123dbb4fa3d4b7..cc14cc5f16796170e84a1031991a6eccb93249d1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dac.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dac.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma.c
index 0eec2613c24693160a561728dcfb901c7e322181..a662b6fd37c920ecb241f09a6b197d4028e66d89 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma2d.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma2d.c
index ff5bd4a5622de53573ae8630a5f7ad57905b684f..9df5b49ff212df5b7286c46eed7f4e40096f3688 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma2d.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_dma2d.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -87,11 +71,14 @@
#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
+
#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX)
#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
+
+
#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \
@@ -112,6 +99,8 @@
#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \
((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
+
+
/**
* @}
*/
@@ -162,7 +151,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
* @note DMA2D transfers must be disabled to set initialization bits in configuration registers,
* otherwise ERROR result is returned.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
+ * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure
* that contains the configuration information for the specified DMA2D peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
@@ -172,7 +161,8 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
{
ErrorStatus status = ERROR;
LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
- uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U;
+ uint32_t tmp, tmp1, tmp2;
+ uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -196,7 +186,13 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
- MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, DMA2D_InitStruct->ColorMode);
+ regMask = DMA2D_OPFCCR_CM;
+ regValue = DMA2D_InitStruct->ColorMode;
+
+
+
+
+ MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue);
/* DMA2D OOR register configuration ------------------------------------------*/
LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
@@ -224,7 +220,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini
/**
* @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
- * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
+ * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -247,9 +243,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
* @brief Configure the foreground or background according to the specified parameters
* in the LL_DMA2D_LayerCfgTypeDef structure.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
+ * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
* the configuration information for the specified layer.
- * @param LayerIdx DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval None
@@ -267,6 +263,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D
assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
+
if (LayerIdx == 0U)
{
/* Configure the background memory address */
@@ -313,7 +310,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D
/**
* @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
- * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
+ * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -337,15 +334,15 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
* @brief Initialize DMA2D output color register according to the specified parameters
* in DMA2D_ColorStruct.
* @param DMA2Dx DMA2D Instance
- * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
+ * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains
* the color configuration information for the specified DMA2D peripheral.
* @retval None
*/
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
{
- uint32_t outgreen = 0U;
- uint32_t outred = 0U;
- uint32_t outalpha = 0U;
+ uint32_t outgreen;
+ uint32_t outred;
+ uint32_t outalpha;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -402,7 +399,7 @@ void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DM
*/
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -446,7 +443,7 @@ uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -490,7 +487,7 @@ uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -534,7 +531,7 @@ uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
*/
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
- uint32_t color = 0U;
+ uint32_t color;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
@@ -595,3 +592,4 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_exti.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_exti.c
index 0cb4875032b1fdd139b3d836dcd413da8344e753..31d70ac68196c6b7d4392a54259fa2bccc12f9fb 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_exti.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_exti.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fmc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fmc.c
index e53e77c289c1de8c247ce369dc1afc278886ffc4..f352abacbeebbbaeb3064576aa2757be7af111e1 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fmc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fmc.c
@@ -44,29 +44,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fsmc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fsmc.c
index 49d124ed4ec0bb038281ad64a14ba1071993c74b..099c5a2423b51c1561f74c11f144f2369e2b39e9 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fsmc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_fsmc.c
@@ -42,29 +42,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_gpio.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_gpio.c
index bf4cdfcb885071cc2a3bc8fd76e5c7a2901515b0..eba14b097ca522a5aa628b38fbe9b63b78ea15c6 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_gpio.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_gpio.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_i2c.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_i2c.c
index 0b69db8e99ab8901b4ddb49f2e009b34b0259d63..125fb2ca13fc7a5a7552bd5f2528afd2cfe9a14c 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_i2c.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_i2c.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -67,9 +51,9 @@
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
+#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
-#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
+#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
@@ -105,8 +89,8 @@
* @brief De-initialize the I2C registers to their default reset values.
* @param I2Cx I2C Instance.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are de-initialized
- * - ERROR: I2C registers are not de-initialized
+ * - SUCCESS I2C registers are de-initialized
+ * - ERROR I2C registers are not de-initialized
*/
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
@@ -155,8 +139,8 @@ uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
* @param I2Cx I2C Instance.
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: I2C registers are initialized
- * - ERROR: Not applicable
+ * - SUCCESS I2C registers are initialized
+ * - ERROR Not applicable
*/
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
{
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_lptim.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_lptim.c
index 5fb42253a7037eaff954152e80019bea48025e8b..2c05217ba837432bb7bee19c1db222f9c106b9de 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_lptim.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_lptim.c
@@ -4,51 +4,36 @@
* @author MCD Application Team
* @brief LPTIM LL module driver.
******************************************************************************
- * @attention
+ * @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ * ******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_lptim.h"
#include "stm32f4xx_ll_bus.h"
+#include "stm32f4xx_ll_rcc.h"
+
#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
+#include "stm32_assert.h"
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F4xx_LL_Driver
* @{
*/
-#if defined (LPTIM1) || defined (LPTIM2)
+#if defined (LPTIM1)
/** @addtogroup LPTIM_LL
* @{
@@ -61,29 +46,36 @@
/** @addtogroup LPTIM_LL_Private_Macros
* @{
*/
-#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
- || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+ || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
-#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
- || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
+ || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
-#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
-#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
- || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+ || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LPTIM_LL_Exported_Functions
* @{
@@ -100,7 +92,7 @@
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
{
ErrorStatus result = SUCCESS;
@@ -112,13 +104,6 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
}
-#if defined(LPTIM2)
- else if (LPTIMx == LPTIM2)
- {
- LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
- LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
- }
-#endif
else
{
result = ERROR;
@@ -133,7 +118,7 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
* @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
* @retval None
*/
-void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
/* Set the default configuration */
LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
@@ -152,36 +137,35 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
* - SUCCESS: LPTIMx instance has been initialized
* - ERROR: LPTIMx instance hasn't been initialized
*/
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
{
ErrorStatus result = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+ assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+ assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+ assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+ assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
/* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
(ENABLE bit is reset to 0).
*/
- if (LL_LPTIM_IsEnabled(LPTIMx))
+ if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
{
result = ERROR;
}
else
{
- /* Check the parameters */
- assert_param(IS_LPTIM_INSTANCE(LPTIMx));
- assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
- assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
- assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
- assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
-
- /* Set CKSEL bitfield according to ClockSource value */
- /* Set PRESC bitfield according to Prescaler value */
- /* Set WAVE bitfield according to Waveform value */
- /* Set WAVEPOL bitfield according to Polarity value */
- MODIFY_REG(LPTIMx->CFGR,
- (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
- LPTIM_InitStruct->ClockSource | \
- LPTIM_InitStruct->Prescaler | \
- LPTIM_InitStruct->Waveform | \
- LPTIM_InitStruct->Polarity);
+ /* Set CKSEL bitfield according to ClockSource value */
+ /* Set PRESC bitfield according to Prescaler value */
+ /* Set WAVE bitfield according to Waveform value */
+ /* Set WAVEPOL bitfield according to Polarity value */
+ MODIFY_REG(LPTIMx->CFGR,
+ (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
+ LPTIM_InitStruct->ClockSource | \
+ LPTIM_InitStruct->Prescaler | \
+ LPTIM_InitStruct->Waveform | \
+ LPTIM_InitStruct->Polarity);
}
return result;
@@ -195,11 +179,114 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In
* @}
*/
+/**
+ * @brief Disable the LPTIM instance
+ * @rmtoll CR ENABLE LL_LPTIM_Disable
+ * @param LPTIMx Low-Power Timer instance
+ * @note The following sequence is required to solve LPTIM disable HW limitation.
+ * Please check Errata Sheet ES0335 for more details under "MCU may remain
+ * stuck in LPTIM interrupt when entering Stop mode" section.
+ * @retval None
+ */
+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+ LL_RCC_ClocksTypeDef rcc_clock;
+ uint32_t tmpclksource = 0;
+ uint32_t tmpIER;
+ uint32_t tmpCFGR;
+ uint32_t tmpCMP;
+ uint32_t tmpARR;
+ uint32_t tmpOR;
+
+ /* Check the parameters */
+ assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+ __disable_irq();
+
+ /********** Save LPTIM Config *********/
+ /* Save LPTIM source clock */
+ switch ((uint32_t)LPTIMx)
+ {
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ default:
+ break;
+ }
+
+ /* Save LPTIM configuration registers */
+ tmpIER = LPTIMx->IER;
+ tmpCFGR = LPTIMx->CFGR;
+ tmpCMP = LPTIMx->CMP;
+ tmpARR = LPTIMx->ARR;
+ tmpOR = LPTIMx->OR;
+
+ /************* Reset LPTIM ************/
+ (void)LL_LPTIM_DeInit(LPTIMx);
+
+ /********* Restore LPTIM Config *******/
+ LL_RCC_GetSystemClocksFreq(&rcc_clock);
+
+ if ((tmpCMP != 0UL) || (tmpARR != 0UL))
+ {
+ /* Force LPTIM source kernel clock from APB */
+ switch ((uint32_t)LPTIMx)
+ {
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
+ }
+
+ if (tmpCMP != 0UL)
+ {
+ /* Restore CMP and ARR registers (LPTIM should be enabled first) */
+ LPTIMx->CR |= LPTIM_CR_ENABLE;
+ LPTIMx->CMP = tmpCMP;
+
+ /* Polling on CMP write ok status after above restore operation */
+ do
+ {
+ rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+ } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+ LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
+ }
+
+ if (tmpARR != 0UL)
+ {
+ LPTIMx->CR |= LPTIM_CR_ENABLE;
+ LPTIMx->ARR = tmpARR;
+
+ LL_RCC_GetSystemClocksFreq(&rcc_clock);
+ /* Polling on ARR write ok status after above restore operation */
+ do
+ {
+ rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+ } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+ LL_LPTIM_ClearFlag_ARROK(LPTIMx);
+ }
+
+ /* Restore LPTIM source kernel clock */
+ LL_RCC_SetLPTIMClockSource(tmpclksource);
+ }
+
+ /* Restore configuration registers (LPTIM should be disabled first) */
+ LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
+ LPTIMx->IER = tmpIER;
+ LPTIMx->CFGR = tmpCFGR;
+ LPTIMx->OR = tmpOR;
+
+ __enable_irq();
+}
+
/**
* @}
*/
-#endif /* defined (LPTIM1) || defined (LPTIM2) */
+#endif /* LPTIM1 */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_pwr.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_pwr.c
index 3a04e896838575813e44f805347d9005522fd494..fe04bc44c935a606f2b677b13595fb1ad47b631e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_pwr.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_pwr.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rcc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rcc.c
index 16b2efdad61a6ca5c0e1ed7a74646cbad58a3533..dd98fbfdb3122c99f4d4f0328ffb0fb5e244b430 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rcc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rcc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rng.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rng.c
index 37e44eefbf30c0fbe4423cf26f3315e0b44639c4..d31a5ed28fad6f7063d3bf36187c07591080430e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rng.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rng.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -80,7 +64,6 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
-
#if !defined (RCC_AHB2_SUPPORT)
/* Enable RNG reset state */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
@@ -94,7 +77,6 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
/* Release RNG from reset state */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
#endif
-
return (SUCCESS);
}
@@ -110,7 +92,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
* @}
*/
-#endif /* defined (RNG) */
+#endif /* RNG */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rtc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rtc.c
index 71188f2478531325665a21e1e8d2c31d61de12ee..c6fa695a18caa0259c0f194b4ba48c7f0e152406 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rtc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_rtc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_sdmmc.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_sdmmc.c
index af7457439b9f631b2a906ec5bceef2e932cd04e3..edeb0a155497a6708a373d2195a4859b7429f6b8 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_sdmmc.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_sdmmc.c
@@ -145,29 +145,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_spi.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_spi.c
index c30e5b8a279a7b4d58de691d3013daad75b3d9b0..5d2902b46d56d6c89f9f36afc6801e941e586cef 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_spi.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_spi.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -222,7 +206,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -406,7 +390,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -415,9 +399,9 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- uint32_t sourceclock = 0U;
+ uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp;
+ uint32_t sourceclock;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
@@ -475,25 +459,25 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
/* Remove the floating point */
tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+ i2sodd = (tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+ i2sdiv = ((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
+ i2sodd = (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
@@ -568,7 +552,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_
*/
ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint16_t mode = 0U;
+ uint32_t mode = 0U;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_tim.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_tim.c
index 583710f66aec9dfe68f61204b4784e55646074a1..f99d29fdb8663fe6a5eb652fd7d93ca2969b395e 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_tim.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_tim.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -302,11 +286,11 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
{
/* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
}
/**
@@ -319,7 +303,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
*/
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
{
- uint32_t tmpcr1 = 0U;
+ uint32_t tmpcr1;
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(TIMx));
@@ -501,8 +485,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct
*/
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
@@ -592,10 +576,10 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI
*/
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
@@ -674,7 +658,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
@@ -688,7 +672,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
@@ -746,9 +730,9 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
*/
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
@@ -825,9 +809,9 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
@@ -904,9 +888,9 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
@@ -983,9 +967,9 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
*/
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usart.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usart.c
index 57b39270ce7b2d88617a7b61035545291a691e4d..dab4fddf178cc126cf6a746b6bc3566c0e6823e0 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usart.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usart.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -402,8 +387,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
+ * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
* @retval None
*/
@@ -425,7 +410,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
@@ -486,8 +471,8 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
+ * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usb.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usb.c
index 787ac1c5564d9e655c0f3552636276cd2c0babea..9263fc3183b1062ed841a3db506cac6d9d7c24ed 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usb.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_usb.c
@@ -26,29 +26,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -60,34 +44,29 @@
* @{
*/
-#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
- ##### Initialization/de-initialization functions #####
+ ##### Initialization/de-initialization functions #####
===============================================================================
- [..] This section provides functions allowing to:
@endverbatim
* @{
@@ -96,15 +75,16 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
/**
* @brief Initializes the USB Core
* @param USBx USB Instance
- * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ HAL_StatusTypeDef ret;
+
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
-
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Init The ULPI Interface */
@@ -112,12 +92,12 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
- if(cfg.use_external_vbus == 1U)
+ if (cfg.use_external_vbus == 1U)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
/* Reset after a PHY select */
- USB_CoreReset(USBx);
+ ret = USB_CoreReset(USBx);
}
else /* FS interface (embedded Phy) */
{
@@ -125,18 +105,110 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
/* Reset after a PHY select and set Host mode */
- USB_CoreReset(USBx);
+ ret = USB_CoreReset(USBx);
- /* Deactivate the power down*/
- USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+ if (cfg.battery_charging_enable == 0U)
+ {
+ /* Activate the USB Transceiver */
+ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+ }
+ else
+ {
+ /* Deactivate the USB Transceiver */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+ }
}
- if(cfg.dma_enable == ENABLE)
+ if (cfg.dma_enable == 1U)
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
}
+ return ret;
+}
+
+
+/**
+ * @brief Set the USB turnaround time
+ * @param USBx USB Instance
+ * @param hclk: AHB clock frequency
+ * @retval USB turnaround time In PHY Clocks number
+ */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+ uint32_t hclk, uint8_t speed)
+{
+ uint32_t UsbTrd;
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ latency to the Data FIFO */
+ if (speed == USBD_FS_SPEED)
+ {
+ if ((hclk >= 14200000U) && (hclk < 15000000U))
+ {
+ /* hclk Clock Range between 14.2-15 MHz */
+ UsbTrd = 0xFU;
+ }
+ else if ((hclk >= 15000000U) && (hclk < 16000000U))
+ {
+ /* hclk Clock Range between 15-16 MHz */
+ UsbTrd = 0xEU;
+ }
+ else if ((hclk >= 16000000U) && (hclk < 17200000U))
+ {
+ /* hclk Clock Range between 16-17.2 MHz */
+ UsbTrd = 0xDU;
+ }
+ else if ((hclk >= 17200000U) && (hclk < 18500000U))
+ {
+ /* hclk Clock Range between 17.2-18.5 MHz */
+ UsbTrd = 0xCU;
+ }
+ else if ((hclk >= 18500000U) && (hclk < 20000000U))
+ {
+ /* hclk Clock Range between 18.5-20 MHz */
+ UsbTrd = 0xBU;
+ }
+ else if ((hclk >= 20000000U) && (hclk < 21800000U))
+ {
+ /* hclk Clock Range between 20-21.8 MHz */
+ UsbTrd = 0xAU;
+ }
+ else if ((hclk >= 21800000U) && (hclk < 24000000U))
+ {
+ /* hclk Clock Range between 21.8-24 MHz */
+ UsbTrd = 0x9U;
+ }
+ else if ((hclk >= 24000000U) && (hclk < 27700000U))
+ {
+ /* hclk Clock Range between 24-27.7 MHz */
+ UsbTrd = 0x8U;
+ }
+ else if ((hclk >= 27700000U) && (hclk < 32000000U))
+ {
+ /* hclk Clock Range between 27.7-32 MHz */
+ UsbTrd = 0x7U;
+ }
+ else /* if(hclk >= 32000000) */
+ {
+ /* hclk Clock Range between 32-200 MHz */
+ UsbTrd = 0x6U;
+ }
+ }
+ else if (speed == USBD_HS_SPEED)
+ {
+ UsbTrd = USBD_HS_TRDT_VALUE;
+ }
+ else
+ {
+ UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+ }
+
+ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+ USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
return HAL_OK;
}
@@ -152,7 +224,6 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
return HAL_OK;
}
-
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
@@ -170,23 +241,27 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @param mode current core mode
* This parameter can be one of these values:
- * @arg USB_OTG_DEVICE_MODE: Peripheral mode
- * @arg USB_OTG_HOST_MODE: Host mode
- * @arg USB_OTG_DRD_MODE: Dual Role Device mode
+ * @arg USB_DEVICE_MODE: Peripheral mode
+ * @arg USB_HOST_MODE: Host mode
+ * @arg USB_DRD_MODE: Dual Role Device mode
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
- if ( mode == USB_OTG_HOST_MODE)
+ if (mode == USB_HOST_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
}
- else if ( mode == USB_OTG_DEVICE_MODE)
+ else if (mode == USB_DEVICE_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
}
+ else
+ {
+ return HAL_ERROR;
+ }
HAL_Delay(50U);
return HAL_OK;
@@ -200,35 +275,52 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
- uint32_t i = 0U;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t i;
- /*Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
- USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+ for (i = 0U; i < 15U; i++)
+ {
+ USBx->DIEPTXF[i] = 0U;
+ }
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
- /* B-peripheral session valid override enable*/
+ /* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
}
+ else
+ {
+ /* Enable HW VBUS sensing */
+ USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+ }
#else
+ /* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
{
+ /*
+ * Disable HW VBUS sensing. VBUS is internally considered to be always
+ * at VBUS-Valid level (5V).
+ */
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
}
else
{
- /* Enable VBUS */
+ /* Enable HW VBUS sensing */
+ USBx->GOTGCTL &= ~USB_OTG_GCCFG_NOVBUSSENS;
USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
}
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
@@ -236,40 +328,53 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Device mode configuration */
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
- if(cfg.phy_itface == USB_OTG_ULPI_PHY)
+ if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
- if(cfg.speed == USB_OTG_SPEED_HIGH)
+ if (cfg.speed == USBD_HS_SPEED)
{
- /* Set High speed phy */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
+ /* Set Core speed to High speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
}
else
{
- /* set High speed phy in Full speed mode */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
+ /* Set Core speed to Full speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
}
}
else
{
- /* Set Full speed phy */
- USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
+ /* Set Core speed to Full speed mode */
+ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
}
/* Flush the FIFOs */
- USB_FlushTxFifo(USBx , 0x10U); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
+ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+ {
+ ret = HAL_ERROR;
+ }
+
+ if (USB_FlushRxFifo(USBx) != HAL_OK)
+ {
+ ret = HAL_ERROR;
+ }
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
USBx_DEVICE->DOEPMSK = 0U;
- USBx_DEVICE->DAINT = 0xFFFFFFFFU;
USBx_DEVICE->DAINTMSK = 0U;
for (i = 0U; i < cfg.dev_endpoints; i++)
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
- USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
+ if (i == 0U)
+ {
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+ }
+ else
+ {
+ USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+ }
}
else
{
@@ -277,14 +382,21 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
}
USBx_INEP(i)->DIEPTSIZ = 0U;
- USBx_INEP(i)->DIEPINT = 0xFFU;
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
}
for (i = 0U; i < cfg.dev_endpoints; i++)
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
- USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
+ if (i == 0U)
+ {
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+ }
+ else
+ {
+ USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+ }
}
else
{
@@ -292,7 +404,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
- USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
@@ -300,10 +412,12 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
if (cfg.dma_enable == 1U)
{
/*Set threshold parameters */
- USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
- USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
+ USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
+ USB_OTG_DTHRCTL_RXTHRLEN_6;
- i= USBx_DEVICE->DTHRCTL;
+ USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
+ USB_OTG_DTHRCTL_ISOTHREN |
+ USB_OTG_DTHRCTL_NONISOTHREN;
}
/* Disable all interrupts. */
@@ -313,31 +427,30 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx->GINTSTS = 0xBFFFFFFFU;
/* Enable the common interrupts */
- if (cfg.dma_enable == DISABLE)
+ if (cfg.dma_enable == 0U)
{
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
}
/* Enable interrupts matching to the Device mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
- USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
- USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
- USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
+ USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+ USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+ USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
+ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
- if(cfg.Sof_enable)
+ if (cfg.Sof_enable != 0U)
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
}
- if (cfg.vbus_sensing_enable == ENABLE)
+ if (cfg.vbus_sensing_enable == 1U)
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
}
- return HAL_OK;
+ return ret;
}
-
/**
* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
* @param USBx Selected device
@@ -346,15 +459,15 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
15 means Flush all Tx FIFOs
* @retval HAL status
*/
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
- uint32_t count = 0;
+ uint32_t count = 0U;
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
+ USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
do
{
- if (++count > 200000)
+ if (++count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -364,7 +477,6 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
return HAL_OK;
}
-
/**
* @brief USB_FlushRxFifo : Flush Rx FIFO
* @param USBx Selected device
@@ -378,7 +490,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
do
{
- if (++count > 200000)
+ if (++count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -389,7 +501,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
}
/**
- * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
+ * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
* depending the PHY type and the enumeration speed of the device.
* @param USBx Selected device
* @param speed device speed
@@ -397,40 +509,42 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
USBx_DEVICE->DCFG |= speed;
return HAL_OK;
}
/**
- * @brief USB_GetDevSpeed :Return the Dev Speed
+ * @brief USB_GetDevSpeed Return the Dev Speed
* @param USBx Selected device
- * @retval speed : device speed
+ * @retval speed device speed
* This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @arg PCD_SPEED_HIGH: High speed mode
+ * @arg PCD_SPEED_FULL: Full speed mode
*/
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
- uint8_t speed = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint8_t speed;
+ uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+ if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
{
- speed = USB_OTG_SPEED_HIGH;
+ speed = USBD_HS_SPEED;
}
- else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
- ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
+ else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+ (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
- speed = USB_OTG_SPEED_FULL;
+ speed = USBD_FS_SPEED;
}
- else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+ else
{
- speed = USB_OTG_SPEED_LOW;
+ speed = 0xFU;
}
return speed;
@@ -444,28 +558,36 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
if (ep->is_in == 1U)
{
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
{
- USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
- ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
}
}
else
{
- USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
+ USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
{
- USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
- (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DOEPCTL_USBAEP;
}
}
return HAL_OK;
}
+
/**
* @brief Activate and configure a dedicated endpoint
* @param USBx Selected device
@@ -474,41 +596,37 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
*/
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
- static __IO uint32_t debug = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+ if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
{
- USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
- ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_USBAEP;
}
-
- debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
- ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
}
else
{
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+ if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
{
- USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
- ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
-
- debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0U)*USB_OTG_EP_REG_SIZE);
- debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
- debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
- ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
+ USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+ ((uint32_t)ep->type << 18) | (epnum << 22) |
+ USB_OTG_DOEPCTL_USBAEP;
}
- USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
+ USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
}
return HAL_OK;
}
+
/**
* @brief De-activate and de-initialize an endpoint
* @param USBx Selected device
@@ -517,66 +635,30 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
- uint32_t count = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
- /* Disable the IN endpoint */
+ /* Read DEPCTLn register */
if (ep->is_in == 1U)
{
- USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
-
- /* sets the NAK bit for the IN endpoint */
- USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
-
- /* Disable IN endpoint */
- USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
-
- do
- {
- if (++count > 200000U)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /*Wait for EPDISD endpoint disabled interrupt*/
- while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
-
-
- /* Flush any data remaining in the TxFIFO */
- USB_FlushTxFifo(USBx , 0x10U);
-
- /* Disable endpoint interrupts */
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
-
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+ USB_OTG_DIEPCTL_MPSIZ |
+ USB_OTG_DIEPCTL_TXFNUM |
+ USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DIEPCTL_EPTYP);
}
- else /* Disable the OUT endpoint */
+ else
{
-
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
-
- /* sets the NAK bit for the OUT endpoint */
- USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
-
- /* Disable OUT endpoint */
- USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
-
- do
- {
- if (++count > 200000U)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /*Wait for EPDISD endpoint disabled interrupt*/
- while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
-
- /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
-
- /* Disable endpoint interrupts */
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
+ USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+ USB_OTG_DOEPCTL_MPSIZ |
+ USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+ USB_OTG_DOEPCTL_EPTYP);
}
+
return HAL_OK;
}
@@ -588,68 +670,22 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
*/
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
- uint32_t count = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
- /* Disable the IN endpoint */
+ /* Read DEPCTLn register */
if (ep->is_in == 1U)
{
- USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_USBAEP;
-
- /* sets the NAK bit for the IN endpoint */
- USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
-
- /* Disable IN endpoint */
- USBx_INEP(ep->num)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS;
-
- do
- {
- if (++count > 200000U)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /*Wait for EPDISD endpoint disabled interrupt*/
- while ((USBx_INEP(ep->num)->DIEPINT & USB_OTG_DIEPCTL_EPDIS) == USB_OTG_DIEPCTL_EPDIS);
-
-
- /* Flush any data remaining in the TxFIFO */
- USB_FlushTxFifo(USBx , 0x10U);
-
- /* Disable endpoint interrupts */
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
-
+ USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
- else /* Disable the OUT endpoint */
+ else
{
-
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
-
- /* sets the NAK bit for the OUT endpoint */
- USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
-
- /* Disable OUT endpoint */
- USBx_OUTEP(ep->num)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS;
-
- do
- {
- if (++count > 200000U)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /*Wait for EPDISD endpoint disabled interrupt*/
- while ((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS);
-
- /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
-
- /* Disable endpoint interrupts */
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -662,9 +698,11 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
{
- uint16_t pktcnt = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+ uint16_t pktcnt;
/* IN endpoint */
if (ep->is_in == 1U)
@@ -672,9 +710,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
}
else
{
@@ -683,52 +721,66 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
if (ep->type == EP_TYPE_ISOC)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U));
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
}
}
if (dma == 1U)
{
- USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+
+ if (ep->type == EP_TYPE_ISOC)
+ {
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
if (ep->type != EP_TYPE_ISOC)
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1U << ep->num;
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
- }
-
- if (ep->type == EP_TYPE_ISOC)
- {
- if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
- {
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
- }
else
{
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
- }
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+ }
+ else
+ {
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+ }
- if (ep->type == EP_TYPE_ISOC)
- {
- USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
+ (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+ }
}
}
else /* OUT endpoint */
@@ -737,40 +789,44 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* pktcnt = N
* xfersize = N * maxpacket
*/
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
if (ep->xfer_len == 0U)
{
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
}
else
{
- pktcnt = (ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket;
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
+ pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
}
if (dma == 1U)
{
- USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
}
if (ep->type == EP_TYPE_ISOC)
{
- if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
+ if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
{
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
}
else
{
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
}
}
/* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
}
+
return HAL_OK;
}
@@ -784,17 +840,20 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
/* IN endpoint */
if (ep->is_in == 1U)
{
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
}
else
{
@@ -803,61 +862,68 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
- if(ep->xfer_len > ep->maxpacket)
+ if (ep->xfer_len > ep->maxpacket)
{
ep->xfer_len = ep->maxpacket;
}
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+ USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
}
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
- if (dma == 1)
+ if (dma == 1U)
{
- USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ if ((uint32_t)ep->dma_addr != 0U)
+ {
+ USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else
{
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
+ USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
}
}
}
-
else /* OUT endpoint */
{
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
*/
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
if (ep->xfer_len > 0U)
{
ep->xfer_len = ep->maxpacket;
}
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
if (dma == 1U)
{
- USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ if ((uint32_t)ep->xfer_buff != 0U)
+ {
+ USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+ }
}
/* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
}
+
return HAL_OK;
}
@@ -876,43 +942,44 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
*/
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{
- uint32_t count32b = 0U , i = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t *pSrc = (uint32_t *)src;
+ uint32_t count32b, i;
if (dma == 0U)
{
- count32b = (len + 3U) / 4U;
- for (i = 0U; i < count32b; i++, src += 4U)
+ count32b = ((uint32_t)len + 3U) / 4U;
+ for (i = 0U; i < count32b; i++)
{
- USBx_DFIFO(ch_ep_num) = __UNALIGNED_UINT32_READ(src);
+ USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+ pSrc++;
}
}
+
return HAL_OK;
}
/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
- * with the EP/channel
+ * @brief USB_ReadPacket : read a packet from the RX FIFO
* @param USBx Selected device
- * @param src source pointer
- * @param ch_ep_num endpoint or host channel number
+ * @param dest source pointer
* @param len Number of bytes to read
- * @param dma USB dma enabled or disabled
- * This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
- uint32_t i=0U;
- uint32_t count32b = (len + 3U) / 4U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t *pDest = (uint32_t *)dest;
+ uint32_t i;
+ uint32_t count32b = ((uint32_t)len + 3U) / 4U;
- for ( i = 0U; i < count32b; i++, dest += 4U )
+ for (i = 0U; i < count32b; i++)
{
- __UNALIGNED_UINT32_WRITE(dest, USBx_DFIFO(0U));
-
+ __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+ pDest++;
}
- return ((void *)dest);
+
+ return ((void *)pDest);
}
/**
@@ -921,28 +988,31 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
if (ep->is_in == 1U)
{
- if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0U)
+ if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
{
- USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+ USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
}
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
}
else
{
- if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U)
+ if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
{
- USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+ USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
}
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
}
+
return HAL_OK;
}
-
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
* @param USBx Selected device
@@ -951,20 +1021,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef
*/
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t epnum = (uint32_t)ep->num;
+
if (ep->is_in == 1U)
{
- USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+ USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
{
- USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
}
}
else
{
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
- if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+ USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+ if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
{
- USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+ USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
}
}
return HAL_OK;
@@ -977,15 +1050,16 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
*/
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
{
+ HAL_StatusTypeDef ret;
+ uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
/* Clear Pending interrupt */
- for (i = 0U; i < 15U ; i++)
+ for (i = 0U; i < 15U; i++)
{
- USBx_INEP(i)->DIEPINT = 0xFFU;
- USBx_OUTEP(i)->DOEPINT = 0xFFU;
+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
}
- USBx_DEVICE->DAINT = 0xFFFFFFFFU;
/* Clear interrupt masks */
USBx_DEVICE->DIEPMSK = 0U;
@@ -993,10 +1067,19 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
USBx_DEVICE->DAINTMSK = 0U;
/* Flush the FIFO */
- USB_FlushRxFifo(USBx);
- USB_FlushTxFifo(USBx , 0x10U);
+ ret = USB_FlushRxFifo(USBx);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
- return HAL_OK;
+ ret = USB_FlushTxFifo(USBx, 0x10U);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
+
+ return ret;
}
/**
@@ -1006,10 +1089,12 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
- USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
- USBx_DEVICE->DCFG |= (address << 4U) & USB_OTG_DCFG_DAD ;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+ USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
return HAL_OK;
}
@@ -1019,9 +1104,11 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
{
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
HAL_Delay(3U);
return HAL_OK;
@@ -1032,9 +1119,11 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
{
- USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
HAL_Delay(3U);
return HAL_OK;
@@ -1045,13 +1134,14 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t v = 0U;
+ uint32_t tmpreg;
- v = USBx->GINTSTS;
- v &= USBx->GINTMSK;
- return v;
+ tmpreg = USBx->GINTSTS;
+ tmpreg &= USBx->GINTMSK;
+
+ return tmpreg;
}
/**
@@ -1059,12 +1149,15 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t v;
- v = USBx_DEVICE->DAINT;
- v &= USBx_DEVICE->DAINTMSK;
- return ((v & 0xffff0000U) >> 16U);
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_DEVICE->DAINT;
+ tmpreg &= USBx_DEVICE->DAINTMSK;
+
+ return ((tmpreg & 0xffff0000U) >> 16);
}
/**
@@ -1072,12 +1165,15 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval HAL status
*/
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
- uint32_t v;
- v = USBx_DEVICE->DAINT;
- v &= USBx_DEVICE->DAINTMSK;
- return ((v & 0xFFFFU));
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_DEVICE->DAINT;
+ tmpreg &= USBx_DEVICE->DAINTMSK;
+
+ return ((tmpreg & 0xFFFFU));
}
/**
@@ -1087,12 +1183,15 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
- uint32_t v;
- v = USBx_OUTEP(epnum)->DOEPINT;
- v &= USBx_DEVICE->DOEPMSK;
- return v;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg;
+
+ tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+ tmpreg &= USBx_DEVICE->DOEPMSK;
+
+ return tmpreg;
}
/**
@@ -1102,15 +1201,17 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
- uint32_t v, msk, emp;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t tmpreg, msk, emp;
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
- msk |= ((emp >> epnum) & 0x1U) << 7U;
- v = USBx_INEP(epnum)->DIEPINT & msk;
- return v;
+ msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+ tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+ return tmpreg;
}
/**
@@ -1119,7 +1220,7 @@ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
* @param interrupt interrupt flag
* @retval None
*/
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
{
USBx->GINTSTS |= interrupt;
}
@@ -1134,21 +1235,22 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
*/
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
{
- return ((USBx->GINTSTS ) & 0x1U);
+ return ((USBx->GINTSTS) & 0x1U);
}
-
/**
* @brief Activate EP0 for Setup transactions
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
/* Set the MPS of the IN EP based on the enumeration speed */
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
- if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
{
USBx_INEP(0U)->DIEPCTL |= 3U;
}
@@ -1157,7 +1259,6 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
return HAL_OK;
}
-
/**
* @brief Prepare the EP0 to start the first control setup
* @param USBx Selected device
@@ -1170,8 +1271,19 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+ if (gSNPSiD > USB_OTG_CORE_ID_300A)
+ {
+ if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+ {
+ return HAL_OK;
+ }
+ }
+
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
- USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)) ;
+ USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
@@ -1179,13 +1291,12 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin
{
USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
/* EP enable */
- USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;
+ USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
}
return HAL_OK;
}
-
/**
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
@@ -1221,7 +1332,6 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
return HAL_OK;
}
-
/**
* @brief USB_HostInit : Initializes the USB OTG controller registers
* for Host mode
@@ -1230,37 +1340,53 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
- /* Activate VBUS Sensing B */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
- USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* Disable HW VBUS sensing */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
#else
- USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
- USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
+ /*
+ * Disable HW VBUS sensing. VBUS is internally considered to be always
+ * at VBUS-Valid level (5V).
+ */
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ /* Disable Battery chargin detector */
+ USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
- /* Disable the FS/LS support mode only */
- if((cfg.speed == USB_OTG_SPEED_FULL)&&
- (USBx != USB_OTG_FS))
+ if ((USBx->CID & (0x1U << 8)) != 0U)
{
- USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ if (cfg.speed == USB_OTG_SPEED_FULL)
+ {
+ /* Force Device Enumeration to FS/LS mode only */
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ }
+ else
+ {
+ /* Set default Max speed support */
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ }
}
else
{
+ /* Set default Max speed support */
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
}
/* Make sure the FIFOs are flushed. */
- USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
- USB_FlushRxFifo(USBx);
+ (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+ (void)USB_FlushRxFifo(USBx);
/* Clear all pending HC Interrupts */
for (i = 0U; i < cfg.Host_channels; i++)
@@ -1270,7 +1396,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
}
/* Enable VBUS driving */
- USB_DriveVbus(USBx, 1U);
+ (void)USB_DriveVbus(USBx, 1U);
HAL_Delay(200U);
@@ -1280,30 +1406,30 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFFU;
- if(USBx == USB_OTG_FS)
+ if ((USBx->CID & (0x1U << 8)) != 0U)
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = 0x80U;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16U)& USB_OTG_NPTXFD) | 0x80U);
- USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+ USBx->GRXFSIZ = 0x200U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+ USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
}
else
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = 0x200U;
- USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16U)& USB_OTG_NPTXFD) | 0x200U);
- USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+ USBx->GRXFSIZ = 0x80U;
+ USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+ USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
}
/* Enable the common interrupts */
- if (cfg.dma_enable == DISABLE)
+ if (cfg.dma_enable == 0U)
{
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
}
/* Enable interrupts matching to the Host mode ONLY */
- USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
- USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
+ USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
return HAL_OK;
@@ -1319,19 +1445,26 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
- USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
+ USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
- if (freq == HCFG_48_MHZ)
+ if (freq == HCFG_48_MHZ)
{
USBx_HOST->HFIR = 48000U;
}
- else if (freq == HCFG_6_MHZ)
+ else if (freq == HCFG_6_MHZ)
{
USBx_HOST->HFIR = 6000U;
}
+ else
+ {
+ /* ... */
+ }
+
return HAL_OK;
}
@@ -1339,21 +1472,25 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq
* @brief USB_OTG_ResetPort : Reset Host Port
* @param USBx Selected device
* @retval HAL status
- * @note (1)The application must wait at least 10 ms
+ * @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
{
- __IO uint32_t hprt0;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ __IO uint32_t hprt0 = 0U;
hprt0 = USBx_HPRT0;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
- HAL_Delay (10U); /* See Note #1 */
+ HAL_Delay(100U); /* See Note #1 */
USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+ HAL_Delay(10U);
+
return HAL_OK;
}
@@ -1365,13 +1502,15 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* 1 : VBUS Inactive
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
- __IO uint32_t hprt0;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ __IO uint32_t hprt0 = 0U;
hprt0 = USBx_HPRT0;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+
+ hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
{
@@ -1389,16 +1528,17 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @param USBx Selected device
* @retval speed : Host speed
* This parameter can be one of these values:
- * @arg USB_OTG_SPEED_HIGH: High speed mode
- * @arg USB_OTG_SPEED_FULL: Full speed mode
- * @arg USB_OTG_SPEED_LOW: Low speed mode
+ * @arg HCD_SPEED_HIGH: High speed mode
+ * @arg HCD_SPEED_FULL: Full speed mode
+ * @arg HCD_SPEED_LOW: Low speed mode
*/
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
{
- __IO uint32_t hprt0;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ __IO uint32_t hprt0 = 0U;
hprt0 = USBx_HPRT0;
- return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17U);
+ return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
}
/**
@@ -1406,8 +1546,10 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
* @param USBx Selected device
* @retval current frame number
*/
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
}
@@ -1443,86 +1585,107 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ep_type,
uint16_t mps)
{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t HCcharEpDir, HCcharLowSpeed;
/* Clear old interrupt conditions for this host channel. */
- USBx_HC(ch_num)->HCINT = 0xFFFFFFFFU;
+ USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
/* Enable channel interrupts required for this transfer. */
switch (ep_type)
{
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
-
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_NAKM ;
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_NAKM;
- if (epnum & 0x80U)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- else
- {
- if(USBx != USB_OTG_FS)
+ if ((epnum & 0x80U) == 0x80U)
{
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+ }
+ else
+ {
+ if ((USBx->CID & (0x1U << 8)) != 0U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ }
+ }
+ break;
+
+ case EP_TYPE_INTR:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_STALLM |
+ USB_OTG_HCINTMSK_TXERRM |
+ USB_OTG_HCINTMSK_DTERRM |
+ USB_OTG_HCINTMSK_NAKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
+
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
}
- }
- break;
-
- case EP_TYPE_INTR:
-
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_STALLM |\
- USB_OTG_HCINTMSK_TXERRM |\
- USB_OTG_HCINTMSK_DTERRM |\
- USB_OTG_HCINTMSK_NAKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
- if (epnum & 0x80U)
- {
- USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
+ break;
- break;
- case EP_TYPE_ISOC:
+ case EP_TYPE_ISOC:
+ USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
+ USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_AHBERR |
+ USB_OTG_HCINTMSK_FRMORM;
- USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
- USB_OTG_HCINTMSK_ACKM |\
- USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+ }
+ break;
- if (epnum & 0x80U)
- {
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
- }
- break;
+ default:
+ ret = HAL_ERROR;
+ break;
}
/* Enable the top level host channel interrupt. */
- USBx_HOST->HAINTMSK |= (1 << ch_num);
+ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
/* Make sure host channel interrupts are enabled. */
USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
/* Program the HCCHAR register */
- USBx_HC(ch_num)->HCCHAR = (((dev_address << 22U) & USB_OTG_HCCHAR_DAD) |\
- (((epnum & 0x7FU)<< 11U) & USB_OTG_HCCHAR_EPNUM)|\
- ((((epnum & 0x80U) == 0x80U)<< 15U) & USB_OTG_HCCHAR_EPDIR)|\
- (((speed == USB_OTG_SPEED_LOW)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
- ((ep_type << 18U) & USB_OTG_HCCHAR_EPTYP)|\
- (mps & USB_OTG_HCCHAR_MPSIZ));
+ if ((epnum & 0x80U) == 0x80U)
+ {
+ HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+ }
+ else
+ {
+ HCcharEpDir = 0U;
+ }
+
+ if (speed == HPRT0_PRTSPD_LOW_SPEED)
+ {
+ HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+ }
+ else
+ {
+ HCcharLowSpeed = 0U;
+ }
+
+ USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+ ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+ (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+ ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
if (ep_type == EP_TYPE_INTR)
{
- USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+ USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
}
- return HAL_OK;
+ return ret;
}
/**
@@ -1535,111 +1698,123 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
* 1 : DMA feature used
* @retval HAL state
*/
-#if defined (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
{
- uint8_t is_oddframe = 0;
- uint16_t len_words = 0;
- uint16_t num_packets = 0;
- uint16_t max_hc_pkt_count = 256;
- uint32_t tmpreg = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t ch_num = (uint32_t)hc->ch_num;
+ static __IO uint32_t tmpreg = 0U;
+ uint8_t is_oddframe;
+ uint16_t len_words;
+ uint16_t num_packets;
+ uint16_t max_hc_pkt_count = 256U;
- if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
+ if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
{
- if((dma == 0) && (hc->do_ping == 1U))
+ if ((dma == 0U) && (hc->do_ping == 1U))
{
- USB_DoPing(USBx, hc->ch_num);
+ (void)USB_DoPing(USBx, hc->ch_num);
return HAL_OK;
}
- else if(dma == 1)
+ else if (dma == 1U)
{
- USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+ USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
hc->do_ping = 0U;
}
+ else
+ {
+ /* ... */
+ }
}
/* Compute the expected number of packets associated to the transfer */
if (hc->xfer_len > 0U)
{
- num_packets = (hc->xfer_len + hc->max_packet - 1U) / hc->max_packet;
+ num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
if (num_packets > max_hc_pkt_count)
{
num_packets = max_hc_pkt_count;
- hc->xfer_len = num_packets * hc->max_packet;
+ hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
}
}
else
{
- num_packets = 1;
+ num_packets = 1U;
}
- if (hc->ep_is_in)
+ if (hc->ep_is_in != 0U)
{
- hc->xfer_len = num_packets * hc->max_packet;
+ hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
}
/* Initialize the HCTSIZn register */
- USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
- ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
- (((hc->data_pid) << 29U) & USB_OTG_HCTSIZ_DPID);
+ USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+ (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+ (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
- if (dma)
+ if (dma != 0U)
{
/* xfer_buff MUST be 32-bits aligned */
- USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+ USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
}
- is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
- USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
- USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
+ is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+ USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+ USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
/* Set host channel enable */
- tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+ tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+ /* make sure to set the correct ep direction */
+ if (hc->ep_is_in != 0U)
+ {
+ tmpreg |= USB_OTG_HCCHAR_EPDIR;
+ }
+ else
+ {
+ tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+ }
tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
+ USBx_HC(ch_num)->HCCHAR = tmpreg;
- if (dma == 0) /* Slave mode */
+ if (dma == 0U) /* Slave mode */
{
- if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
{
- switch(hc->ep_type)
+ switch (hc->ep_type)
{
/* Non periodic transfer */
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
- len_words = (hc->xfer_len + 3) / 4;
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+ {
+ /* need to process data in nptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+ }
+ break;
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx->HNPTXSTS & 0xFFFF))
- {
- /* need to process data in nptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
- }
- break;
/* Periodic transfer */
- case EP_TYPE_INTR:
- case EP_TYPE_ISOC:
- len_words = (hc->xfer_len + 3) / 4;
- /* check if there is enough space in FIFO space */
- if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
- {
- /* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
- }
- break;
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+ /* check if there is enough space in FIFO space */
+ if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+ {
+ /* need to process data in ptxfempty interrupt */
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ }
+ break;
- default:
- break;
+ default:
+ break;
}
/* Write packet into the Tx FIFO. */
- USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+ (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
}
}
@@ -1651,8 +1826,10 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
return ((USBx_HOST->HAINT) & 0xFFFFU);
}
@@ -1663,20 +1840,23 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t hcnum = (uint32_t)hc_num;
uint32_t count = 0U;
+ uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
/* Check for space in the request queue to issue the halt. */
- if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || (((((USBx_HC(hc_num)->HCCHAR) &
- USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
+ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
- if ((USBx->HNPTXSTS & 0xFF0000U) == 0U)
+ if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
{
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1684,21 +1864,22 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
break;
}
}
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
}
else
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
- if ((USBx_HOST->HPTXSTS & 0xFFFFU) == 0U)
+ if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
{
- USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{
if (++count > 1000U)
@@ -1706,11 +1887,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
break;
}
}
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
}
@@ -1724,19 +1905,21 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
- uint8_t num_packets = 1U;
- uint32_t tmpreg = 0U;
+ uint32_t USBx_BASE = (uint32_t)USBx;
+ uint32_t chnum = (uint32_t)ch_num;
+ uint32_t num_packets = 1U;
+ uint32_t tmpreg;
- USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
- USB_OTG_HCTSIZ_DOPING;
+ USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+ USB_OTG_HCTSIZ_DOPING;
/* Set host channel enable */
- tmpreg = USBx_HC(ch_num)->HCCHAR;
+ tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(ch_num)->HCCHAR = tmpreg;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
return HAL_OK;
}
@@ -1748,21 +1931,22 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
{
- uint8_t i;
+ uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t count = 0U;
uint32_t value;
+ uint32_t i;
+
- USB_DisableGlobalInt(USBx);
+ (void)USB_DisableGlobalInt(USBx);
- /* Flush FIFO */
- USB_FlushTxFifo(USBx, 0x10U);
- USB_FlushRxFifo(USBx);
+ /* Flush FIFO */
+ (void)USB_FlushTxFifo(USBx, 0x10U);
+ (void)USB_FlushRxFifo(USBx);
/* Flush out any leftover queued requests. */
- for (i = 0; i <= 15; i++)
+ for (i = 0U; i <= 15U; i++)
{
-
- value = USBx_HC(i)->HCCHAR ;
+ value = USBx_HC(i)->HCCHAR;
value |= USB_OTG_HCCHAR_CHDIS;
value &= ~USB_OTG_HCCHAR_CHENA;
value &= ~USB_OTG_HCCHAR_EPDIR;
@@ -1770,15 +1954,14 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
}
/* Halt all channels to put them into a known state. */
- for (i = 0; i <= 15; i++)
+ for (i = 0U; i <= 15U; i++)
{
- value = USBx_HC(i)->HCCHAR ;
-
+ value = USBx_HC(i)->HCCHAR;
value |= USB_OTG_HCCHAR_CHDIS;
value |= USB_OTG_HCCHAR_CHENA;
value &= ~USB_OTG_HCCHAR_EPDIR;
-
USBx_HC(i)->HCCHAR = value;
+
do
{
if (++count > 1000U)
@@ -1792,16 +1975,55 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = 0xFFFFFFFFU;
USBx->GINTSTS = 0xFFFFFFFFU;
- USB_EnableGlobalInt(USBx);
+ (void)USB_EnableGlobalInt(USBx);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+ {
+ /* active Remote wakeup signalling */
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+ uint32_t USBx_BASE = (uint32_t)USBx;
+
+ /* active Remote wakeup signalling */
+ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
return HAL_OK;
}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
- STM32F412Vx || STM32F412Cx || STM32F413xx || STM32F423xx */
-#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
/**
* @}
diff --git a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_utils.c b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_utils.c
index a9b0ba397777bedfc664cbfd688d384435d52c27..f7ca91a163506aa893a96d3090a5e15a3ccd41bd 100644
--- a/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_utils.c
+++ b/stm32cube/stm32f4xx/drivers/src/stm32f4xx_ll_utils.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2017 STMicroelectronics
+ * © Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/stm32cube/stm32f4xx/soc/stm32f401xc.h b/stm32cube/stm32f4xx/soc/stm32f401xc.h
index e72dd1ebe5d1f8a18541565e4dc29107ffe87ee9..3cd47b4f49c46b266e3c66a5dadfd09eac50f85f 100644
--- a/stm32cube/stm32f4xx/soc/stm32f401xc.h
+++ b/stm32cube/stm32f4xx/soc/stm32f401xc.h
@@ -649,15 +649,15 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
-#define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */
-#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */
-#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
-#define FLASH_END 0x0803FFFFU /*!< FLASH end address */
-#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
-#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000UL /*!< SRAM1(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0803FFFFUL /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -665,96 +665,96 @@ typedef struct
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
-#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
+#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
/* Legacy define */
#define ADC_BASE ADC1_COMMON_BASE
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
/*!< Debug MCU registers base address */
-#define DBGMCU_BASE 0xE0042000U
+#define DBGMCU_BASE 0xE0042000UL
/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE 0x50000000U
-
-#define USB_OTG_GLOBAL_BASE 0x000U
-#define USB_OTG_DEVICE_BASE 0x800U
-#define USB_OTG_IN_ENDPOINT_BASE 0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
-#define USB_OTG_EP_REG_SIZE 0x20U
-#define USB_OTG_HOST_BASE 0x400U
-#define USB_OTG_HOST_PORT_BASE 0x440U
-#define USB_OTG_HOST_CHANNEL_BASE 0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
-#define USB_OTG_PCGCCTL_BASE 0xE00U
-#define USB_OTG_FIFO_BASE 0x1000U
-#define USB_OTG_FIFO_SIZE 0x1000U
-
-#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
-#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE 0x000UL
+#define USB_OTG_DEVICE_BASE 0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
+#define USB_OTG_EP_REG_SIZE 0x20UL
+#define USB_OTG_HOST_BASE 0x400UL
+#define USB_OTG_HOST_PORT_BASE 0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
+#define USB_OTG_PCGCCTL_BASE 0xE00UL
+#define USB_OTG_FIFO_BASE 0x1000UL
+#define USB_OTG_FIFO_SIZE 0x1000UL
+
+#define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */
/**
* @}
*/
@@ -847,502 +847,502 @@ typedef struct
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
-#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
#define ADC_SR_AWD ADC_SR_AWD_Msk /*!