diff --git a/stm32cube/stm32f3xx/README b/stm32cube/stm32f3xx/README index 656f148ed1895e05aa387482bfa9610fc2b21c4f..88c8136d4e4362f5b8f5816502df2f66484d851e 100644 --- a/stm32cube/stm32f3xx/README +++ b/stm32cube/stm32f3xx/README @@ -1 +1,5 @@ -The current version supported in Zephyr for STM32F3 Cube is V1.6.0 +The current version supported in Zephyr for STM32F3 Cube is V1.7.0 + +Changes from official delivery: +*dos2unix applied +*trailing white spaces removed diff --git a/stm32cube/stm32f3xx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32f3xx/drivers/include/Legacy/stm32_hal_legacy.h index 44c7f544f983a04b9fb0481eaecce70fc089e29a..c6312e950b81a6ee15db0d8c9abe3f79e41abb6b 100644 --- a/stm32cube/stm32f3xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32f3xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -138,6 +138,7 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -240,9 +241,9 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -355,6 +356,7 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 + /** * @} */ @@ -852,6 +854,8 @@ #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 +#define __DIV_LPUART UART_DIV_LPUART + #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK @@ -913,48 +917,48 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) - -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} @@ -2227,26 +2231,26 @@ #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET @@ -2648,10 +2652,22 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY -#if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE -#define RCC_IT_CSS RCC_IT_CSSHSE -#endif +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG @@ -2768,11 +2784,14 @@ #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32_assert_template.h b/stm32cube/stm32f3xx/drivers/include/stm32_assert_template.h index 1bba96ae0211900168e655fcc3c48b4138099b26..41d484da458641ac282694caf44127b4fc098d31 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32_assert_template.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32_assert_template.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_assert.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief STM32 assert template file. * This file should be copied to the application folder and renamed * to stm32_assert.h. diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal.h index 462488052fc09b140c9fc5ab162c116792070299..d68f1a10456f892daf1f1c9d3698875497a4f9fd 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -80,9 +80,9 @@ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- CFGR2 Register ---*/ /* Alias word address of BYP_ADDR_PAR bit */ -#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18) +#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U) #define BYPADDRPAR_BitNumber 0x04 -#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4)) +#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U)) /** * @} */ @@ -96,54 +96,54 @@ * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices) * @{ */ -#define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) - 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */ -#define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap - 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */ -#define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap - 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */ -#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) - 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */ -#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) - 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */ -#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) - 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ -#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) - 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ +#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) + 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4U) */ +#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6U) */ +#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7U) */ +#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) + 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3U) */ +#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) + 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4U) */ +#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only) + 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */ +#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only) + 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */ #if defined(SYSCFG_CFGR3_DMA_RMP) #if !defined(HAL_REMAP_CFGR3_MASK) -#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000) +#define HAL_REMAP_CFGR3_MASK (0x01000000U) #endif -#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) - 11: Map on DMA1 channel 2 */ -#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) - 01: Map on DMA1 channel 4 */ -#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) - 10: Map on DMA1 channel 6 */ -#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) - 11: Map on DMA1 channel 3 */ -#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) - 01: Map on DMA1 channel 5 */ -#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) - 10: Map on DMA1 channel 7 */ -#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) - 11: Map on DMA1 channel 7 */ -#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) - 01: Map on DMA1 channel 3 */ -#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) - 10: Map on DMA1 channel 5 */ -#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) - 11: Map on DMA1 channel 6 */ -#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) - 01: Map on DMA1 channel 2 */ -#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) - 10: Map on DMA1 channel 4 */ -#define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap +#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) + 11: Map on DMA1 channel 2U */ +#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) + 01: Map on DMA1 channel 4U */ +#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only) + 10: Map on DMA1 channel 6U */ +#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) + 11: Map on DMA1 channel 3U */ +#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) + 01: Map on DMA1 channel 5U */ +#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only) + 10: Map on DMA1 channel 7U */ +#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) + 11: Map on DMA1 channel 7U */ +#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) + 01: Map on DMA1 channel 3U */ +#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only) + 10: Map on DMA1 channel 5U */ +#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) + 11: Map on DMA1 channel 6U */ +#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) + 01: Map on DMA1 channel 2U */ +#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only) + 10: Map on DMA1 channel 4U */ +#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap x0: No remap (ADC2 on DMA2) - 10: Map on DMA1 channel 2 */ -#define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap - 11: Map on DMA1 channel 4 */ + 10: Map on DMA1 channel 2U */ +#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap + 11: Map on DMA1 channel 4U */ #endif /* SYSCFG_CFGR3_DMA_RMP */ #if defined(SYSCFG_CFGR3_DMA_RMP) @@ -190,20 +190,20 @@ * - 01: CFGR3 register in SYSCFG * @{ */ -#define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) +#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) 0: No remap (DAC trigger is TIM8_TRGO) 1: Remap (DAC trigger is TIM3_TRGO) */ -#define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap +#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap 0: No remap 1: Remap (TIM1_TRG3 = TIM17_OC) */ #if defined(SYSCFG_CFGR3_TRIGGER_RMP) #if !defined(HAL_REMAP_CFGR3_MASK) -#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000) +#define HAL_REMAP_CFGR3_MASK (0x01000000U) #endif -#define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap +#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 0: Remap (DAC trigger is TIM15_TRGO) 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */ -#define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap +#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 0: No remap 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */ #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ @@ -241,7 +241,7 @@ 0: No remap (TIM2_CC1) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 - 0: No remap (EXTI line 15) + 0: No remap (EXTI line 15U) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 0: No remap (TIM3_CC1) @@ -250,11 +250,11 @@ #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13)) + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U)) /** * @} */ @@ -283,13 +283,13 @@ 0: No remap (TIM2_CC1) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 - 0: No remap (EXTI line 15) + 0: No remap (EXTI line 15U) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 0: No remap (TIM3_CC1) 1: Remap (TIM20_CC4) */ #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5 - 0: No remap (EXTI line 2) + 0: No remap (EXTI line 2U) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6 0: No remap (TIM4_CC1) @@ -310,17 +310,17 @@ #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15U) == HAL_REMAPADCTRIGGER_ADC34_EXT15U) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \ - (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14)) + (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11U) == HAL_REMAPADCTRIGGER_ADC34_JEXT11U) || \ + (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14U) == HAL_REMAPADCTRIGGER_ADC34_JEXT14U)) /** * @} */ @@ -356,34 +356,34 @@ /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection * @{ */ -#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */ -#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */ -#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */ -#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */ +#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0U */ +#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1U */ +#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2U */ +#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3U */ #if defined(SYSCFG_RCR_PAGE4) /* More than 4KB CCM-SRAM defined */ -#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */ -#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */ -#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */ -#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */ +#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4U */ +#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5U */ +#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6U */ +#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7U */ #endif /* SYSCFG_RCR_PAGE4 */ #if defined(SYSCFG_RCR_PAGE8) -#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */ -#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */ -#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */ -#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */ -#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */ -#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */ -#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */ -#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */ +#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8U */ +#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9U */ +#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10U) /*!< ICODE SRAM Write protection page 10U */ +#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11U) /*!< ICODE SRAM Write protection page 11U */ +#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12U) /*!< ICODE SRAM Write protection page 12U */ +#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13U) /*!< ICODE SRAM Write protection page 13U */ +#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14U) /*!< ICODE SRAM Write protection page 14U */ +#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15U) /*!< ICODE SRAM Write protection page 15U */ #endif /* SYSCFG_RCR_PAGE8 */ #if defined(SYSCFG_RCR_PAGE8) -#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF)) +#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU)) #elif defined(SYSCFG_RCR_PAGE4) -#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF)) +#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU)) #else -#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F)) +#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU)) #endif /* SYSCFG_RCR_PAGE8 */ /** * @} @@ -571,7 +571,7 @@ */ #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) @@ -579,13 +579,13 @@ */ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ #if defined(SYSCFG_CFGR1_MEM_MODE_2) #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_2 */ /** * @} @@ -605,7 +605,7 @@ */ #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */ #if defined(SYSCFG_CFGR1_ENCODER_MODE_1) @@ -613,7 +613,7 @@ */ #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */ #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1) @@ -621,7 +621,7 @@ */ #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */ /** * @} @@ -638,22 +638,22 @@ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \ - }while(0) + }while(0U) #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \ - }while(0) + }while(0U) #elif defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping */ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 |= (__DMA_REMAP__); \ - }while(0) + }while(0U) #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */ /** * @} @@ -668,11 +668,11 @@ */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) + }while(0U) #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) + }while(0U) /** * @} */ @@ -685,11 +685,11 @@ */ #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ SYSCFG->CFGR1 |= (__INTERRUPT__); \ - }while(0) + }while(0U) #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ SYSCFG->CFGR1 &= ~(__INTERRUPT__); \ - }while(0) + }while(0U) /** * @} */ @@ -730,7 +730,7 @@ */ #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ - }while(0) + }while(0U) /** * @} */ @@ -746,7 +746,7 @@ */ #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ - }while(0) + }while(0U) /** * @} */ @@ -762,7 +762,7 @@ */ #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ - }while(0) + }while(0U) /** * @} */ @@ -779,22 +779,22 @@ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \ - }while(0) + }while(0U) #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \ - }while(0) + }while(0U) #else /** @brief Trigger remapping enable/disable macros * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping */ #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \ - }while(0) + }while(0U) #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \ - }while(0) + }while(0U) #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ /** * @} @@ -809,10 +809,10 @@ */ #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \ - }while(0) + }while(0U) #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \ - }while(0) + }while(0U) /** * @} */ @@ -827,7 +827,7 @@ * @note Disabling the parity check on RAM locks the configuration bit. * To re-enable the parity check on RAM perform a system reset. */ -#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001) +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U) /** * @} */ @@ -843,7 +843,7 @@ */ #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \ SYSCFG->RCR |= (__PAGE_WP__); \ - }while(0) + }while(0U) /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc.h index 85960599956d1e76bc9af21abcec9bbacfbf4c1c..b8b7ccade11da58278fd83e5b476c30fb071ccd4 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -71,36 +71,36 @@ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, +#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, +#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc_ex.h index ad29f11f3931d24d7f0df9313e66f86596ce5f7c..20a1436253fc06389ad6f14ddf733bf85339a83c 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -89,14 +89,14 @@ typedef struct Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */ uint32_t Resolution; /*!< Configures the ADC resolution. This parameter can be a value of @ref ADCEx_Resolution */ - uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0) (default setting) - or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4, if offset enabled: MSB on register bit 14 and LSB on register bit 3). + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting) + or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U). See reference manual for alignments with other resolutions. This parameter can be a value of @ref ADCEx_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADCEx_Scan_mode */ @@ -177,7 +177,7 @@ typedef struct This parameter must be a value of @ref ADCEx_SingleDifferential Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode. + Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ @@ -186,7 +186,7 @@ typedef struct Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */ uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ }ADC_ChannelConfTypeDef; @@ -228,7 +228,7 @@ typedef struct This parameter must be a value of @ref ADCEx_SingleDifferential Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode. + Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ @@ -237,8 +237,8 @@ typedef struct Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), - this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. @@ -315,11 +315,11 @@ typedef struct uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ }ADC_AnalogWDGConfTypeDef; @@ -365,17 +365,17 @@ typedef struct */ typedef struct { - uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) - or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U). This parameter can be a value of @ref ADCEx_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADCEx_Scan_mode - Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) + Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ @@ -452,8 +452,8 @@ typedef struct Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), - this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. @@ -502,7 +502,7 @@ typedef struct This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ - uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */ }ADC_AnalogWDGConfTypeDef; #endif /* STM32F373xC || STM32F378xx */ /** @@ -518,12 +518,12 @@ typedef struct /** @defgroup ADCEx_Error_Code ADC Extended Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ -#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ /** * @} */ @@ -535,22 +535,22 @@ typedef struct /** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler * @{ */ -#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated PLL */ +#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ #endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */ #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ @@ -564,7 +564,7 @@ typedef struct /** @defgroup ADCEx_Resolution ADC Extended Resolution * @{ */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ @@ -575,7 +575,7 @@ typedef struct /** @defgroup ADCEx_Data_align ADC Extended Data Alignment * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT (0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /** * @} @@ -584,8 +584,8 @@ typedef struct /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode * @{ */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) +#define ADC_SCAN_DISABLE (0x00000000U) +#define ADC_SCAN_ENABLE (0x00000001U) /** * @} */ @@ -593,7 +593,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) @@ -641,12 +641,12 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #if defined(STM32F303xE) || defined(STM32F398xx) /* ADC external triggers specific to device STM303xE: mask to differentiate */ -/* standard triggers from specific timer 20, needed for reallocation of */ -/* triggers common to ADC1&2/ADC3&4 and to avoid mixing with standard */ +/* standard triggers from specific timer 20U, needed for reallocation of */ +/* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */ /* triggers without remap. */ #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 @@ -657,8 +657,8 @@ typedef struct /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ -#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */ -#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */ +#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ +#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ /*!< External triggers of regular group for ADC3&ADC4 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ @@ -669,7 +669,7 @@ typedef struct /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ /* ADC3_4 by driver when needed. */ #define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */ - /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15) */ + /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */ #define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */ #define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */ @@ -700,11 +700,11 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #if defined(STM32F302xE) /* ADC external triggers specific to device STM302xE: mask to differentiate */ -/* standard triggers from specific timer 20, needed for reallocation of */ +/* standard triggers from specific timer 20U, needed for reallocation of */ /* triggers common to ADC1&2 and to avoind mixing with standard */ /* triggers without remap. */ #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 @@ -716,8 +716,8 @@ typedef struct /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ /* device STM302xE: : using Timer20 with ADC trigger input remap */ -#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */ -#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */ +#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ +#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ #endif /* STM32F302xE */ #endif /* STM32F302xE || */ @@ -745,7 +745,7 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F303x8 || STM32F328xx */ @@ -769,7 +769,7 @@ typedef struct #define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1 #define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) @@ -786,7 +786,7 @@ typedef struct #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} @@ -805,8 +805,8 @@ typedef struct /** @defgroup ADCEx_Overrun ADC Extended overrun * @{ */ -#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) /*!< Default setting, to be used for compatibility with other STM32 devices */ -#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001) +#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */ +#define ADC_OVR_DATA_PRESERVED (0x00000001U) /** * @} */ @@ -840,7 +840,7 @@ typedef struct #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 #define ADC_CHANNEL_VBAT ADC_CHANNEL_17 -/* Note: Vopamp2/3/4 internal channels available on ADC2/3/4 respectively */ +/* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */ #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17 #define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17 @@ -855,7 +855,7 @@ typedef struct /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */ #define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */ @@ -870,8 +870,8 @@ typedef struct /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode * @{ */ -#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) -#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001) +#define ADC_SINGLE_ENDED (0x00000000U) +#define ADC_DIFFERENTIAL_ENDED (0x00000001U) /** * @} */ @@ -879,11 +879,11 @@ typedef struct /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number * @{ */ -#define ADC_OFFSET_NONE ((uint32_t)0x00) -#define ADC_OFFSET_1 ((uint32_t)0x01) -#define ADC_OFFSET_2 ((uint32_t)0x02) -#define ADC_OFFSET_3 ((uint32_t)0x03) -#define ADC_OFFSET_4 ((uint32_t)0x04) +#define ADC_OFFSET_NONE (0x00U) +#define ADC_OFFSET_1 (0x01U) +#define ADC_OFFSET_2 (0x02U) +#define ADC_OFFSET_3 (0x03U) +#define ADC_OFFSET_4 (0x04U) /** * @} */ @@ -891,22 +891,22 @@ typedef struct /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group * @{ */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) +#define ADC_REGULAR_RANK_1 (0x00000001U) +#define ADC_REGULAR_RANK_2 (0x00000002U) +#define ADC_REGULAR_RANK_3 (0x00000003U) +#define ADC_REGULAR_RANK_4 (0x00000004U) +#define ADC_REGULAR_RANK_5 (0x00000005U) +#define ADC_REGULAR_RANK_6 (0x00000006U) +#define ADC_REGULAR_RANK_7 (0x00000007U) +#define ADC_REGULAR_RANK_8 (0x00000008U) +#define ADC_REGULAR_RANK_9 (0x00000009U) +#define ADC_REGULAR_RANK_10 (0x0000000AU) +#define ADC_REGULAR_RANK_11 (0x0000000BU) +#define ADC_REGULAR_RANK_12 (0x0000000CU) +#define ADC_REGULAR_RANK_13 (0x0000000DU) +#define ADC_REGULAR_RANK_14 (0x0000000EU) +#define ADC_REGULAR_RANK_15 (0x0000000FU) +#define ADC_REGULAR_RANK_16 (0x00000010U) /** * @} */ @@ -914,10 +914,10 @@ typedef struct /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) +#define ADC_INJECTED_RANK_1 (0x00000001U) +#define ADC_INJECTED_RANK_2 (0x00000002U) +#define ADC_INJECTED_RANK_3 (0x00000003U) +#define ADC_INJECTED_RANK_4 (0x00000004U) /** * @} */ @@ -925,7 +925,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) @@ -971,7 +971,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_INJECTED_SOFTWARE_START (0x00000001U) #if defined(STM32F303xE) || defined(STM32F398xx) /*!< List of external triggers specific to device STM303xE: using Timer20 */ @@ -981,11 +981,11 @@ typedef struct /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ -#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */ +#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ /*!< External triggers of injected group for ADC3&ADC4 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ -#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14) */ +#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */ /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ @@ -994,7 +994,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ - /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11) */ + /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */ #endif /* STM32F303xE || STM32F398xx */ #if defined(STM32F303xC) || defined(STM32F358xx) @@ -1079,7 +1079,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_INJECTED_SOFTWARE_START (0x00000001U) #if defined(STM32F302xE) /*!< List of external triggers specific to device STM302xE: using Timer20 */ @@ -1089,7 +1089,7 @@ typedef struct /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ /* device STM302xE: : using Timer20 with ADC trigger input remap */ -#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */ +#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ #endif /* STM32F302xE */ @@ -1120,7 +1120,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) @@ -1144,7 +1144,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) @@ -1155,11 +1155,13 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2 +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1 +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15 -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} @@ -1169,7 +1171,7 @@ typedef struct /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) +#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U)) #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0)) #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1)) #define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0)) @@ -1185,7 +1187,7 @@ typedef struct /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode * @{ */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC will use its own DMA channel */ +#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** @@ -1195,7 +1197,7 @@ typedef struct /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases * @{ */ -#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) +#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U)) #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1)) #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) @@ -1214,9 +1216,9 @@ typedef struct /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection * @{ */ -#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) -#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) -#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) +#define ADC_ANALOGWATCHDOG_1 (0x00000001U) +#define ADC_ANALOGWATCHDOG_2 (0x00000002U) +#define ADC_ANALOGWATCHDOG_3 (0x00000003U) /** * @} */ @@ -1224,7 +1226,7 @@ typedef struct /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) +#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) @@ -1310,7 +1312,7 @@ typedef struct /** @defgroup ADCEx_Data_align ADC Extended Data Alignment * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT (0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} @@ -1319,7 +1321,7 @@ typedef struct /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode * @{ */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) +#define ADC_SCAN_DISABLE (0x00000000U) #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} @@ -1328,7 +1330,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} @@ -1358,7 +1360,7 @@ typedef struct */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000) +#define ADC_CHANNEL_0 (0x00000000U) #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) @@ -1388,7 +1390,7 @@ typedef struct /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ @@ -1403,22 +1405,22 @@ typedef struct /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group * @{ */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) +#define ADC_REGULAR_RANK_1 (0x00000001U) +#define ADC_REGULAR_RANK_2 (0x00000002U) +#define ADC_REGULAR_RANK_3 (0x00000003U) +#define ADC_REGULAR_RANK_4 (0x00000004U) +#define ADC_REGULAR_RANK_5 (0x00000005U) +#define ADC_REGULAR_RANK_6 (0x00000006U) +#define ADC_REGULAR_RANK_7 (0x00000007U) +#define ADC_REGULAR_RANK_8 (0x00000008U) +#define ADC_REGULAR_RANK_9 (0x00000009U) +#define ADC_REGULAR_RANK_10 (0x0000000AU) +#define ADC_REGULAR_RANK_11 (0x0000000BU) +#define ADC_REGULAR_RANK_12 (0x0000000CU) +#define ADC_REGULAR_RANK_13 (0x0000000DU) +#define ADC_REGULAR_RANK_14 (0x0000000EU) +#define ADC_REGULAR_RANK_15 (0x0000000FU) +#define ADC_REGULAR_RANK_16 (0x00000010U) /** * @} */ @@ -1426,10 +1428,10 @@ typedef struct /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) +#define ADC_INJECTED_RANK_1 (0x00000001U) +#define ADC_INJECTED_RANK_2 (0x00000002U) +#define ADC_INJECTED_RANK_3 (0x00000003U) +#define ADC_INJECTED_RANK_4 (0x00000004U) /** * @} */ @@ -1437,7 +1439,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} @@ -1463,7 +1465,7 @@ typedef struct /** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +#define ADC_ANALOGWATCHDOG_NONE (0x00000000U) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) @@ -1543,7 +1545,7 @@ typedef struct /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1 & ADC2 */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) @@ -1561,7 +1563,7 @@ typedef struct #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /* External triggers of regular group for ADC3 & ADC4 */ -#define ADC3_4_EXTERNALTRIG_T3_CC1 ((uint32_t)0x00000000) +#define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U) #define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) @@ -1584,7 +1586,7 @@ typedef struct defined(STM32F302xC) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) @@ -1604,7 +1606,7 @@ typedef struct #if defined(STM32F303x8) || defined(STM32F328xx) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) @@ -1625,7 +1627,7 @@ typedef struct #if defined(STM32F334x8) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) @@ -1644,7 +1646,7 @@ typedef struct #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers of regular group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) +#define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) @@ -1653,7 +1655,7 @@ typedef struct #define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) -#define ADC_SOFTWARE_START ((uint32_t)0x00000001) +#define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} @@ -1669,7 +1671,7 @@ typedef struct /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers for injected groups of ADC1 & ADC2 */ -#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) @@ -1694,9 +1696,9 @@ typedef struct /* differentiation between similar triggers of common groups ADC1&ADC2, */ /* ADC3&ADC4 (Differentiation processed into macro */ /* ADC_JSQR_JEXTSEL_SET) */ -#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) -#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000) +#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U) #define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) @@ -1721,7 +1723,7 @@ typedef struct defined(STM32F302xC) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) @@ -1740,7 +1742,7 @@ typedef struct #if defined(STM32F303x8) || defined(STM32F328xx) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) @@ -1761,7 +1763,7 @@ typedef struct #if defined(STM32F334x8) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) @@ -1780,8 +1782,10 @@ typedef struct #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers of injected group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) +#define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) +#define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) @@ -1815,7 +1819,7 @@ typedef struct /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIG_T19_TRGO ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U) #define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0) #define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1) #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) @@ -1834,7 +1838,7 @@ typedef struct /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of injected group for ADC1 */ -#define ADC_EXTERNALTRIGINJEC_T19_CC1 ((uint32_t) 0x00000000) +#define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U) #define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0) #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1) #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) @@ -1873,7 +1877,7 @@ typedef struct (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) -#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U) #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) @@ -1882,7 +1886,7 @@ typedef struct #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) -#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U) #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) @@ -1947,7 +1951,7 @@ typedef struct do{ \ SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ - } while(0) + } while(0U) /** * @brief Enable the ADC end of conversion interrupt. @@ -2275,7 +2279,7 @@ typedef struct * @param _CHANNELNB_: Channel number. * @retval None */ -#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) /** * @brief Set the ADC's sample time for Channels numbers between 10 and 18. @@ -2283,7 +2287,7 @@ typedef struct * @param _CHANNELNB_: Channel number. * @retval None */ -#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) /** * @brief Set the selected regular Channel rank for rank between 1 and 4. @@ -2291,7 +2295,7 @@ typedef struct * @param _RANKNB_: Rank number. * @retval None */ -#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_))) +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_))) /** * @brief Set the selected regular Channel rank for rank between 5 and 9. @@ -2299,7 +2303,7 @@ typedef struct * @param _RANKNB_: Rank number. * @retval None */ -#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 5))) +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U))) /** * @brief Set the selected regular Channel rank for rank between 10 and 14. @@ -2307,7 +2311,7 @@ typedef struct * @param _RANKNB_: Rank number. * @retval None */ -#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 10))) +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U))) /** * @brief Set the selected regular Channel rank for rank between 15 and 16. @@ -2315,7 +2319,7 @@ typedef struct * @param _RANKNB_: Rank number. * @retval None */ -#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 15))) +#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U))) /** * @brief Set the selected injected Channel rank. @@ -2323,7 +2327,7 @@ typedef struct * @param _RANKNB_: Rank number. * @retval None */ -#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_) +2)) +#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U)) /** @@ -2331,7 +2335,7 @@ typedef struct * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. * @retval None */ -#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26) +#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U) /** * @brief Configure the channel number into Analog Watchdog 2 or 3. @@ -2345,49 +2349,49 @@ typedef struct * @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion. * @retval None */ -#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25) +#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U) /** * @brief Enable ADC injected context queue * @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode. * @retval None */ -#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21) +#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U) /** * @brief Enable ADC discontinuous conversion mode for injected group * @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode. * @retval None */ -#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20) +#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U) /** * @brief Enable ADC discontinuous conversion mode for regular group * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. * @retval None */ -#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16) +#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U) /** * @brief Configures the number of discontinuous conversions for regular group. * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. * @retval None */ -#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17) +#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) /** * @brief Enable the ADC auto delay mode. * @param _AUTOWAIT_: Auto delay bit enable or disable. * @retval None */ -#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14) +#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ -#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) +#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) /** * @brief Enable ADC overrun mode. @@ -2395,11 +2399,11 @@ typedef struct * @retval Overrun bit setting to be programmed into CFGR register */ /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */ -/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */ /* as the default case to be compliant with other STM32 devices. */ #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ - )? (ADC_CFGR_OVRMOD) : (0x00000000) \ + )? (ADC_CFGR_OVRMOD) : (0x00000000U) \ ) /** @@ -2407,7 +2411,7 @@ typedef struct * @param _DMACONTREQ_MODE_: DMA continuous request mode. * @retval None */ -#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1) +#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U) /** * @brief For devices with 3 ADCs or more: Defines the external trigger source @@ -2598,7 +2602,7 @@ typedef struct * @param _CHANNEL_: ADC Channel * @retval None */ -#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26) +#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U) /** * @brief Configure the channel number into differential mode selection register @@ -2612,28 +2616,28 @@ typedef struct * @param _Calibration_Factor_: Calibration factor value * @retval None */ -#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16) +#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U) /** * @brief Calibration factor in differential mode to be retrieved from calibration register * @param _Calibration_Factor_: Calibration factor value * @retval None */ -#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16) +#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U) /** * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. * @param _Threshold_: Threshold value * @retval None */ -#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) +#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) /** * @brief Enable the ADC DMA continuous request for ADC multimode. * @param _DMAContReq_MODE_: DMA continuous request mode. * @retval None */ -#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13) +#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U) /** * @brief Verification of hardware constraints before ADC can be disabled @@ -2659,7 +2663,7 @@ typedef struct * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ - ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) + ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) /** * @brief Shift the AWD1 threshold in function of the selected ADC resolution. @@ -2674,7 +2678,7 @@ typedef struct * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ - ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) /** * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. @@ -2689,8 +2693,8 @@ typedef struct */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ - ((_Threshold_) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ - (_Threshold_) << 2 ) + ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \ + (_Threshold_) << 2U ) /** * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4 @@ -2872,7 +2876,7 @@ typedef struct #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (RESET) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /** * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4 @@ -3456,10 +3460,10 @@ typedef struct * @{ */ #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ - ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) ) + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) /** * @} */ @@ -3467,7 +3471,7 @@ typedef struct /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification * @{ */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) /** * @} */ @@ -3475,7 +3479,7 @@ typedef struct /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification * @{ */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) /** * @} */ @@ -3483,7 +3487,7 @@ typedef struct /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification * @{ */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @} */ @@ -3496,7 +3500,7 @@ typedef struct * @param _Calibration_Factor_: Calibration factor value * @retval None */ -#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F)) +#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU)) /** * @} */ @@ -3559,7 +3563,7 @@ typedef struct * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ - (((_NbrOfConversion_) - (uint8_t)1) << 20) + (((_NbrOfConversion_) - (uint8_t)1U) << 20U) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. @@ -3568,7 +3572,7 @@ typedef struct * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) + ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. @@ -3577,7 +3581,7 @@ typedef struct * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) + ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. @@ -3586,7 +3590,7 @@ typedef struct * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) + ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. @@ -3595,7 +3599,7 @@ typedef struct * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) + ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. @@ -3604,7 +3608,7 @@ typedef struct * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) + ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U))) /** * @brief Set the injected sequence length. @@ -3612,7 +3616,7 @@ typedef struct * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ - (((_JSQR_JL_) -1) << 20) + (((_JSQR_JL_) -1U) << 20U) /** * @brief Set the selected injected channel rank @@ -3625,7 +3629,7 @@ typedef struct * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ - ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) + ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U))) /** * @brief Enable ADC continuous conversion mode. @@ -3633,7 +3637,7 @@ typedef struct * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ - ((_CONTINUOUS_MODE_) << 1) + ((_CONTINUOUS_MODE_) << 1U) /** * @brief Configures the number of discontinuous conversions for the regular group channels. @@ -3641,7 +3645,7 @@ typedef struct * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ - (((_NBR_DISCONTINUOUS_CONV_) - 1) << 13) + (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. @@ -3661,7 +3665,7 @@ typedef struct * @retval None */ #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \ - ((_Calibration_Factor_) << 16) + ((_Calibration_Factor_) << 16U) /** * @brief Calibration factor in differential mode to be retrieved from calibration register @@ -3669,7 +3673,7 @@ typedef struct * @retval None */ #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \ - ((_Calibration_Factor_) >> 16) + ((_Calibration_Factor_) >> 16U) /** @@ -3712,16 +3716,16 @@ typedef struct */ #define ADC_CLOCK_PRESCALER_RANGE() \ (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \ - (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32 ) \ + (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \ : \ - (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128 ) \ + (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \ ) /** * @brief Get the ADC clock prescaler from system clock configuration register. * @retval None */ -#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14) +1) +#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ ((ALIGN) == ADC_DATAALIGN_LEFT) ) @@ -3822,7 +3826,7 @@ typedef struct * For a unique ADC resolution: 12 bits * @{ */ -#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) +#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU)) /** * @} */ @@ -3830,7 +3834,7 @@ typedef struct /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification * @{ */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) /** * @} */ @@ -3838,7 +3842,7 @@ typedef struct /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification * @{ */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) /** * @} */ @@ -3846,7 +3850,7 @@ typedef struct /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification * @{ */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_can.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_can.h index 9cb893307d419fe1fdd24ff7363c1dafcd20df55..46f1f01ad3c4c7223a4aef57d76de22743ad9f7a 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_can.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_can.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -66,16 +66,16 @@ */ /** * @brief HAL State structures definition - */ + */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ }HAL_CAN_StateTypeDef; @@ -144,7 +144,7 @@ typedef struct second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. @@ -255,16 +255,16 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ -#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ -#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ /** * @} */ @@ -272,8 +272,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -281,7 +281,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -293,7 +293,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -304,7 +304,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -327,7 +327,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -342,8 +342,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ /** * @} */ @@ -351,8 +351,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ /** * @} */ @@ -360,8 +360,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -369,8 +369,8 @@ typedef struct /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -378,8 +378,8 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ @@ -387,8 +387,8 @@ typedef struct /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ /** * @} */ @@ -402,34 +402,34 @@ typedef struct CAN_GetFlagStatus() function. */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} @@ -468,9 +468,9 @@ typedef struct * @{ */ /* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) /** * @} */ @@ -513,7 +513,7 @@ typedef struct * @retval The number of pending message. */ #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) /** @brief Check whether the specified CAN flag is set or not. * @param __HANDLE__: specifies the CAN Handle. @@ -543,10 +543,10 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Clear the specified CAN pending flag. @@ -576,10 +576,10 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Check if the specified CAN interrupt source is enabled or disabled. @@ -718,8 +718,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ @@ -741,9 +741,9 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) @@ -754,12 +754,12 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) +#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U)) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cec.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cec.h index 72cf0b2e964bb07113ecc3dead17be6a2b814183..422fcbff0ca839ae3b4ed5edcc44bba6abeb77af 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cec.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cec.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention @@ -51,7 +51,7 @@ * @{ */ -/** @addtogroup CEC CEC +/** @addtogroup CEC * @{ */ @@ -67,78 +67,120 @@ typedef struct { uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. It can be one of @ref CEC_Signal_Free_Time - and belongs to the set {0,...,7} where + and belongs to the set {0U,...,7} where 0x0 is the default configuration - else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ + else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, - it can be a value of @ref CEC_Tolerance : - @arg CEC_STANDARD_TOLERANCE - @arg CEC_EXTENDED_TOLERANCE */ + it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE + or CEC_EXTENDED_TOLERANCE */ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. - @arg CEC_NO_RX_STOP_ON_BRE: reception is not stopped. - @arg CEC_RX_STOP_ON_BRE: reception is stopped. */ + CEC_NO_RX_STOP_ON_BRE: reception is not stopped. + CEC_RX_STOP_ON_BRE: reception is stopped. */ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the CEC line upon Bit Rising Error detection. - @arg CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. - @arg CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ + CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the - @arg CEC line upon Long Bit Period Error detection. - @arg CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. - @arg CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ + CEC line upon Long Bit Period Error detection. + CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. + CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line upon an error detected on a broadcast message. It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: - @arg 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. - @arg __ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE + 1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION. + a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. - @arg __ b) LBPE detection: error-bit generation on the CEC line + b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. - @arg 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. + 2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. no error-bit generation in case neither a) nor b) are satisfied. Additionally, there is no error-bit generation in case of Short Bit Period Error detection in a broadcast message while LSTN bit is set. */ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. - @arg CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. - @arg CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ - - uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */ + CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: - @arg CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received. - @arg CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent. */ - uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of @ref CEC_OWN_ADDRESS */ + + uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ + }CEC_InitTypeDef; /** * @brief HAL CEC State structures definition + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. + * - gState contains CEC state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 Error information + * 0 : No Error + * 1 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */ - HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */ - HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */ - HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ + HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing + Value is allowed for gState only */ +HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ }HAL_CEC_StateTypeDef; /** @@ -154,21 +196,23 @@ typedef struct uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */ - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register - in case error is reported */ - HAL_LockTypeDef Lock; /*!< Locking object */ - HAL_CEC_StateTypeDef State; /*!< CEC communication state */ + HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + + uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register + in case error is reported */ }CEC_HandleTypeDef; /** - * @} - */ + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CEC_Exported_Constants CEC Exported Constants @@ -178,7 +222,7 @@ typedef struct /** @defgroup CEC_Error_Code CEC Error Code * @{ */ -#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< No error */ +#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */ #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ @@ -195,14 +239,14 @@ typedef struct /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter * @{ */ -#define CEC_DEFAULT_SFT ((uint32_t)0x00000000) /*!< Transmission history-based signal free time (ruled by hardware) */ -#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) /*!< 0.5 nominal data bit period */ -#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) /*!< 1.5 nominal data bit periods */ -#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) /*!< 2.5 nominal data bit periods */ -#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) /*!< 3.5 nominal data bit periods */ -#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) /*!< 4.5 nominal data bit periods */ -#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) /*!< 5.5 nominal data bit periods */ -#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) /*!< 6.5 nominal data bit periods */ +#define CEC_DEFAULT_SFT (0x00000000U) +#define CEC_0_5_BITPERIOD_SFT (0x00000001U) +#define CEC_1_5_BITPERIOD_SFT (0x00000002U) +#define CEC_2_5_BITPERIOD_SFT (0x00000003U) +#define CEC_3_5_BITPERIOD_SFT (0x00000004U) +#define CEC_4_5_BITPERIOD_SFT (0x00000005U) +#define CEC_5_5_BITPERIOD_SFT (0x00000006U) +#define CEC_6_5_BITPERIOD_SFT (0x00000007U) /** * @} */ @@ -210,8 +254,8 @@ typedef struct /** @defgroup CEC_Tolerance CEC Receiver Tolerance * @{ */ -#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) /*!< Standard tolerance margin */ -#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) /*!< Extended Tolerance */ +#define CEC_STANDARD_TOLERANCE (0x00000000U) +#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) /** * @} */ @@ -219,8 +263,8 @@ typedef struct /** @defgroup CEC_BRERxStop CEC Reception Stop on Error * @{ */ -#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) /*!< CEC reception not stopped by BRE detection */ -#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) /*!< CEC reception stopped by BRE detection */ +#define CEC_NO_RX_STOP_ON_BRE (0x00000000U) +#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) /** * @} */ @@ -228,8 +272,8 @@ typedef struct /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported * @{ */ -#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of BRE detection */ -#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) /*!< Error-Bit on CEC line in case of BRE detection */ +#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U) +#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) /** * @} */ @@ -237,8 +281,8 @@ typedef struct /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported * @{ */ -#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of LBPE detection */ -#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) /*!< Error-Bit on CEC line in case of LBPE detection */ +#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U) +#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) /** * @} */ @@ -246,10 +290,8 @@ typedef struct /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message * @{ */ -#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) /*!< Error-Bit on CEC line for specific error conditions - on a broadcast message (cf Reference Manual) */ -#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) /*!< No Error-Bit on CEC line for specific error conditions - on a broadcast message (cf Reference Manual) */ +#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U) +#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) /** * @} */ @@ -257,8 +299,8 @@ typedef struct /** @defgroup CEC_SFT_Option CEC Signal Free Time start option * @{ */ -#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) /*!< SFT timer starts when TXSOM is set by software */ -#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) /*!< SFT timer starts automatically at the end of message transmission/reception */ +#define CEC_SFT_START_ON_TXSOM (0x00000000U) +#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) /** * @} */ @@ -266,10 +308,8 @@ typedef struct /** @defgroup CEC_Listening_Mode CEC Listening mode option * @{ */ -#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) /*!< CEC peripheral receives only message addressed to its own address (OAR). */ -#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) /*!< CEC peripheral receives messages addressed to its own address (OAR) with - positive acknowledge. Messages addressed to different destination are - received, but without interfering with the CEC bus: no acknowledge sent. */ +#define CEC_REDUCED_LISTENING_MODE (0x00000000U) +#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) /** * @} */ @@ -277,7 +317,7 @@ typedef struct /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register * @{ */ -#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) /*!< CEC Device Own Address position in CEC CFGR register */ +#define CEC_CFGR_OAR_LSB_POS (16U) /** * @} */ @@ -285,47 +325,70 @@ typedef struct /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header * @{ */ -#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) /*!< CEC Initiator logical address position in message header */ +#define CEC_INITIATOR_LSB_POS (4U) +/** + * @} + */ + +/** @defgroup CEC_OWN_ADDRESS CEC Own Address + * @{ + */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */ +#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */ +#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */ +#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */ +#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */ +#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */ +#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */ /** * @} */ -/** @defgroup CEC_Interrupts_Definitions CEC interrupts definition +/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition * @{ */ -#define CEC_IT_TXACKE CEC_IER_TXACKEIE /*!< Tx missing acknowledge error interruption */ -#define CEC_IT_TXERR CEC_IER_TXERRIE /*!< Tx error interruption */ -#define CEC_IT_TXUDR CEC_IER_TXUDRIE /*!< Tx underrun interruption */ -#define CEC_IT_TXEND CEC_IER_TXENDIE /*!< Tx end of message interruption */ -#define CEC_IT_TXBR CEC_IER_TXBRIE /*!< Tx byte request interruption */ -#define CEC_IT_ARBLST CEC_IER_ARBLSTIE /*!< Arbitration lost interruption */ -#define CEC_IT_RXACKE CEC_IER_RXACKEIE /*!< Rx missing acknowledge error interruption */ -#define CEC_IT_LBPE CEC_IER_LBPEIE /*!< Long bit period error interruption */ -#define CEC_IT_SBPE CEC_IER_SBPEIE /*!< Short bit period error interruption */ -#define CEC_IT_BRE CEC_IER_BREIE /*!< Bit rising error interruption */ -#define CEC_IT_RXOVR CEC_IER_RXOVRIE /*!< Rx overrun interruption */ -#define CEC_IT_RXEND CEC_IER_RXENDIE /*!< End of reception interruption */ -#define CEC_IT_RXBR CEC_IER_RXBRIE /*!< RX byte received interruption */ +#define CEC_IT_TXACKE CEC_IER_TXACKEIE +#define CEC_IT_TXERR CEC_IER_TXERRIE +#define CEC_IT_TXUDR CEC_IER_TXUDRIE +#define CEC_IT_TXEND CEC_IER_TXENDIE +#define CEC_IT_TXBR CEC_IER_TXBRIE +#define CEC_IT_ARBLST CEC_IER_ARBLSTIE +#define CEC_IT_RXACKE CEC_IER_RXACKEIE +#define CEC_IT_LBPE CEC_IER_LBPEIE +#define CEC_IT_SBPE CEC_IER_SBPEIE +#define CEC_IT_BRE CEC_IER_BREIE +#define CEC_IT_RXOVR CEC_IER_RXOVRIE +#define CEC_IT_RXEND CEC_IER_RXENDIE +#define CEC_IT_RXBR CEC_IER_RXBRIE /** * @} */ -/** @defgroup CEC_Flags_Definitions CEC flags definition +/** @defgroup CEC_Flags_Definitions CEC Flags definition * @{ */ -#define CEC_FLAG_TXACKE CEC_ISR_TXACKE /*!< Tx missing acknowledge error flag */ -#define CEC_FLAG_TXERR CEC_ISR_TXERR /*!< Tx error flag */ -#define CEC_FLAG_TXUDR CEC_ISR_TXUDR /*!< Tx underrun flag */ -#define CEC_FLAG_TXEND CEC_ISR_TXEND /*!< Tx end of message flag */ -#define CEC_FLAG_TXBR CEC_ISR_TXBR /*!< Tx byte request flag */ -#define CEC_FLAG_ARBLST CEC_ISR_ARBLST /*!< Arbitration lost flag */ -#define CEC_FLAG_RXACKE CEC_ISR_RXACKE /*!< Rx missing acknowledge error flag */ -#define CEC_FLAG_LBPE CEC_ISR_LBPE /*!< Long bit period error flag */ -#define CEC_FLAG_SBPE CEC_ISR_SBPE /*!< Short bit period error flag */ -#define CEC_FLAG_BRE CEC_ISR_BRE /*!< Bit rising error flag */ -#define CEC_FLAG_RXOVR CEC_ISR_RXOVR /*!< Rx overrun flag */ -#define CEC_FLAG_RXEND CEC_ISR_RXEND /*!< End of reception flag */ -#define CEC_FLAG_RXBR CEC_ISR_RXBR /*!< RX byte received flag */ +#define CEC_FLAG_TXACKE CEC_ISR_TXACKE +#define CEC_FLAG_TXERR CEC_ISR_TXERR +#define CEC_FLAG_TXUDR CEC_ISR_TXUDR +#define CEC_FLAG_TXEND CEC_ISR_TXEND +#define CEC_FLAG_TXBR CEC_ISR_TXBR +#define CEC_FLAG_ARBLST CEC_ISR_ARBLST +#define CEC_FLAG_RXACKE CEC_ISR_RXACKE +#define CEC_FLAG_LBPE CEC_ISR_LBPE +#define CEC_FLAG_SBPE CEC_ISR_SBPE +#define CEC_FLAG_BRE CEC_ISR_BRE +#define CEC_FLAG_RXOVR CEC_ISR_RXOVR +#define CEC_FLAG_RXEND CEC_ISR_RXEND +#define CEC_FLAG_RXBR CEC_ISR_RXBR /** * @} */ @@ -334,7 +397,7 @@ typedef struct * @{ */ #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /*!< All Rx or Tx errors flags concatenation */ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /** * @} */ @@ -342,7 +405,7 @@ typedef struct /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag * @{ */ -#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /*!< All Rx errors interruptions concatenation */ +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /** * @} */ @@ -350,7 +413,7 @@ typedef struct /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag * @{ */ -#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /*!< All Tx errors interruptions concatenation */ +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /** * @} */ @@ -364,16 +427,18 @@ typedef struct * @{ */ -/** @brief Reset CEC handle state +/** @brief Reset CEC handle gstate & RxState * @param __HANDLE__: CEC handle. * @retval None */ -#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET) +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ + } while(0U) -/** @brief Check whether or not the specified CEC interrupt flag is set. +/** @brief Checks whether or not the specified CEC interrupt flag is set. * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the interrupt to check. - * This parameter can be one of the following values: + * @param __FLAG__: specifies the flag to check. * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. @@ -383,15 +448,15 @@ typedef struct * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge * @arg CEC_FLAG_LBPE: Rx Long period Error * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error * @arg CEC_FLAG_RXOVR: Rx Overrun. * @arg CEC_FLAG_RXEND: End Of Reception. * @arg CEC_FLAG_RXBR: Rx-Byte Received. - * @retval IT Status + * @retval ITStatus */ #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) -/** @brief Clear the interrupt or status flag when raised (write at 1) +/** @brief Clears the interrupt or status flag when raised (write at 1U) * @param __HANDLE__: specifies the CEC Handle. * @param __FLAG__: specifies the interrupt/status flag to clear. * This parameter can be one of the following values: @@ -404,7 +469,7 @@ typedef struct * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge * @arg CEC_FLAG_LBPE: Rx Long period Error * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_BRE: Rx Bit Rising Error * @arg CEC_FLAG_RXOVR: Rx Overrun. * @arg CEC_FLAG_RXEND: End Of Reception. * @arg CEC_FLAG_RXBR: Rx-Byte Received. @@ -412,7 +477,7 @@ typedef struct */ #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) -/** @brief Enable the specified CEC interrupt. +/** @brief Enables the specified CEC interrupt. * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to enable. * This parameter can be one of the following values: @@ -433,7 +498,7 @@ typedef struct */ #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) -/** @brief Disable the specified CEC interrupt. +/** @brief Disables the specified CEC interrupt. * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to disable. * This parameter can be one of the following values: @@ -454,7 +519,7 @@ typedef struct */ #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) -/** @brief Check whether or not the specified CEC interrupt is enabled. +/** @brief Checks whether or not the specified CEC interrupt is enabled. * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to check. * This parameter can be one of the following values: @@ -471,58 +536,57 @@ typedef struct * @arg CEC_IT_RXOVR: Rx Overrun IT Enable * @arg CEC_IT_RXEND: End Of Reception IT Enable * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable - * @retval Flag Status + * @retval FlagStatus */ #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) -/** @brief Enable the CEC device. +/** @brief Enables the CEC device * @param __HANDLE__: specifies the CEC Handle. * @retval none */ #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) -/** @brief Disable the CEC device. +/** @brief Disables the CEC device * @param __HANDLE__: specifies the CEC Handle. * @retval none */ #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) -/** @brief Set Transmission Start flag. +/** @brief Set Transmission Start flag * @param __HANDLE__: specifies the CEC Handle. * @retval none */ #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) -/** @brief Set Transmission End flag. +/** @brief Set Transmission End flag * @param __HANDLE__: specifies the CEC Handle. - * @note If the CEC message consists of only one byte, TXEOM must be set before TXSOM. * @retval none - * + * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) -/** @brief Get Transmission Start flag. +/** @brief Get Transmission Start flag * @param __HANDLE__: specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) -/** @brief Get Transmission End flag. +/** @brief Get Transmission End flag * @param __HANDLE__: specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) -/** @brief Clear OAR register. +/** @brief Clear OAR register * @param __HANDLE__: specifies the CEC Handle. * @retval none */ #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) -/** @brief Set OAR register (without resetting previously set address in case of multi-address mode). +/** @brief Set OAR register (without resetting previously set address in case of multi-address mode) + * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand * @param __HANDLE__: specifies the CEC Handle. - * @param __ADDRESS__: own address value (CEC logical address is identified by bit position) - * @note To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand. + * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) @@ -532,46 +596,42 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CEC_Exported_Functions CEC Exported Functions +/** @addtogroup CEC_Exported_Functions * @{ */ -/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup CEC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); /** * @} */ -/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions - * @brief CEC Transmit/Receive functions +/** @addtogroup CEC_Exported_Functions_Group2 * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); /** * @} */ -/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control functions - * @brief CEC control functions +/** @addtogroup CEC_Exported_Functions_Group3 * @{ */ -/* Peripheral State and Error functions ***************************************/ +/* Peripheral State functions ************************************************/ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); /** @@ -582,6 +642,33 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * @} */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup CEC_Private_Types CEC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Variables CEC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup CEC_Private_Macros CEC Private Macros * @{ @@ -592,8 +679,8 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) -#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ - ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) +#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ + ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) @@ -610,28 +697,36 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ ((__MODE__) == CEC_FULL_LISTENING_MODE)) +/** @brief Check CEC message size. + * The message size is the payload size: without counting the header, + * it varies from 0 byte (ping operation, one header only, no payload) to + * 15 bytes (1 opcode and up to 14 operands following the header). + * @param __SIZE__: CEC message size. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) + /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. * @param __ADDRESS__: CEC own address. * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF) +#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. * @param __ADDRESS__: CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) - -/** @brief Check CEC message size. - * The message size is the payload size: without counting the header, - * it varies from 0 byte (ping operation, one header only, no payload) to - * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. - * @retval Test result (TRUE or FALSE). +#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) +/** + * @} */ -#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ + /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp.h index 1f2647c6ab11d799693da117ab056cdbe0143d54..535c4263780dc49f6b9c1759d5e5fb15587671ab 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention @@ -90,7 +90,7 @@ typedef struct This parameter can be a value of @ref COMPEx_Mode Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */ - uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2, 4 or 6 if available). + uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available). This parameter can be a value of @ref COMPEx_WindowMode */ uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode). @@ -103,10 +103,10 @@ typedef struct */ typedef enum { - HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */ - HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */ - HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */ - HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ }HAL_COMP_StateTypeDef; @@ -133,7 +133,7 @@ typedef struct /** @defgroup COMP_OutputPolarity COMP Output Polarity * @{ */ -#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */ #define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */ /** * @} @@ -144,7 +144,7 @@ typedef struct */ /* When output polarity is not inverted, comparator output is low when the non-inverting input is at a lower voltage than the inverting input*/ -#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) +#define COMP_OUTPUTLEVEL_LOW (0x00000000U) /* When output polarity is not inverted, comparator output is high when the non-inverting input is at a higher voltage than the inverting input */ #define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT @@ -155,13 +155,13 @@ typedef struct /** @defgroup COMP_TriggerMode COMP Trigger Mode * @{ */ -#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */ -#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */ -#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */ +#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */ +#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -169,7 +169,7 @@ typedef struct /** @defgroup COMP_State_Lock COMP State Lock * @{ */ -#define COMP_STATE_BIT_LOCK ((uint32_t)0x00000010) /* Lock bit in COMP handle state */ +#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp_ex.h index e02d6afe667800ba6b786fd90ce7516747329e27..0a61ccb2b6f18d8ec4078998a195f74dbf886814 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_comp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of COMP HAL Extended module. ****************************************************************************** * @attention @@ -65,9 +65,9 @@ /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices) * @{ */ -#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */ @@ -86,9 +86,9 @@ /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices) * @{ */ -#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6) @@ -106,9 +106,9 @@ /* connected to a GPIO. */ /* It must be chosen among the 2 literals COMP_INVERTINGINPUT_IOx */ /* depending on comparator instance COMPx. */ -#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */ @@ -128,9 +128,9 @@ /** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices) * @{ */ -#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1/2 VREFINT connected to comparator inverting input */ -#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1U/2 VREFINT connected to comparator inverting input */ +#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3U/4 VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2) /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */ @@ -150,7 +150,7 @@ /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices) * @{ */ -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, +#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) connected to comparator non inverting input */ #define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, @@ -163,7 +163,7 @@ /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices) * @{ */ -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6) +#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6) connected to comparator non inverting input */ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */ /** @@ -173,7 +173,7 @@ /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices) * @{ */ -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA3 for COMP2) +#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2) connected to comparator non inverting input */ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ /** @@ -183,7 +183,7 @@ /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices) * @{ */ -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, +#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) connected to comparator non inverting input */ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ @@ -194,7 +194,7 @@ /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices) * @{ */ -#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6) +#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6) connected to comparator non inverting input */ /** * @} @@ -209,23 +209,23 @@ * @{ */ /* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */ -#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */ +#define COMP_OUTPUT_TIM1BKIN2 (0x0000142AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ /* Output Redirection specific to COMP2 */ -#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */ -#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */ +#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */ /* Output Redirection specific to COMP4 */ -#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */ -#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */ +#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */ +#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */ /* Output Redirection specific to COMP6 */ -#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */ -#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */ -#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */ +#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */ +#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */ +#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ /** * @} */ @@ -237,26 +237,26 @@ * @{ */ /* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1BKIN2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ /* Output Redirection common to COMP2 and COMP4 */ -#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0A) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0AU) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */ /* Output Redirection specific to COMP2 */ -#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */ -#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002802) /*!< COMP2 output connected to TIM3 Input Capture 1 */ +#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */ +#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC1 (0x00002802U) /*!< COMP2 output connected to TIM3 Input Capture 1U */ /* Output Redirection specific to COMP4 */ -#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */ -#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */ -#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */ +#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */ +#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */ /* Output Redirection specific to COMP6 */ -#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */ -#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */ -#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */ +#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */ +#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */ +#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ /** * @} */ @@ -268,29 +268,29 @@ * @{ */ /* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0000002B) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */ -#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_NONE (0x0000002BU) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN (0x0000042BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */ +#define COMP_OUTPUT_TIM1BKIN2 (0x0000142BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */ /* Output Redirection common to COMP1 and COMP2 */ -#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001803) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */ -#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002403) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */ +#define COMP_OUTPUT_TIM1OCREFCLR (0x00001803U) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */ +#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x00002403U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */ /* Output Redirection common to COMP1,COMP2 and COMP4 */ -#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0B) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0BU) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */ /* Output Redirection specific to COMP4 */ -#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */ -#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */ -#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */ -#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */ +#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */ +#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */ +#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */ /* Output Redirection specific to COMP6 */ -#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */ -#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */ -#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */ -#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */ +#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */ +#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */ +#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ +#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */ /** * @} */ @@ -302,50 +302,50 @@ * @{ */ /* Output Redirection values common to all comparators COMP1...COMP7 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */ -#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */ -#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */ +#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */ /* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */ -#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */ /* Output Redirection common to COMP1, COMP2 and COMP3 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */ /* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */ -#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */ /* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */ -#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */ +#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */ /* Output Redirection common to COMP1 and COMP2 */ -#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */ +#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */ +#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */ /* Output Redirection specific to COMP3 */ -#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */ -#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */ -#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */ -#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */ +#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */ +#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */ +#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */ /* Output Redirection specific to COMP4 */ -#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */ -#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */ -#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */ -#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */ +#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */ +#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */ +#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */ /* Output Redirection specific to COMP5 */ -#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */ -#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */ -#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */ -#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */ +#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */ +#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */ +#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */ /* Output Redirection specific to COMP6 */ -#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */ -#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */ -#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */ -#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */ +#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */ +#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */ +#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ +#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */ /* Output Redirection specific to COMP7 */ -#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */ -#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */ -#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */ -#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */ +#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */ +#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */ +#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ /** * @} */ @@ -357,55 +357,55 @@ * @{ */ /* Output Redirection values common to all comparators COMP1...COMP7 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */ -#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */ -#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */ -#define COMP_OUTPUT_TIM20BKIN ((uint32_t)0x0000307F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */ -#define COMP_OUTPUT_TIM20BKIN2 ((uint32_t)0x0000347F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */ -#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 ((uint32_t)0x0000387F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input 2 */ +#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */ +#define COMP_OUTPUT_TIM20BKIN (0x0000307FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM20BKIN2 (0x0000347FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */ +#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 (0x0000387FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2U, TIM8 Break Input 2 and TIM20 Break Input 2 */ /* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */ -#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */ +#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */ /* Output Redirection common to COMP1, COMP2 and COMP3 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */ /* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */ -#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */ /* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */ -#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */ +#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */ /* Output Redirection common to COMP1 and COMP2 */ -#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */ +#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */ +#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */ /* Output Redirection specific to COMP2 */ -#define COMP_OUTPUT_TIM20OCREFCLR ((uint32_t)0x00003C04) /*!< COMP2 output connected to TIM20 OCREF Clear */ +#define COMP_OUTPUT_TIM20OCREFCLR (0x00003C04U) /*!< COMP2 output connected to TIM20 OCREF Clear */ /* Output Redirection specific to COMP3 */ -#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */ -#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */ -#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */ -#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */ +#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */ +#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */ +#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */ /* Output Redirection specific to COMP4 */ -#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */ -#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */ -#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */ -#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */ +#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */ +#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */ +#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */ +#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */ /* Output Redirection specific to COMP5 */ -#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */ -#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */ -#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */ -#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */ +#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */ +#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */ +#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */ /* Output Redirection specific to COMP6 */ -#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */ -#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */ -#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */ -#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */ -#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */ +#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */ +#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */ +#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */ +#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */ /* Output Redirection specific to COMP7 */ -#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */ -#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */ -#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */ -#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ +#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */ +#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */ +#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */ +#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */ /** * @} */ @@ -417,21 +417,21 @@ * @{ */ /* Output Redirection values common to all comparators COMP1 and COMP2 */ -#define COMP_OUTPUT_NONE ((uint32_t)0x0003) /*!< COMP1 or COMP2 output isn't connected to other peripherals */ -#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x0403) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */ -#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x0503) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */ +#define COMP_OUTPUT_NONE (0x0003U) /*!< COMP1 or COMP2 output isn't connected to other peripherals */ +#define COMP_OUTPUT_TIM2IC4 (0x0403U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */ +#define COMP_OUTPUT_TIM2OCREFCLR (0x0503U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */ /* Output Redirection specific to COMP1 */ -#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x0101) /*!< COMP1 output connected to TIM15 Break Input */ -#define COMP_OUTPUT_COMP1_TIM3IC1 ((uint32_t)0x0201) /*!< COMP1 output connected to TIM3 Input Capture 1 */ -#define COMP_OUTPUT_COMP1_TIM3OCREFCLR ((uint32_t)0x0301) /*!< COMP1 output connected to TIM3 OCREF Clear */ -#define COMP_OUTPUT_TIM5IC4 ((uint32_t)0x0601) /*!< COMP1 output connected to TIM5 Input Capture 4 */ -#define COMP_OUTPUT_TIM5OCREFCLR ((uint32_t)0x0701) /*!< COMP1 output connected to TIM5 OCREF Clear */ +#define COMP_OUTPUT_TIM15BKIN (0x0101U) /*!< COMP1 output connected to TIM15 Break Input */ +#define COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U) /*!< COMP1 output connected to TIM3 Input Capture 1U */ +#define COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U) /*!< COMP1 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM5IC4 (0x0601U) /*!< COMP1 output connected to TIM5 Input Capture 4U */ +#define COMP_OUTPUT_TIM5OCREFCLR (0x0701U) /*!< COMP1 output connected to TIM5 OCREF Clear */ /* Output Redirection specific to COMP2 */ -#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x0102) /*!< COMP2 output connected to TIM16 Break Input */ -#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x0202) /*!< COMP2 output connected to TIM4 Input Capture 1 */ -#define COMP_OUTPUT_TIM4OCREFCLR ((uint32_t)0x0302) /*!< COMP2 output connected to TIM4 OCREF Clear */ -#define COMP_OUTPUT_COMP2_TIM3IC1 ((uint32_t)0x0602) /*!< COMP2 output connected to TIM3 Input Capture 1 */ -#define COMP_OUTPUT_COMP2_TIM3OCREFCLR ((uint32_t)0x0702) /*!< COMP2 output connected to TIM3 OCREF Clear */ +#define COMP_OUTPUT_TIM16BKIN (0x0102U) /*!< COMP2 output connected to TIM16 Break Input */ +#define COMP_OUTPUT_TIM4IC1 (0x0202U) /*!< COMP2 output connected to TIM4 Input Capture 1U */ +#define COMP_OUTPUT_TIM4OCREFCLR (0x0302U) /*!< COMP2 output connected to TIM4 OCREF Clear */ +#define COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U) /*!< COMP2 output connected to TIM3 Input Capture 1U */ +#define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U) /*!< COMP2 output connected to TIM3 OCREF Clear */ /** * @} */ @@ -441,9 +441,9 @@ /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices) * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */ -#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6) - is connected to the non inverting input of comparator X-1 */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ +#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) + is connected to the non inverting input of comparator X-1U */ /** * @} */ @@ -451,9 +451,9 @@ /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices) * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */ -#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6) - is connected to the non inverting input of comparator X-1 */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ +#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U) + is connected to the non inverting input of comparator X-1U */ /** * @} */ @@ -461,7 +461,7 @@ /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices) * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */ #define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2 is connected to the non inverting input of comparator 1 (PA1) */ /** @@ -471,7 +471,7 @@ /** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices) * @{ */ -#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled (not available) */ +#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled (not available) */ /** * @} */ @@ -485,7 +485,7 @@ /* Please refer to the electrical characteristics in the device datasheet for the power consumption values */ -#define COMP_MODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */ +#define COMP_MODE_HIGHSPEED (0x00000000U) /*!< High Speed */ #define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0 /*!< Medium Speed */ #define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1 /*!< Low power mode */ #define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE /*!< Ultra-low power mode */ @@ -502,14 +502,14 @@ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ +#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ #define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */ #define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */ #define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST /*!< Hysteresis level high */ #else -#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */ +#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ @@ -523,7 +523,7 @@ * @{ */ /* No blanking source can be selected for all comparators */ -#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */ +#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */ /* Blanking source for COMP2 */ #define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP2 */ #define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP2 */ @@ -547,7 +547,7 @@ * @{ */ /* No blanking source can be selected for all comparators */ -#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */ +#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */ /* Blanking source common for COMP1 and COMP2 */ #define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */ /* Blanking source common for COMP1 and COMP2 */ @@ -573,7 +573,7 @@ * @{ */ /* No blanking source can be selected for all comparators */ -#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */ +#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */ /* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */ #define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */ /* Blanking source common for COMP1 and COMP2 */ @@ -601,7 +601,7 @@ * @{ */ /* No blanking source can be selected for all comparators */ -#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */ +#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */ /** * @} */ @@ -645,7 +645,7 @@ regshift = COMP_CSR_COMP2_SHIFT; \ } \ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \ - } while(0) + } while(0U) /** * @brief Disable the specified comparator. @@ -661,7 +661,7 @@ regshift = COMP_CSR_COMP2_SHIFT; \ } \ CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \ - } while(0) + } while(0U) /** * @brief Lock a comparator instance @@ -677,7 +677,7 @@ regshift = COMP_CSR_COMP2_SHIFT; \ } \ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); \ - } while(0) + } while(0U) /** @brief Check whether the specified COMP flag is set or not. * @param __HANDLE__ COMP Handle. @@ -759,7 +759,7 @@ #define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. @@ -768,7 +768,7 @@ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP1 EXTI line in interrupt mode. @@ -847,7 +847,7 @@ #define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. @@ -856,7 +856,7 @@ #define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP2 EXTI line in interrupt mode. @@ -934,7 +934,7 @@ #define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. @@ -943,7 +943,7 @@ #define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP3 EXTI line in interrupt mode. @@ -1026,7 +1026,7 @@ #define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP4 EXTI line rising & falling edge trigger. @@ -1035,7 +1035,7 @@ #define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP4 EXTI line in interrupt mode. @@ -1118,7 +1118,7 @@ #define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP5 EXTI line rising & falling edge trigger. @@ -1127,7 +1127,7 @@ #define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP5 EXTI line in interrupt mode. @@ -1210,7 +1210,7 @@ #define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP6 EXTI line rising & falling edge trigger. @@ -1219,7 +1219,7 @@ #define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP6 EXTI line in interrupt mode. @@ -1301,7 +1301,7 @@ #define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Disable the COMP7 EXTI line rising & falling edge trigger. @@ -1310,7 +1310,7 @@ #define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) + } while(0U) /** * @brief Enable the COMP7 EXTI line in interrupt mode. @@ -1431,30 +1431,30 @@ #define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */ #if defined(STM32F373xC) || defined(STM32F378xx) /* CSR register reset value */ -#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000) -#define COMP_CSR_RESET_PARAMETERS_MASK ((uint32_t)0x00003FFF) -#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0x00003FFE) +#define COMP_CSR_RESET_VALUE (0x00000000U) +#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU) +#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU) /* CSR COMP1/COMP2 shift */ #define COMP_CSR_COMP1_SHIFT 0U #define COMP_CSR_COMP2_SHIFT 16U #else /* CSR register reset value */ -#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000) +#define COMP_CSR_RESET_VALUE (0x00000000U) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define COMP_CSR_COMPxNONINSEL_MASK (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */ -#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */ #define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */ #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define COMP_CSR_COMPxNONINSEL_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxNONINSEL_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */ #define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */ #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ @@ -1468,9 +1468,9 @@ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define COMP_CSR_COMPxNONINSEL_MASK (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */ -#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */ -#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ -#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */ #define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ @@ -1479,7 +1479,7 @@ #define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */ #define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */ #define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */ -#define COMP_CSR_COMPxBLANKING_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */ +#define COMP_CSR_COMPxBLANKING_MASK (0x00000000U) /*!< Mask empty: feature not available */ #endif /* STM32F373xC || STM32F378xx */ /** @@ -1592,7 +1592,7 @@ { \ COMP->CSR |= COMP_CSR_WNDWEN; \ } \ - } while(0) + } while(0U) /** * @brief DeInit a comparator instance @@ -1610,7 +1610,7 @@ MODIFY_REG(COMP->CSR, \ COMP_CSR_RESET_PARAMETERS_MASK << regshift, \ COMP_CSR_RESET_VALUE << regshift); \ - } while(0) + } while(0U) /** @@ -1703,7 +1703,7 @@ */ #define COMP_INIT(__HANDLE__) \ do { \ - __IO uint32_t csrreg = 0; \ + __IO uint32_t csrreg = 0U; \ \ csrreg = READ_REG((__HANDLE__)->Instance->CSR); \ MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \ @@ -1715,7 +1715,7 @@ MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode); \ MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode); \ WRITE_REG((__HANDLE__)->Instance->CSR, csrreg); \ - } while(0) + } while(0U) /** * @brief DeInit a comparator instance @@ -1933,7 +1933,7 @@ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2)) -/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */ +/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */ #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \ ((((INSTANCE) == COMP2) && \ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \ @@ -2032,7 +2032,7 @@ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2)) -/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */ +/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */ #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \ ((((INSTANCE) == COMP2) && \ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_conf.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_conf.h index d2ec474410864cafee8bcb3018c36cef8379e763..10e1ee60f04047369a936377179e6735d6fe80db 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_conf.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_conf.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_conf.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -92,7 +92,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** @@ -100,7 +100,7 @@ * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -109,7 +109,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -117,14 +117,14 @@ * Timeout value */ #if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ + #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ #endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)40000) + #define LSI_VALUE (40000U) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ @@ -132,14 +132,14 @@ * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** @@ -150,7 +150,7 @@ * - External clock not generated on EVAL 373 */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ + #define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -160,8 +160,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */ +#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 0 @@ -172,7 +172,7 @@ * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ -/*#define USE_FULL_ASSERT 1*/ +/*#define USE_FULL_ASSERT 1U*/ /* Includes ------------------------------------------------------------------*/ /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cortex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cortex.h index db08149ef99f9714828e44b96c0122ef02e8766a..5610c9396d97f1df0cb46cf8eecae75131eea1ef 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cortex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cortex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -58,7 +58,7 @@ * @{ */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ @@ -105,15 +105,15 @@ typedef struct /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority +#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /** * @} @@ -122,20 +122,20 @@ typedef struct /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source * @{ */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) /** * @} */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) +#define MPU_HARDFAULT_NMI (0x00000002U) +#define MPU_PRIVILEGED_DEFAULT (0x00000004U) +#define MPU_HFNMI_PRIVDEF (0x00000006U) /** * @} */ @@ -143,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) /** * @} */ @@ -152,8 +152,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /** * @} */ @@ -161,8 +161,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /** * @} */ @@ -170,8 +170,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /** * @} */ @@ -179,8 +179,8 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /** * @} */ @@ -188,9 +188,9 @@ typedef struct /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /** * @} */ @@ -198,34 +198,34 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /** * @} */ @@ -233,12 +233,12 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /** * @} */ @@ -246,14 +246,14 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /** * @} */ @@ -289,7 +289,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); * @{ */ /* Peripheral Control functions ***********************************************/ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); @@ -322,9 +322,9 @@ void HAL_SYSTICK_Callback(void); ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) @@ -337,7 +337,7 @@ void HAL_SYSTICK_Callback(void); * @} */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) @@ -402,7 +402,7 @@ void HAL_SYSTICK_Callback(void); ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ /** @@ -415,39 +415,11 @@ void HAL_SYSTICK_Callback(void); * @{ */ -#if (__MPU_PRESENT == 1) -/** - * @brief Disables the MPU - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} +#if (__MPU_PRESENT == 1U) -/** - * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +void HAL_MPU_Disable(void); +void HAL_MPU_Enable(uint32_t MPU_Control); - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} #endif /* __MPU_PRESENT */ /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc.h index 5f6ce7d4bbcf3b6d237990a50bafff1b8d04b52c..299ccec2b102bbffc487c7229675745e178ffb95 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -63,10 +63,10 @@ */ typedef enum { - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ }HAL_CRC_StateTypeDef; @@ -78,7 +78,7 @@ typedef struct { uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1. In that case, there is no need to set GeneratingPolynomial field. If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ @@ -87,9 +87,9 @@ typedef struct 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ - uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, - e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree + respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation, + e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. @@ -107,12 +107,12 @@ typedef struct @arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion @arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 @arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion, - @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488 */ + @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U */ }CRC_InitTypeDef; @@ -149,7 +149,7 @@ typedef struct /** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ -#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */ /** * @} @@ -167,8 +167,8 @@ typedef struct /** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) /*!< Disable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7U */ /** * @} */ @@ -176,8 +176,8 @@ typedef struct /** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) /*!< Enable initial CRC default value */ -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) /*!< Disable initial CRC default value */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ /** * @} */ @@ -185,7 +185,7 @@ typedef struct /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ -#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ #define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ #define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ #define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ @@ -212,10 +212,10 @@ typedef struct * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) /*!< Input data in word format */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U) /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U) /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U) /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U) /*!< Input data in word format */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc_ex.h index 81427ef6947a45b029e8299ae2f87a640db70d2c..1c218add99521788a83335541e45b0f9d4a8d744 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention @@ -63,7 +63,7 @@ /** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes * @{ */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ #define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */ @@ -74,7 +74,7 @@ /** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ #define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ /** * @} diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac.h index 50b784e8e65f718ac78c7e8008df79a5bcd3fff4..0de9d7e3e667c1766ed5e531da05bf23f9bd7ccd 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -65,10 +65,10 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ }HAL_DAC_StateTypeDef; @@ -104,9 +104,9 @@ typedef struct __DAC_HandleTypeDef HAL_LockTypeDef Lock; /*!< DAC locking object */ - DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */ - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */ __IO uint32_t ErrorCode; /*!< DAC Error code */ @@ -134,7 +134,7 @@ typedef struct __DAC_HandleTypeDef /** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -146,18 +146,18 @@ typedef struct __DAC_HandleTypeDef #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ +#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */ +#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */ +#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */ +#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */ +#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */ +#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */ +#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */ +#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */ +#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */ +#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */ +#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */ +#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */ /** * @} @@ -166,7 +166,7 @@ typedef struct __DAC_HandleTypeDef /** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) /** @@ -177,7 +177,7 @@ typedef struct __DAC_HandleTypeDef /** @defgroup DAC_output_switch DAC output switch * @{ */ -#define DAC_OUTPUTSWITCH_DISABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U) #define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1) /** @@ -188,9 +188,9 @@ typedef struct __DAC_HandleTypeDef /** @defgroup DAC_data_alignement DAC data alignement * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R (0x00000000U) +#define DAC_ALIGN_12B_L (0x00000004U) +#define DAC_ALIGN_8B_R (0x00000008U) /** * @} @@ -251,19 +251,19 @@ typedef struct __DAC_HandleTypeDef * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment * @param __ALIGNMENT__: specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt * @param __HANDLE__: specifies the DAC handle @@ -362,7 +362,7 @@ typedef struct __DAC_HandleTypeDef ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac_ex.h index e8cd1e72a49c8e5c12027f381fdb868afc7df489..8380807b734162c645f4b0936492938de12a6c42 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention @@ -65,7 +65,7 @@ */ #if defined(STM32F301x8) || defined(STM32F318xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ @@ -85,7 +85,7 @@ defined(STM32F302xC) || \ defined(STM32F302x8) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ @@ -111,7 +111,7 @@ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ @@ -141,7 +141,7 @@ #if defined(STM32F303x8) || defined(STM32F328xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ @@ -166,7 +166,7 @@ #if defined(STM32F373xC) || defined(STM32F378xx) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ @@ -194,7 +194,7 @@ #if defined(STM32F334x8) -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel @@ -237,7 +237,7 @@ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */ +#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */ #endif /* STM32F302xE || */ /* STM32F302xC || */ @@ -246,8 +246,8 @@ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */ -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */ +#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */ +#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */ #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ @@ -255,8 +255,8 @@ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */ -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */ +#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */ +#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */ #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F373xC || STM32F378xx */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_def.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_def.h index 9b1070ab5ee79fee74d51643b749d23b7f275bd2..4e94b66405391c4d99c474e0f9de010f1eaee53b 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_def.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_def.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -56,9 +56,9 @@ */ typedef enum { - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; @@ -67,7 +67,7 @@ typedef enum */ typedef enum { - HAL_UNLOCKED = 0x00, + HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01 } HAL_LockTypeDef; @@ -81,7 +81,7 @@ typedef enum do{ \ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) + } while(0U) #define UNUSED(x) ((void)(x)) @@ -100,9 +100,9 @@ typedef enum * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) -#if (USE_RTOS == 1) +#if (USE_RTOS == 1U) #error " USE_RTOS should be 0 in the current HAL release " #else #define __HAL_LOCK(__HANDLE__) \ @@ -115,12 +115,12 @@ typedef enum { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ - }while (0) + }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) + }while (0U) #endif /* USE_RTOS */ #if defined ( __GNUC__ ) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma.h index db5f357d47c7a18aa19162c7eec6a34c5e6dd562..36cac319555368ea0198c30ce3ea976eda898266 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -84,43 +84,43 @@ typedef struct uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ + data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** - * @brief DMA Configuration enumeration values definition + * @brief HAL DMA State structures definition */ typedef enum { - DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ - DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ - -} DMA_ControlTypeDef; + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; /** - * @brief HAL DMA State structures definition + * @brief HAL DMA Error Code structure definition */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ -}HAL_DMA_StateTypeDef; + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; /** - * @brief HAL DMA Error Code structure definition + * @brief HAL DMA Callback ID structure definition */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ +}HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition @@ -143,9 +143,13 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ } DMA_HandleTypeDef; /** * @} @@ -160,10 +164,11 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ /** * @} */ @@ -171,7 +176,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ +#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ @@ -183,7 +188,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ +#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ /** * @} */ @@ -192,7 +197,7 @@ typedef struct __DMA_HandleTypeDef * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ +#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ /** * @} */ @@ -200,7 +205,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ /** @@ -210,7 +215,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ /** @@ -220,8 +225,8 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_mode DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ +#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ /** * @} */ @@ -229,7 +234,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Priority_level DMA Priority level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ +#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ @@ -251,34 +256,34 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) +#define DMA_FLAG_GL1 (0x00000001U) +#define DMA_FLAG_TC1 (0x00000002U) +#define DMA_FLAG_HT1 (0x00000004U) +#define DMA_FLAG_TE1 (0x00000008U) +#define DMA_FLAG_GL2 (0x00000010U) +#define DMA_FLAG_TC2 (0x00000020U) +#define DMA_FLAG_HT2 (0x00000040U) +#define DMA_FLAG_TE2 (0x00000080U) +#define DMA_FLAG_GL3 (0x00000100U) +#define DMA_FLAG_TC3 (0x00000200U) +#define DMA_FLAG_HT3 (0x00000400U) +#define DMA_FLAG_TE3 (0x00000800U) +#define DMA_FLAG_GL4 (0x00001000U) +#define DMA_FLAG_TC4 (0x00002000U) +#define DMA_FLAG_HT4 (0x00004000U) +#define DMA_FLAG_TE4 (0x00008000U) +#define DMA_FLAG_GL5 (0x00010000U) +#define DMA_FLAG_TC5 (0x00020000U) +#define DMA_FLAG_HT5 (0x00040000U) +#define DMA_FLAG_TE5 (0x00080000U) +#define DMA_FLAG_GL6 (0x00100000U) +#define DMA_FLAG_TC6 (0x00200000U) +#define DMA_FLAG_HT6 (0x00400000U) +#define DMA_FLAG_TE6 (0x00800000U) +#define DMA_FLAG_GL7 (0x01000000U) +#define DMA_FLAG_TC7 (0x02000000U) +#define DMA_FLAG_HT7 (0x04000000U) +#define DMA_FLAG_TE7 (0x08000000U) /** * @} */ @@ -302,16 +307,16 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ -#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ -#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) /* Interrupt & Flag management */ @@ -326,7 +331,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) /** * @brief Disables the specified DMA Channel interrupts. @@ -338,7 +343,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) /** * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. @@ -350,7 +355,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_IT_TE: Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. @@ -368,7 +373,7 @@ typedef struct __DMA_HandleTypeDef #include "stm32f3xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions DMA Exported Functions +/** @addtogroup DMA_Exported_Functions * @{ */ @@ -385,13 +390,15 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions * @{ */ -/* IO operation functions *****************************************************/ +/* Input and Output operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ @@ -415,7 +422,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @{ */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma_ex.h index aeb4e3e3413847c07a841929316999bf296e3793..962f6fd968563d4a04dc036965d0550cb12b4a18 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_flash.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_flash.h index 86445dbeebe9455985d77b944ddc34ca587ebd95..5ce998428e97e43f7383ace05333f021fc6c6317 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_flash.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention @@ -57,7 +57,7 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ /** * @} */ @@ -88,12 +88,12 @@ */ typedef enum { - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGEERASE = 1, - FLASH_PROC_MASSERASE = 2, - FLASH_PROC_PROGRAMHALFWORD = 3, - FLASH_PROC_PROGRAMWORD = 4, - FLASH_PROC_PROGRAMDOUBLEWORD = 5 + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U } FLASH_ProcedureTypeDef; /** @@ -139,9 +139,9 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \ - ((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \ - ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF)))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ + ((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFF)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \ - ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \ - ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF)))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ + ((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU)))) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F373xC) || defined(STM32F378xx) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF))) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU))) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU))) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ @@ -199,7 +199,7 @@ typedef struct This parameter can be a value of @ref FLASHEx_OB_Data_Address */ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ } FLASH_OBProgramInitTypeDef; /** * @} @@ -221,8 +221,8 @@ typedef struct /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ */ -#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ }\ - } while(0) + } while(0U) /** @brief Enables or disables the specified HRTIM common interrupts. * @param __HANDLE__: specifies the HRTIM Handle. diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c.h index 01ce8cb6a4868a6fe575be5079274813cf6778ea..f3710f144f3846eff3ad56b56770d8d55f5821ad 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -245,8 +245,8 @@ typedef struct __I2C_HandleTypeDef /** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options * @{ */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) #define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) @@ -658,6 +658,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_NO_STARTSTOP)) #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ ((REQUEST) == I2C_LAST_FRAME)) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c_ex.h index e8218e1ee38fd8314b2dd7e9ddfcf70ef2ce909d..db9c17f82f9f57ca95f5c8c8c54792f9e75a4ce9 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup I2CEx I2CEx +/** @addtogroup I2CEx * @{ */ @@ -64,8 +64,8 @@ /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ @@ -73,33 +73,22 @@ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ -#if defined(SYSCFG_CFGR1_I2C_PB6_FMP) -#define I2C_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast Mode Plus on PB6 */ -#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */ - -#if defined(SYSCFG_CFGR1_I2C_PB7_FMP) -#define I2C_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast Mode Plus on PB7 */ -#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */ - -#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) -#define I2C_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast Mode Plus on PB8 */ -#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ - -#if defined(SYSCFG_CFGR1_I2C_PB9_FMP) -#define I2C_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast Mode Plus on PB9 */ -#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ - -#if defined(SYSCFG_CFGR1_I2C1_FMP) -#define I2C_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< Enable Fast Mode Plus on I2C1 pins */ -#endif /* SYSCFG_CFGR1_I2C1_FMP */ - +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ #if defined(SYSCFG_CFGR1_I2C2_FMP) -#define I2C_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< Enable Fast Mode Plus on I2C2 pins */ -#endif /* SYSCFG_CFGR1_I2C2_FMP */ - +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif #if defined(SYSCFG_CFGR1_I2C3_FMP) -#define I2C_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< Enable Fast Mode Plus on I2C3 pins */ -#endif /* SYSCFG_CFGR1_I2C3_FMP */ +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /** * @} */ @@ -123,8 +112,8 @@ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); @@ -142,33 +131,18 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) - - -#if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) -#elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) -#elif defined(SYSCFG_CFGR1_I2C1_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) -#endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) /** * @} */ @@ -198,12 +172,10 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ - #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_I2C_EX_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s.h index d3f4c6a85514f95aae4ea934e680f3424ba9dbfd..43d34b91c4a688a05868fd0e969478c36e4a7d61 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -100,13 +100,13 @@ typedef struct */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */ }HAL_I2S_StateTypeDef; @@ -159,12 +159,12 @@ typedef struct /** @defgroup I2S_Error I2S Error * @{ */ -#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ -#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */ -#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */ -#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */ -#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */ +#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ +#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ +#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ +#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */ /** * @} */ @@ -172,8 +172,8 @@ typedef struct /** @defgroup I2S_Clock_Source I2S Clock Source * @{ */ -#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) -#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002) +#define I2S_CLOCK_EXTERNAL (0x00000001U) +#define I2S_CLOCK_SYSCLK (0x00000002U) #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ ((CLOCK) == I2S_CLOCK_SYSCLK)) @@ -184,10 +184,10 @@ typedef struct /** @defgroup I2S_Mode I2S Mode * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) -#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) -#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) +#define I2S_MODE_SLAVE_TX (0x00000000U) +#define I2S_MODE_SLAVE_RX (0x00000100U) +#define I2S_MODE_MASTER_TX (0x00000200U) +#define I2S_MODE_MASTER_RX (0x00000300U) #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ ((MODE) == I2S_MODE_SLAVE_RX) || \ @@ -200,11 +200,11 @@ typedef struct /** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) -#define I2S_STANDARD_MSB ((uint32_t)0x00000010) -#define I2S_STANDARD_LSB ((uint32_t)0x00000020) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) -#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) +#define I2S_STANDARD_PHILIPS (0x00000000U) +#define I2S_STANDARD_MSB (0x00000010U) +#define I2S_STANDARD_LSB (0x00000020U) +#define I2S_STANDARD_PCM_SHORT (0x00000030U) +#define I2S_STANDARD_PCM_LONG (0x000000B0U) #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ ((STANDARD) == I2S_STANDARD_MSB) || \ @@ -218,10 +218,10 @@ typedef struct /** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) -#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) -#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) +#define I2S_DATAFORMAT_16B (0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U) +#define I2S_DATAFORMAT_24B (0x00000003U) +#define I2S_DATAFORMAT_32B (0x00000005U) #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ @@ -235,7 +235,7 @@ typedef struct * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) @@ -246,16 +246,16 @@ typedef struct /** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) +#define I2S_AUDIOFREQ_192K (192000U) +#define I2S_AUDIOFREQ_96K (96000U) +#define I2S_AUDIOFREQ_48K (48000U) +#define I2S_AUDIOFREQ_44K (44100U) +#define I2S_AUDIOFREQ_32K (32000U) +#define I2S_AUDIOFREQ_22K (22050U) +#define I2S_AUDIOFREQ_16K (16000U) +#define I2S_AUDIOFREQ_11K (11025U) +#define I2S_AUDIOFREQ_8K (8000U) +#define I2S_AUDIOFREQ_DEFAULT (2U) #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ @@ -267,8 +267,8 @@ typedef struct /** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode * @{ */ -#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000) -#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001) +#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U) +#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U) #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) @@ -279,7 +279,7 @@ typedef struct /** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_LOW (0x00000000U) #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ @@ -384,7 +384,7 @@ typedef struct tmpreg = (__HANDLE__)->Instance->DR; \ tmpreg = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg); \ - }while(0) + }while(0U) /** @brief Clears the I2S UDR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None @@ -393,7 +393,7 @@ typedef struct __IO uint32_t tmpreg;\ tmpreg = ((__HANDLE__)->Instance->SR);\ UNUSED(tmpreg); \ - }while(0) + }while(0U) /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s_ex.h index 3d33fa6f78d8e0ca1f782b7883b67519ac47597d..48ac73fd3ffb5c82ded10dbb72e34c8436e07dde 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_i2s_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of I2S HAL Extended module. ****************************************************************************** * @attention @@ -119,7 +119,7 @@ * @retval None */ #define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\ - (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0) + (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U) /** @brief Clears the I2SExt UDR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda.h index 8fbd02505c9fb2386cf52978dcd45510a68f0c01..cb496d54c2432eb6c2fe389beb1b8c7bd6fcd0c1 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_irda.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** @@ -155,12 +155,12 @@ typedef enum */ typedef enum { - IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }IRDA_ClockSourceTypeDef; /** @@ -168,7 +168,7 @@ typedef enum */ typedef struct { - USART_TypeDef *Instance; /*!< USART registers base address */ + USART_TypeDef *Instance; /*!< IRDA registers base address */ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ @@ -176,15 +176,15 @@ typedef struct uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ - uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ - uint16_t Mask; /*!< USART RX RDR register mask */ + uint16_t Mask; /*!< IRDA RX RDR register mask */ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ @@ -209,12 +209,12 @@ typedef struct */ typedef enum { - IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */ - IRDA_PARITY = 0x01, /*!< IRDA frame parity */ - IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */ - IRDA_MODE = 0x03, /*!< IRDA communication mode */ - IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */ - IRDA_POWERMODE = 0x05 /*!< IRDA power mode */ + IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */ + IRDA_PARITY = 0x01U, /*!< IRDA frame parity */ + IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */ + IRDA_MODE = 0x03U, /*!< IRDA communication mode */ + IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */ + IRDA_POWERMODE = 0x05U /*!< IRDA power mode */ }IRDA_ControlTypeDef; /** @@ -229,12 +229,13 @@ typedef enum /** @defgroup IRDA_Error IRDA Error * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ /** * @} */ @@ -242,7 +243,7 @@ typedef enum /** @defgroup IRDA_Parity IRDA Parity * @{ */ -#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */ #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** @@ -262,7 +263,7 @@ typedef enum /** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */ #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */ /** * @} @@ -271,7 +272,7 @@ typedef enum /** @defgroup IRDA_State IRDA State * @{ */ -#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */ +#define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */ #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */ /** * @} @@ -280,7 +281,7 @@ typedef enum /** @defgroup IRDA_Mode IRDA Mode * @{ */ -#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */ +#define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */ #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */ /** * @} @@ -289,7 +290,7 @@ typedef enum /** @defgroup IRDA_One_Bit IRDA One Bit Sampling * @{ */ -#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */ +#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */ #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */ /** * @} @@ -298,7 +299,7 @@ typedef enum /** @defgroup IRDA_DMA_Tx IRDA DMA Tx * @{ */ -#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */ #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */ /** * @} @@ -307,7 +308,7 @@ typedef enum /** @defgroup IRDA_DMA_Rx IRDA DMA Rx * @{ */ -#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */ +#define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */ #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */ /** * @} @@ -316,8 +317,8 @@ typedef enum /** @defgroup IRDA_Request_Parameters IRDA Request Parameters * @{ */ -#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ #define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ /** * @} @@ -328,18 +329,18 @@ typedef enum * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */ -#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */ -#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */ -#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */ -#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */ -#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */ -#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */ -#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */ -#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */ -#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */ -#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */ -#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */ +#define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */ +#define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */ +#define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */ +#define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */ +#define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */ +#define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */ +#define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */ +#define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */ +#define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */ +#define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */ +#define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */ +#define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */ /** * @} */ @@ -354,27 +355,15 @@ typedef enum * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */ -#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */ -#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */ -#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */ -#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */ - -/** Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - */ -#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */ - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ -#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */ -#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */ -#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */ +#define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */ +#define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */ +#define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */ +#define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */ +#define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */ +#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */ +#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */ /** * @} */ @@ -382,10 +371,11 @@ typedef enum /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags * @{ */ -#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ /** * @} @@ -394,7 +384,7 @@ typedef enum /** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask * @{ */ -#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */ +#define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */ /** * @} */ @@ -416,9 +406,9 @@ typedef enum #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ - } while(0) + } while(0U) -/** @brief Flush the IRDA Data registers. +/** @brief Flush the IRDA DR register. * @param __HANDLE__: specifies the IRDA Handle. * @retval None */ @@ -426,18 +416,18 @@ typedef enum do{ \ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__: specifies the IRDA Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: - * @arg IRDA_CLEAR_PEF - * @arg IRDA_CLEAR_FEF - * @arg IRDA_CLEAR_NEF - * @arg IRDA_CLEAR_OREF - * @arg IRDA_CLEAR_TCF - * @arg IRDA_CLEAR_IDLEF + * @arg @ref IRDA_CLEAR_PEF + * @arg @ref IRDA_CLEAR_FEF + * @arg @ref IRDA_CLEAR_NEF + * @arg @ref IRDA_CLEAR_OREF + * @arg @ref IRDA_CLEAR_TCF + * @arg @ref IRDA_CLEAR_IDLEF * @retval None */ #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -475,23 +465,20 @@ typedef enum /** @brief Check whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag - * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag - * @arg IRDA_FLAG_BUSY: Busy flag - * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag - * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag - * @arg IRDA_FLAG_TXE: Transmit data register empty flag - * @arg IRDA_FLAG_TC: Transmission Complete flag - * @arg IRDA_FLAG_RXNE: Receive data register not empty flag - * @arg IRDA_FLAG_IDLE: Idle Line detection flag - * @arg IRDA_FLAG_ORE: OverRun Error flag - * @arg IRDA_FLAG_NE: Noise Error flag - * @arg IRDA_FLAG_FE: Framing Error flag - * @arg IRDA_FLAG_PE: Parity Error flag + * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag + * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref IRDA_FLAG_BUSY Busy flag + * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag + * @arg @ref IRDA_FLAG_TC Transmission Complete flag + * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag + * @arg @ref IRDA_FLAG_ORE OverRun Error flag + * @arg @ref IRDA_FLAG_NE Noise Error flag + * @arg @ref IRDA_FLAG_FE Framing Error flag + * @arg @ref IRDA_FLAG_PE Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) @@ -499,91 +486,79 @@ typedef enum /** @brief Enable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_PE: Parity Error interrupt - * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_PE: Parity Error interrupt - * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __IT__: specifies the IRDA interrupt source to check. * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_ORE: OverRun Error interrupt - * @arg IRDA_IT_NE: Noise Error interrupt - * @arg IRDA_IT_FE: Framing Error interrupt - * @arg IRDA_IT_PE: Parity Error interrupt + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ORE OverRun Error interrupt + * @arg @ref IRDA_IT_NE Noise Error interrupt + * @arg @ref IRDA_IT_FE Framing Error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) +#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __IT__: specifies the IRDA interrupt source to check. * This parameter can be one of the following values: - * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt - * @arg IRDA_IT_TC: Transmission complete interrupt - * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt - * @arg IRDA_IT_IDLE: Idle line detection interrupt - * @arg IRDA_IT_ORE: OverRun Error interrupt - * @arg IRDA_IT_NE: Noise Error interrupt - * @arg IRDA_IT_FE: Framing Error interrupt - * @arg IRDA_IT_PE: Parity Error interrupt + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag - * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag - * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag - * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag - * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag + * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag + * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag + * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag + * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag + * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) @@ -591,13 +566,11 @@ typedef enum /** @brief Set a specific IRDA request flag. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @param __REQ__: specifies the request flag to set * This parameter can be one of the following values: - * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request - * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request * * @retval None */ @@ -605,32 +578,24 @@ typedef enum /** @brief Enable the IRDA one bit sample method. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disable the IRDA one bit sample method. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @retval None */ #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle. * @param __HANDLE__: specifies the IRDA Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -648,13 +613,13 @@ typedef enum * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. * @retval True or False */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) /** @brief Ensure that IRDA prescaler value is strictly larger than 0. * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. * @retval True or False */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) /** * @brief Ensure that IRDA frame parity is valid. @@ -670,7 +635,7 @@ typedef enum * @param __MODE__: IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that IRDA power mode is valid. @@ -717,8 +682,8 @@ typedef enum * @param __DMARX__: IRDA DMA RX mode. * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) */ -#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ - ((__DMARX__) == IRDA_DMA_RX_ENABLE)) +#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ + ((__DMARX__) == IRDA_DMA_RX_ENABLE)) /** * @brief Ensure that IRDA request is valid. @@ -768,12 +733,23 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); + void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda); /** * @} @@ -804,6 +780,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); /** * @} */ + #ifdef __cplusplus } #endif diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda_ex.h index 6c54765dae7eaac26c7b12c427a5b6bd763b53ac..68da807a9c85a4883d0da23d1bea315347b6047e 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_irda_ex.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f3xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 - * @brief Header file of IRDA HAL Extension module. + * @version V1.4.0 + * @date 16-December-2016 + * @brief Header file of IRDA HAL Extended module. ****************************************************************************** * @attention * @@ -50,8 +50,7 @@ * @{ */ -/** @defgroup IRDAEx IRDAEx - * @brief IRDA Extension HAL module driver. +/** @addtogroup IRDAEx * @{ */ @@ -68,10 +67,10 @@ defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */ -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */ #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */ #else -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */ #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F334x8 || */ @@ -100,7 +99,7 @@ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) -#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -211,10 +210,10 @@ { \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -249,7 +248,7 @@ { \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #else #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ @@ -320,7 +319,7 @@ { \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ @@ -331,74 +330,74 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the IRDA Handle - * @retval None, the mask to apply to IRDA RDR register is stored in (__HANDLE__)->Mask field. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ defined(STM32F334x8) -#define IRDA_MASK_COMPUTATION(__HANDLE__) \ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ -} while(0) +} while(0U) #else -#define IRDA_MASK_COMPUTATION(__HANDLE__) \ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ -} while(0) +} while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F334x8 */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_iwdg.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_iwdg.h index 8203036b4f03ebd7066fe7cbb893d1a9c541c82e..e589d021f9ee4ee8b2790d1a37e7569f5f1241ad 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_iwdg.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_iwdg.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -68,10 +68,10 @@ typedef struct This parameter can be a value of @ref IWDG_Prescaler */ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */ } IWDG_InitTypeDef; @@ -103,8 +103,8 @@ typedef struct #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128U */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256U */ /** * @} */ @@ -250,6 +250,6 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); } #endif -#endif /* __STM32L4xx_HAL_IWDG_H */ +#endif /* __STM32F3xx_HAL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nand.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nand.h index 82765109247b1ccbaf07f93ade67ed5bb65d20d5..3d0d40ade27cf11ea50e83d82ec972cbdd6783f7 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nand.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nand.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -61,32 +61,32 @@ #define NAND_DEVICE1 FMC_BANK2 #define NAND_DEVICE2 FMC_BANK3 -#define NAND_WRITE_TIMEOUT ((uint32_t)1000) +#define NAND_WRITE_TIMEOUT (1000U) -#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ +#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16U = CLE high */ +#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17U = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) +#define NAND_VALID_ADDRESS (0x00000100U) +#define NAND_INVALID_ADDRESS (0x00000200U) +#define NAND_TIMEOUT_ERROR (0x00000400U) +#define NAND_BUSY (0x00000000U) +#define NAND_ERROR (0x00000001U) +#define NAND_READY (0x00000040U) /** * @} @@ -111,9 +111,9 @@ * @retval NAND address cycling value. */ #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ -#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ -#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ -#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ +#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */ /** * @} @@ -130,9 +130,9 @@ */ typedef enum { - HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ }HAL_NAND_StateTypeDef; diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nor.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nor.h index 300c450460c1d0fc050d2829998701d8a6ab612a..6d271127a7d75f3cfe5fe832562aa1ec78db531c 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nor.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nor.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -61,20 +61,20 @@ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x10) -#define CFI2_ADDRESS ((uint16_t)0x11) -#define CFI3_ADDRESS ((uint16_t)0x12) -#define CFI4_ADDRESS ((uint16_t)0x13) +#define CFI1_ADDRESS ((uint16_t)0x10U) +#define CFI2_ADDRESS ((uint16_t)0x11U) +#define CFI3_ADDRESS ((uint16_t)0x12U) +#define CFI4_ADDRESS ((uint16_t)0x13U) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) /* NOR memory device read/write start address */ #define NOR_MEMORY_ADRESS1 FMC_BANK1_1 @@ -99,7 +99,7 @@ */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) /** @@ -124,10 +124,10 @@ */ typedef enum { - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ }HAL_NOR_StateTypeDef; @@ -136,7 +136,7 @@ typedef enum */ typedef enum { - HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp.h index 8f5e5071f996550705130846da9bbb1d96ff000e..49525a543541b23fde6a1d9163eb7759bab0c5a9 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of OPAMP HAL module. ****************************************************************************** * @attention @@ -113,7 +113,7 @@ typedef struct uint32_t PgaGain; /*!< Specifies the gain in PGA mode i.e. when mode is OPAMP_PGA_MODE. - This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */ + This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */ uint32_t UserTrimming; /*!< Specifies the trimming mode This parameter must be a value of @ref OPAMP_UserTrimming @@ -121,11 +121,11 @@ typedef struct uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 31U */ uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) i.e. when UserTrimming is OPAMP_TRIMMING_USER. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 31U */ }OPAMP_InitTypeDef; @@ -135,13 +135,13 @@ typedef struct typedef enum { - HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */ + HAL_OPAMP_STATE_RESET = 0x00000000U, /*!< OPMAP is not yet Initialized */ - HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */ - HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */ + HAL_OPAMP_STATE_READY = 0x00000001U, /*!< OPAMP is initialized and ready for use */ + HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */ - HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */ - HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked + HAL_OPAMP_STATE_BUSY = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */ + HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U, /*!< OPAMP is locked only system reset allows reconfiguring the opamp. */ }HAL_OPAMP_StateTypeDef; @@ -189,7 +189,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_Mode OPAMP Mode * @{ */ -#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */ +#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< standalone mode */ #define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */ #define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */ @@ -208,7 +208,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4) connected to OPAMPx non inverting input */ -#define OPAMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4) +#define OPAMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4) connected to OPAMPx non inverting input */ #define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4) connected to OPAMPx non inverting input */ @@ -228,7 +228,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */ +#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< inverting input connected to VM0 */ #define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */ #define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \ @@ -241,7 +241,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode * @{ */ - #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE ((uint32_t)0x00000000) /*!< Timer controlled Mux mode disabled */ + #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U) /*!< Timer controlled Mux mode disabled */ #define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */ #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \ @@ -256,7 +256,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; #define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4) connected to OPAMPx non inverting input */ -#define OPAMP_SEC_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4) +#define OPAMP_SEC_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4) connected to OPAMPx non inverting input */ #define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4) connected to OPAMPx non inverting input */ @@ -276,7 +276,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_SEC_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4) +#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000U) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4) connected to OPAMPx inverting input */ #define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4) connected to OPAMPx inverting input */ @@ -292,7 +292,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */ +#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000U) /*!< In PGA mode, the non inverting input is not connected */ #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */ #define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */ @@ -308,10 +308,10 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */ -#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */ -#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */ -#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */ +#define OPAMP_PGA_GAIN_2 (0x00000000U) /*!< PGA gain = 2U */ +#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4U */ +#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8U */ +#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16U */ #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \ ((GAIN) == OPAMP_PGA_GAIN_4) || \ @@ -325,7 +325,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */ +#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */ #define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */ #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ @@ -335,10 +335,10 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFFU) /*!< Dummy trimming value */ +#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy trimming value */ -#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */ -#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */ +#define OPAMP_FACTORYTRIMMING_N (0x00000000U) /*!< Offset trimming N */ +#define OPAMP_FACTORYTRIMMING_P (0x00000001U) /*!< Offset trimming P */ #define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P)) @@ -352,7 +352,7 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F) +#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) /** @@ -364,8 +364,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_INPUT_INVERTING ((uint32_t) 24) /*!< Inverting input */ -#define OPAMP_INPUT_NONINVERTING ((uint32_t) 19) /*!< Non inverting input */ +#define OPAMP_INPUT_INVERTING ( 24U) /*!< Inverting input */ +#define OPAMP_INPUT_NONINVERTING ( 19U) /*!< Non inverting input */ #define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \ ((INPUT) == OPAMP_INPUT_NONINVERTING)) @@ -378,10 +378,10 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; * @{ */ -#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */ -#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */ -#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */ -#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */ +#define OPAMP_VREF_3VDDA (0x00000000U) /*!< OPMAP Vref = 3.3U% VDDA */ +#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10U% VDDA */ +#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50U% VDDA */ +#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90U% VDDA */ #define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \ ((VREF) == OPAMP_VREF_10VDDA) || \ @@ -395,8 +395,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; /** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib */ -#define OPAMP_VREF_NOTCONNECTEDTO_ADC ((uint32_t)0x00000000) /*!< VREF not connected to ADC */ -#define OPAMP_VREF_CONNECTEDTO_ADC ((uint32_t)0x00000001) /*!< VREF not connected to ADC */ +#define OPAMP_VREF_NOTCONNECTEDTO_ADC (0x00000000U) /*!< VREF not connected to ADC */ +#define OPAMP_VREF_CONNECTEDTO_ADC (0x00000001U) /*!< VREF not connected to ADC */ #define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \ ((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC)) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp_ex.h index 65c2198960c8fec8f55fc4d26ccf287d27f55512..72d9846dec48e113c21326c6b7e20cfdc2894047 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_opamp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of OPAMP HAL Extended module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pccard.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pccard.h index c40c211fb82e905ef7b796a9265cae470e6835fb..ef05af3e0cbc4862dfb263e7253f08ce2ad3fa68 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pccard.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pccard.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention @@ -60,36 +60,36 @@ */ #define PCCARD_DEVICE_ADDRESS FMC_BANK4 -#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */ +#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */ #define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */ -#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */ -#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */ /* Compact Flash-ATA registers description */ -#define ATA_DATA ((uint8_t)0x00) /* Data register */ -#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */ -#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */ -#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */ -#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */ -#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */ -#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */ -#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */ -#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */ -#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */ +#define ATA_DATA ((uint8_t)0x00U) /* Data register */ +#define ATA_SECTOR_COUNT ((uint8_t)0x02U) /* Sector Count register */ +#define ATA_SECTOR_NUMBER ((uint8_t)0x03U) /* Sector Number register */ +#define ATA_CYLINDER_LOW ((uint8_t)0x04U) /* Cylinder low register */ +#define ATA_CYLINDER_HIGH ((uint8_t)0x05U) /* Cylinder high register */ +#define ATA_CARD_HEAD ((uint8_t)0x06U) /* Card/Head register */ +#define ATA_STATUS_CMD ((uint8_t)0x07U) /* Status(read)/Command(write) register */ +#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0EU) /* Alternate Status(read)/Command(write) register */ +#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */ +#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202U) /* Card Configuration and Status Register */ /* Compact Flash-ATA commands */ -#define ATA_READ_SECTOR_CMD ((uint8_t)0x20) -#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30) -#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0) -#define ATA_IDENTIFY_CMD ((uint8_t)0xEC) +#define ATA_READ_SECTOR_CMD ((uint8_t)0x20U) +#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30U) +#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0U) +#define ATA_IDENTIFY_CMD ((uint8_t)0xECU) /* Compact Flash status */ -#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60) -#define PCCARD_BUSY ((uint8_t)0x80) -#define PCCARD_PROGR ((uint8_t)0x01) -#define PCCARD_READY ((uint8_t)0x40) +#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60U) +#define PCCARD_BUSY ((uint8_t)0x80U) +#define PCCARD_PROGR ((uint8_t)0x01U) +#define PCCARD_READY ((uint8_t)0x40U) -#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */ +#define PCCARD_SECTOR_SIZE (255U) /* In half words */ /* Compact Flash redefinition */ @@ -136,15 +136,15 @@ */ typedef enum { - HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */ - HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */ - HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */ + HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */ + HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */ + HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */ }HAL_PCCARD_StateTypeDef; typedef enum { - HAL_PCCARD_STATUS_SUCCESS = 0, + HAL_PCCARD_STATUS_SUCCESS = 0U, HAL_PCCARD_STATUS_ONGOING, HAL_PCCARD_STATUS_ERROR, HAL_PCCARD_STATUS_TIMEOUT diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd.h index db362d02b3e5f7ecc110cffbf542408728fc34e9..ee5feefee03558a44ddc7ef8bf51293a1c90a5a4 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -69,11 +69,11 @@ */ typedef enum { - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U } PCD_StateTypeDef; /** @@ -203,8 +203,8 @@ typedef struct /** @defgroup PCD_Core_Speed PCD Core Speed * @{ */ -#define PCD_SPEED_HIGH 0 /* Not Supported */ -#define PCD_SPEED_FULL 2 +#define PCD_SPEED_HIGH 0U /* Not Supported */ +#define PCD_SPEED_FULL 2U /** * @} */ @@ -212,7 +212,7 @@ typedef struct /** @defgroup PCD_Core_PHY PCD Core PHY * @{ */ -#define PCD_PHY_EMBEDDED 2 +#define PCD_PHY_EMBEDDED 2U /** * @} */ @@ -226,7 +226,7 @@ typedef struct * @{ */ #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) @@ -238,19 +238,19 @@ typedef struct #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\ - } while(0) + } while(0U) #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\ - } while(0) + } while(0U) #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\ EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\ - } while(0) + } while(0U) /** * @} */ @@ -345,10 +345,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U #define PCD_EP0MPS_64 DEP0CTL_MPS_64 #define PCD_EP0MPS_32 DEP0CTL_MPS_32 @@ -361,10 +361,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_EP_Type PCD EP Type * @{ */ -#define PCD_EP_TYPE_CTRL 0 -#define PCD_EP_TYPE_ISOC 1 -#define PCD_EP_TYPE_BULK 2 -#define PCD_EP_TYPE_INTR 3 +#define PCD_EP_TYPE_CTRL 0U +#define PCD_EP_TYPE_ISOC 1U +#define PCD_EP_TYPE_BULK 2U +#define PCD_EP_TYPE_INTR 3U /** * @} */ @@ -372,14 +372,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_ENDP PCD ENDP * @{ */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) +#define PCD_ENDP0 ((uint8_t)0U) +#define PCD_ENDP1 ((uint8_t)1U) +#define PCD_ENDP2 ((uint8_t)2U) +#define PCD_ENDP3 ((uint8_t)3U) +#define PCD_ENDP4 ((uint8_t)4U) +#define PCD_ENDP5 ((uint8_t)5U) +#define PCD_ENDP6 ((uint8_t)6U) +#define PCD_ENDP7 ((uint8_t)7U) /** * @} */ @@ -387,8 +387,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind * @{ */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U /** * @} */ @@ -404,10 +404,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))) @@ -419,7 +419,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) + ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) ))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -427,7 +427,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval Endpoint Type */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) +#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD) /** @@ -459,9 +459,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #define PCD_GET_DB_DIR(USBx, bEpNum)\ {\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ + if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\ return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ + else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\ return(PCD_EP_DBUF_IN);\ else\ return(PCD_EP_DBUF_ERR);\ @@ -474,17 +474,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState: new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\ - register uint16_t _wRegVal; \ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0) \ - _wRegVal ^= USB_EPTX_DTOG1; \ + if((USB_EPTX_DTOG1 & (wState))!= 0U)\ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - _wRegVal ^= USB_EPTX_DTOG2; \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\ } /* PCD_SET_EP_TX_STATUS */ /** @@ -497,14 +500,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ register uint16_t _wRegVal; \ \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ + _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - _wRegVal ^= USB_EPRX_DTOG1; \ + if((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - _wRegVal ^= USB_EPRX_DTOG2; \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ + if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \ + { \ + _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ } /* PCD_SET_EP_RX_STATUS */ /** @@ -520,17 +527,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \ + { \ _wRegVal ^= USB_EPRX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ _wRegVal ^= USB_EPRX_DTOG2; \ + } \ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG1; \ + } \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG2; \ + } \ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ } /* PCD_SET_EP_TXRX_STATUS */ @@ -541,9 +556,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval status */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) - -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT) /** * @brief sets directly the VALID tx/rx-status into the endpoint register @@ -573,9 +587,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK)))) #define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) + (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))) /** * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. @@ -602,9 +616,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. @@ -613,9 +627,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) #define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) + USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK))) /** * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. @@ -623,10 +637,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - PCD_RX_DTOG((USBx), (bEpNum)) -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - PCD_TX_DTOG((USBx), (bEpNum)) +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\ + { \ + PCD_RX_DTOG((USBx),(bEpNum));\ + } +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\ + {\ + PCD_TX_DTOG((USBx),(bEpNum));\ + } /** * @brief Sets address in an endpoint register. @@ -636,7 +654,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) + USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr)) /** * @brief Gets address in an endpoint register. @@ -653,8 +671,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wAddr: address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) /** * @brief Gets address of the tx/rx buffer. @@ -673,29 +691,41 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ + (wNBlocks) = (wCount) >> 5U;\ + if(((wCount) & 0x1fU) == 0U)\ + { \ (wNBlocks)--;\ - *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\ + } \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \ }/* PCD_CALC_BLK32 */ + #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ + (wNBlocks) = (wCount) >> 1U;\ + if(((wCount) & 0x1U) != 0U)\ + { \ (wNBlocks)++;\ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ + } \ + *pdwReg = (uint16_t)((wNBlocks) << 10U);\ }/* PCD_CALC_BLK2 */ #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ uint16_t wNBlocks;\ - if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\ - else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\ + if((wCount) > 62U) \ + { \ + PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \ + } \ + else \ + { \ + PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \ + } \ }/* PCD_SET_EP_CNT_RX_REG */ #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint32_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\ + uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\ } + /** * @brief sets counter for the tx/rx buffer. * @param USBx: USB peripheral instance register address. @@ -711,8 +741,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval Counter value */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) /** * @brief Sets buffer 0/1 address in a double buffer endpoint. @@ -721,8 +751,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf0Addr: buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr))) +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr))) /** * @brief Sets addresses in a double buffer endpoint. @@ -758,25 +788,28 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ if((bDir) == PCD_EP_DBUF_OUT)\ /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ + {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \ else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ + { \ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ } /* SetEPDblBuf0Count*/ #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\ + {/* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \ + } \ else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */\ + {/* IN endpoint */ \ *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + } \ } /* SetEPDblBuf1Count */ #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \ + } / /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd_ex.h index 517b444da4cdf7aff81bdce0c087c95c9a75d2d5..94f42d330f886a56019d66b1df7699d1f016cdec 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention @@ -75,14 +75,15 @@ #if defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F373xC) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8)*2+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+2)*2+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+4)*2+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+6)*2+ ((uint32_t)USBx + 0x400))) +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U))))) + #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint32_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\ + uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \ + PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ } #endif /* STM32F302xC || STM32F303xC || */ @@ -92,14 +93,14 @@ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302x8) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400))) +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U))))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U))))) #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\ + uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\ + PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\ } #endif /* STM32F302xE || STM32F303xE || */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr.h index 4e0dc236d0513b051de955059eaa96ff4dad5a31..c9003d721eccc8bc1ab2fb422d773dc646379202 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -64,9 +64,9 @@ * @{ */ -#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1 */ -#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2 */ -#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3 */ +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */ +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */ +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */ /** * @} */ @@ -74,7 +74,7 @@ /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Voltage regulator on during STOP mode */ +#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */ #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */ /** * @} @@ -83,8 +83,8 @@ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter SLEEP mode */ -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter SLEEP mode */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */ /** * @} */ @@ -92,8 +92,8 @@ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter STOP mode */ -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter STOP mode */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */ /** * @} */ @@ -144,7 +144,7 @@ * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) /** * @} diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr_ex.h index bdf8b9180a7425286b8429e7abcfc9e6cb4edc19..2ab9bc4b8e220856e9a415bd037a8763b9b38c98 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention @@ -114,13 +114,13 @@ typedef struct /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -137,9 +137,9 @@ typedef struct /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx * @{ */ -#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN) /*!< Enable SDADC1 */ -#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN) /*!< Enable SDADC2 */ -#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN) /*!< Enable SDADC3 */ +#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */ +#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */ +#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc.h index cbc2fad2a511a1e6c87702f9376bc3f35ea01f96..aaeb59cbdf1e50583774d493d0908e9c61d045bf 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -68,9 +68,9 @@ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ /** * @} */ @@ -102,63 +102,63 @@ /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) -#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) /* Alias word address of HSEON bit */ #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) -#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) /* Alias word address of CSSON bit */ #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) -#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) /* Alias word address of PLLON bit */ #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) -#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) -#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) /* Alias word address of RMVF bit */ #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) -#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) /* --- BDCR Registers ---*/ /* Alias word address of LSEON bit */ #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) -#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) /* Alias word address of LSEON bit */ #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) -#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) /* Alias word address of RTCEN bit */ #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) -#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) /* Alias word address of BDRST bit */ #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) -#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4))) +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) /** * @} */ /* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) /* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) /* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) /* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1) -#define BDCR_REG_INDEX ((uint8_t)2) -#define CSR_REG_INDEX ((uint8_t)3) -#define CFGR_REG_INDEX ((uint8_t)4) +#define CR_REG_INDEX ((uint8_t)1U) +#define BDCR_REG_INDEX ((uint8_t)2U) +#define CSR_REG_INDEX ((uint8_t)3U) +#define CFGR_REG_INDEX ((uint8_t)4U) -#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define RCC_FLAG_MASK ((uint8_t)0x1FU) /** * @} @@ -179,7 +179,7 @@ #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) @@ -307,7 +307,7 @@ typedef struct This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ @@ -365,11 +365,11 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) /** * @} */ @@ -377,7 +377,7 @@ typedef struct /** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** @@ -387,7 +387,7 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ @@ -398,10 +398,10 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ /** * @} @@ -410,7 +410,7 @@ typedef struct /** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** @@ -420,9 +420,9 @@ typedef struct /** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ -#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ -#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ /** * @} @@ -431,10 +431,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ /** * @} @@ -620,7 +620,7 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000) +#define RCC_MCO1 (0x00000000U) #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** @@ -651,29 +651,29 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ #if defined(RCC_CSR_V18PWRRSTF) -#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) #endif -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ /* Flags in the CFGR register */ #if defined(RCC_CFGR_MCOF) -#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ +#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ #endif /* RCC_CFGR_MCOF */ /** @@ -703,70 +703,70 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) @@ -795,56 +795,56 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) @@ -871,35 +871,35 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) @@ -1167,7 +1167,7 @@ typedef struct CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1215,7 +1215,7 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1679,10 +1679,10 @@ typedef struct @endif * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX) ? RCC->CR : \ - (((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \ - (((__FLAG__) >> 5) == CFGR_REG_INDEX)? RCC->CFGR : \ - RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \ + RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) /** * @} @@ -1720,6 +1720,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); void HAL_RCC_DisableCSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); @@ -1728,12 +1732,6 @@ uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc_ex.h index e90aa87ec5ddfc3bc2c940473989f8cfe7d833fd..98e09ad55df424db8cbb2569a6e07f6a600d363b 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -983,213 +983,213 @@ typedef struct * @{ */ #if defined(STM32F301x8) || defined(STM32F318xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000) -#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_I2C3 (0x00008000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_TIM15 (0x00040000U) +#define RCC_PERIPHCLK_TIM16 (0x00080000U) +#define RCC_PERIPHCLK_TIM17 (0x00100000U) #endif /* STM32F301x8 || STM32F318xx */ #if defined(STM32F302x8) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000) -#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_I2C3 (0x00008000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_TIM15 (0x00040000U) +#define RCC_PERIPHCLK_TIM16 (0x00080000U) +#define RCC_PERIPHCLK_TIM17 (0x00100000U) #endif /* STM32F302x8 */ #if defined(STM32F302xC) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F302xC */ #if defined(STM32F303xC) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F303xC */ #if defined(STM32F302xE) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) #endif /* STM32F302xE */ #if defined(STM32F303xE) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) -#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) +#define RCC_PERIPHCLK_TIM20 (0x02000000U) #endif /* STM32F303xE */ #if defined(STM32F398xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) -#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) -#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) -#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) -#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) -#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) -#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) +#define RCC_PERIPHCLK_TIM20 (0x02000000U) #endif /* STM32F398xx */ #if defined(STM32F358xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F358xx */ #if defined(STM32F303x8) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F303x8 */ #if defined(STM32F334x8) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_HRTIM1 (0x00004000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F334x8 */ #if defined(STM32F328xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F328xx */ #if defined(STM32F373xC) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) -#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_SDADC (0x00000800U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F373xC */ #if defined(STM32F378xx) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) -#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) -#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_SDADC (0x00000800U) +#define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F378xx */ /** @@ -1711,23 +1711,23 @@ typedef struct /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler * @{ */ -#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1 -#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2 -#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4 -#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6 -#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8 -#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10 -#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12 -#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14 -#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16 -#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20 -#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24 -#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28 -#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32 -#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36 -#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40 -#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44 -#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48 +#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1 +#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2 +#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4 +#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6 +#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8 +#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10 +#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12 +#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14 +#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16 +#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20 +#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24 +#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28 +#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32 +#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36 +#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40 +#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44 +#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48 /** * @} @@ -1761,18 +1761,18 @@ typedef struct */ #if defined(RCC_CFGR_MCOPRE) -#define RCC_MCODIV_1 ((uint32_t)0x00000000) -#define RCC_MCODIV_2 ((uint32_t)0x10000000) -#define RCC_MCODIV_4 ((uint32_t)0x20000000) -#define RCC_MCODIV_8 ((uint32_t)0x30000000) -#define RCC_MCODIV_16 ((uint32_t)0x40000000) -#define RCC_MCODIV_32 ((uint32_t)0x50000000) -#define RCC_MCODIV_64 ((uint32_t)0x60000000) -#define RCC_MCODIV_128 ((uint32_t)0x70000000) +#define RCC_MCODIV_1 (0x00000000U) +#define RCC_MCODIV_2 (0x10000000U) +#define RCC_MCODIV_4 (0x20000000U) +#define RCC_MCODIV_8 (0x30000000U) +#define RCC_MCODIV_16 (0x40000000U) +#define RCC_MCODIV_32 (0x50000000U) +#define RCC_MCODIV_64 (0x60000000U) +#define RCC_MCODIV_128 (0x70000000U) #else -#define RCC_MCODIV_1 ((uint32_t)0x00000000) +#define RCC_MCODIV_1 (0x00000000U) #endif /* RCC_CFGR_MCOPRE */ @@ -1784,7 +1784,7 @@ typedef struct * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */ +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ @@ -1823,7 +1823,7 @@ typedef struct do { \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ - } while(0) + } while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ @@ -1897,7 +1897,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ @@ -1910,21 +1910,21 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() @@ -1946,7 +1946,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ @@ -1958,7 +1958,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() @@ -1976,14 +1976,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) @@ -1996,21 +1996,21 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) @@ -2034,28 +2034,28 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) @@ -2071,49 +2071,49 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) @@ -2132,14 +2132,14 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) @@ -2152,84 +2152,84 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM18_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CEC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) @@ -2255,7 +2255,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #endif /* STM32F303xE || STM32F398xx || */ @@ -2273,7 +2273,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F302xE || STM32F303xE || */ @@ -2288,7 +2288,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F301x8*/ @@ -2300,7 +2300,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ @@ -2323,7 +2323,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ @@ -2337,7 +2337,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #endif /* STM32F303xE || STM32F398xx || */ @@ -2350,7 +2350,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ @@ -2362,7 +2362,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN)) #endif /* STM32F334x8 */ @@ -2374,42 +2374,42 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM19_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SDADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SDADC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SDADC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) @@ -2429,7 +2429,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ @@ -2444,7 +2444,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ @@ -2456,7 +2456,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN)) #endif /* STM32F303xE || STM32F398xx */ @@ -3560,7 +3560,7 @@ typedef struct * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock */ #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__)) + MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__)) /** @brief Macro to get the SDADCx clock prescaler. * @retval The clock source can be one of the following values: @@ -3582,7 +3582,7 @@ typedef struct * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock */ -#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE))) +#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE))) /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc.h index 52a87c5565da99e98de0d9bab109e2443c9e45da..3763de9eedf640af1e2903273ad84f247b15d8d6 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -64,10 +64,10 @@ */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ }HAL_RTCStateTypeDef; @@ -81,10 +81,10 @@ typedef struct This parameter can be a value of @ref RTC_Hour_Formats */ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FU */ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ @@ -106,21 +106,21 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 59U */ uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 59U */ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. - This parameter corresponds to a time unit range between [0-1] Second + This parameter corresponds to a time unit range between [0U-1] Second with [1 Sec / SecondFraction +1] granularity */ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content corresponding to Synchronous pre-scaler factor value (PREDIV_S) - This parameter corresponds to a time unit range between [0-1] Second + This parameter corresponds to a time unit range between [0U-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ @@ -144,10 +144,10 @@ typedef struct This parameter can be a value of @ref RTC_Month_Date_Definitions */ uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + This parameter must be a number between Min_Data = 1 and Max_Data = 31U */ uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 99U */ }RTC_DateTypeDef; @@ -168,7 +168,7 @@ typedef struct This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm Date is selected, this parameter must be set to a value in the 1U-31 range. If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ uint32_t Alarm; /*!< Specifies the alarm . @@ -201,7 +201,7 @@ typedef struct /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) +#define RTC_HOURFORMAT_24 (0x00000000U) #define RTC_HOURFORMAT_12 RTC_CR_FMT /** * @} @@ -210,7 +210,7 @@ typedef struct /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) +#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U) #define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} @@ -219,7 +219,7 @@ typedef struct /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) +#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U) #define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /** * @} @@ -228,8 +228,8 @@ typedef struct /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) /** * @} */ @@ -237,7 +237,7 @@ typedef struct /** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) +#define RTC_DAYLIGHTSAVING_NONE (0x00000000U) #define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H #define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H /** @@ -247,7 +247,7 @@ typedef struct /** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) +#define RTC_STOREOPERATION_RESET (0x00000000U) #define RTC_STOREOPERATION_SET RTC_CR_BCK /** * @} @@ -256,8 +256,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN (0x000000000U) +#define RTC_FORMAT_BCD (0x000000001U) /** * @} */ @@ -266,18 +266,18 @@ typedef struct * @{ */ /* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) /** * @} */ @@ -285,13 +285,13 @@ typedef struct /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /** * @} */ @@ -299,7 +299,7 @@ typedef struct /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) +#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U) #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** * @} @@ -308,7 +308,7 @@ typedef struct /** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_NONE (0x00000000U) #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 @@ -334,7 +334,7 @@ typedef struct /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. +#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm @@ -378,10 +378,10 @@ typedef struct #define RTC_IT_ALRB RTC_CR_ALRBIE #define RTC_IT_ALRA RTC_CR_ALRAIE #define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) /*only for RTC_ISR flag check*/ -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP1 (0x00020000U) /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP2 (0x00040000U) /*only for RTC_ISR flag check*/ #if defined(RTC_TAMPER3_SUPPORT) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP3 (0x00080000U) /*only for RTC_ISR flag check*/ #endif /* RTC_TAMPER3_SUPPORT */ /** * @} @@ -434,9 +434,9 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) /** * @brief Enable the write protection for RTC registers. @@ -445,8 +445,8 @@ typedef struct */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -507,7 +507,7 @@ typedef struct * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -703,10 +703,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_TR_RESERVED_MASK (0x007F7F7FU) +#define RTC_DR_RESERVED_MASK (0x00FFFF3FU) +#define RTC_INIT_MASK (0xFFFFFFFFU) +#define RTC_RSF_MASK (0xFFFFFF5FU) #define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \ RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \ @@ -739,12 +739,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) #define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ ((PM) == RTC_HOURFORMAT12_PM)) @@ -758,11 +758,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -772,7 +772,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ @@ -785,11 +785,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET) #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU) #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc_ex.h index ae17e024572663a8309eaea8127aa438f64e36ca..2116b681585a95fbedc4b7e74cc030424532e8b4 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention @@ -98,7 +98,7 @@ typedef struct /** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition * @{ */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) +#define RTC_OUTPUT_DISABLE (0x00000000U) #define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 #define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 #define RTC_OUTPUT_WAKEUP RTC_CR_OSEL @@ -109,49 +109,49 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition * @{ */ -#if RTC_BKP_NUMBER > 0 -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#endif /* RTC_BKP_NUMBER > 0 */ - -#if RTC_BKP_NUMBER > 5 -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#endif /* RTC_BKP_NUMBER > 5 */ - -#if RTC_BKP_NUMBER > 16 -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#endif /* RTC_BKP_NUMBER > 16 */ - -#if RTC_BKP_NUMBER > 20 -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) -#endif /* RTC_BKP_NUMBER > 20 */ +#if RTC_BKP_NUMBER > 0U +#define RTC_BKP_DR0 (0x00000000U) +#define RTC_BKP_DR1 (0x00000001U) +#define RTC_BKP_DR2 (0x00000002U) +#define RTC_BKP_DR3 (0x00000003U) +#define RTC_BKP_DR4 (0x00000004U) +#endif /* RTC_BKP_NUMBER > 0U */ + +#if RTC_BKP_NUMBER > 5U +#define RTC_BKP_DR5 (0x00000005U) +#define RTC_BKP_DR6 (0x00000006U) +#define RTC_BKP_DR7 (0x00000007U) +#define RTC_BKP_DR8 (0x00000008U) +#define RTC_BKP_DR9 (0x00000009U) +#define RTC_BKP_DR10 (0x0000000AU) +#define RTC_BKP_DR11 (0x0000000BU) +#define RTC_BKP_DR12 (0x0000000CU) +#define RTC_BKP_DR13 (0x0000000DU) +#define RTC_BKP_DR14 (0x0000000EU) +#define RTC_BKP_DR15 (0x0000000FU) +#endif /* RTC_BKP_NUMBER > 5U */ + +#if RTC_BKP_NUMBER > 16U +#define RTC_BKP_DR16 (0x00000010U) +#define RTC_BKP_DR17 (0x00000011U) +#define RTC_BKP_DR18 (0x00000012U) +#define RTC_BKP_DR19 (0x00000013U) +#endif /* RTC_BKP_NUMBER > 16U */ + +#if RTC_BKP_NUMBER > 20U +#define RTC_BKP_DR20 (0x00000014U) +#define RTC_BKP_DR21 (0x00000015U) +#define RTC_BKP_DR22 (0x00000016U) +#define RTC_BKP_DR23 (0x00000017U) +#define RTC_BKP_DR24 (0x00000018U) +#define RTC_BKP_DR25 (0x00000019U) +#define RTC_BKP_DR26 (0x0000001AU) +#define RTC_BKP_DR27 (0x0000001BU) +#define RTC_BKP_DR28 (0x0000001CU) +#define RTC_BKP_DR29 (0x0000001DU) +#define RTC_BKP_DR30 (0x0000001EU) +#define RTC_BKP_DR31 (0x0000001FU) +#endif /* RTC_BKP_NUMBER > 20U */ /** * @} */ @@ -159,7 +159,7 @@ typedef struct /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMPEDGE_RISING (0x00000000U) #define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} @@ -168,7 +168,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) +#define RTC_TIMESTAMPPIN_DEFAULT (0x00000000U) /** * @} */ @@ -189,7 +189,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) +#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U) #define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE @@ -200,7 +200,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition * @{ */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ @@ -215,10 +215,10 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768U */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ + with a frequency = RTCCLK / 16384U */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled @@ -238,7 +238,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ @@ -254,7 +254,7 @@ typedef struct * @{ */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ /** * @} */ @@ -262,7 +262,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */ /** * @} @@ -271,7 +271,7 @@ typedef struct /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U) #define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 #define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 #define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) @@ -284,7 +284,7 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation +#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ #define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ @@ -297,11 +297,11 @@ typedef struct /** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ #define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ + with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */ /** * @} */ @@ -309,7 +309,7 @@ typedef struct /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition * @{ */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) +#define RTC_CALIBOUTPUT_512HZ (0x00000000U) #define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** * @} @@ -318,7 +318,7 @@ typedef struct /** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition * @{ */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) +#define RTC_SHIFTADD1S_RESET (0x00000000U) #define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} @@ -379,7 +379,7 @@ typedef struct * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. @@ -542,7 +542,7 @@ typedef struct * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. @@ -659,7 +659,7 @@ typedef struct * @note (*) RTC_IT_TAMP3 not present on all the devices * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. @@ -946,7 +946,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6U) == 0x00) && ((TAMPER) != (uint32_t)RESET)) +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) @@ -983,7 +983,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU) #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ @@ -993,10 +993,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ ((SEL) == RTC_SHIFTADD1S_SET)) -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sdadc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sdadc.h index f813be5902ec252d2e5f72c0de6ca05598f92764..ae8b4b8e73de89dc72b64eae0bb8fe82765516c0 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sdadc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sdadc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sdadc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains all the functions prototypes for the SDADC * firmware library. ****************************************************************************** @@ -68,13 +68,13 @@ */ typedef enum { - HAL_SDADC_STATE_RESET = 0x00, /*!< SDADC not initialized */ - HAL_SDADC_STATE_READY = 0x01, /*!< SDADC initialized and ready for use */ - HAL_SDADC_STATE_CALIB = 0x02, /*!< SDADC calibration in progress */ - HAL_SDADC_STATE_REG = 0x03, /*!< SDADC regular conversion in progress */ - HAL_SDADC_STATE_INJ = 0x04, /*!< SDADC injected conversion in progress */ - HAL_SDADC_STATE_REG_INJ = 0x05, /*!< SDADC regular and injected conversions in progress */ - HAL_SDADC_STATE_ERROR = 0xFF, /*!< SDADC state error */ + HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */ + HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */ + HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */ + HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */ + HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */ + HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */ + HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */ }HAL_SDADC_StateTypeDef; /** @@ -123,10 +123,10 @@ typedef struct This parameter can be any value of @ref SDADC_InputMode */ uint32_t Gain; /*!< Specifies the gain setting. This parameter can be any value of @ref SDADC_Gain */ - uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2). + uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U). This parameter can be any value of @ref SDADC_CommonMode */ uint32_t Offset; /*!< Specifies the 12-bit offset value. - This parameter can be any value lower or equal to 0x00000FFF */ + This parameter can be any value lower or equal to 0x00000FFFU */ }SDADC_ConfParamTypeDef; /** @@ -142,7 +142,7 @@ typedef struct /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode * @{ */ -#define SDADC_LOWPOWER_NONE ((uint32_t)0x00000000) +#define SDADC_LOWPOWER_NONE (0x00000000U) #define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI #define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI /** @@ -152,7 +152,7 @@ typedef struct /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode * @{ */ -#define SDADC_FAST_CONV_DISABLE ((uint32_t)0x00000000) +#define SDADC_FAST_CONV_DISABLE (0x00000000U) #define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST /** * @} @@ -161,7 +161,7 @@ typedef struct /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode * @{ */ -#define SDADC_SLOW_CLOCK_DISABLE ((uint32_t)0x00000000) +#define SDADC_SLOW_CLOCK_DISABLE (0x00000000U) #define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK /** * @} @@ -170,7 +170,7 @@ typedef struct /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage * @{ */ -#define SDADC_VREF_EXT ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */ +#define SDADC_VREF_EXT (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */ #define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */ #define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */ #define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */ @@ -182,9 +182,9 @@ typedef struct * @{ */ -#define SDADC_CONF_INDEX_0 ((uint32_t)0x00000000) /*!< Configuration 0 Register selected */ -#define SDADC_CONF_INDEX_1 ((uint32_t)0x00000001) /*!< Configuration 1 Register selected */ -#define SDADC_CONF_INDEX_2 ((uint32_t)0x00000002) /*!< Configuration 2 Register selected */ +#define SDADC_CONF_INDEX_0 (0x00000000U) /*!< Configuration 0 Register selected */ +#define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */ +#define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */ /** * @} */ @@ -192,7 +192,7 @@ typedef struct /** @defgroup SDADC_InputMode SDADC Input Mode * @{ */ -#define SDADC_INPUT_MODE_DIFF ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */ +#define SDADC_INPUT_MODE_DIFF (0x00000000U) /*!< Conversions are executed in differential mode */ #define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */ #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */ /** @@ -202,13 +202,13 @@ typedef struct /** @defgroup SDADC_Gain SDADC Gain * @{ */ -#define SDADC_GAIN_1 ((uint32_t)0x00000000) /*!< Gain equal to 1 */ -#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2 */ -#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4 */ -#define SDADC_GAIN_8 ((uint32_t)0x00300000) /*!< Gain equal to 8 */ -#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16 */ -#define SDADC_GAIN_32 ((uint32_t)0x00500000) /*!< Gain equal to 32 */ -#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1/2 */ +#define SDADC_GAIN_1 (0x00000000U) /*!< Gain equal to 1U */ +#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */ +#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */ +#define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */ +#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */ +#define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */ +#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */ /** * @} */ @@ -216,7 +216,7 @@ typedef struct /** @defgroup SDADC_CommonMode SDADC Common Mode * @{ */ -#define SDADC_COMMON_MODE_VSSA ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */ +#define SDADC_COMMON_MODE_VSSA (0x00000000U) /*!< Select SDADC VSSA as common mode */ #define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */ #define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */ /** @@ -236,16 +236,16 @@ typedef struct e.g. for channel 5 definition: - the channel mask is 0x00000020 (bit 5 is set) - the channel number 5 is 0x00050000 - --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ -#define SDADC_CHANNEL_0 ((uint32_t)0x00000001) -#define SDADC_CHANNEL_1 ((uint32_t)0x00010002) -#define SDADC_CHANNEL_2 ((uint32_t)0x00020004) -#define SDADC_CHANNEL_3 ((uint32_t)0x00030008) -#define SDADC_CHANNEL_4 ((uint32_t)0x00040010) -#define SDADC_CHANNEL_5 ((uint32_t)0x00050020) -#define SDADC_CHANNEL_6 ((uint32_t)0x00060040) -#define SDADC_CHANNEL_7 ((uint32_t)0x00070080) -#define SDADC_CHANNEL_8 ((uint32_t)0x00080100) + --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */ +#define SDADC_CHANNEL_0 (0x00000001U) +#define SDADC_CHANNEL_1 (0x00010002U) +#define SDADC_CHANNEL_2 (0x00020004U) +#define SDADC_CHANNEL_3 (0x00030008U) +#define SDADC_CHANNEL_4 (0x00040010U) +#define SDADC_CHANNEL_5 (0x00050020U) +#define SDADC_CHANNEL_6 (0x00060040U) +#define SDADC_CHANNEL_7 (0x00070080U) +#define SDADC_CHANNEL_8 (0x00080100U) /** * @} */ @@ -253,7 +253,7 @@ typedef struct /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence * @{ */ -#define SDADC_CALIBRATION_SEQ_1 ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */ +#define SDADC_CALIBRATION_SEQ_1 (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */ #define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */ #define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */ /** @@ -263,8 +263,8 @@ typedef struct /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode * @{ */ -#define SDADC_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */ -#define SDADC_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */ +#define SDADC_CONTINUOUS_CONV_OFF (0x00000000U) /*!< Conversion are not continuous */ +#define SDADC_CONTINUOUS_CONV_ON (0x00000001U) /*!< Conversion are continuous */ /** * @} */ @@ -272,9 +272,9 @@ typedef struct /** @defgroup SDADC_Trigger SDADC Trigger * @{ */ -#define SDADC_SOFTWARE_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */ -#define SDADC_SYNCHRONOUS_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */ -#define SDADC_EXTERNAL_TRIGGER ((uint32_t)0x00000002) /*!< External trigger */ +#define SDADC_SOFTWARE_TRIGGER (0x00000000U) /*!< Software trigger */ +#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */ +#define SDADC_EXTERNAL_TRIGGER (0x00000002U) /*!< External trigger */ /** * @} */ @@ -282,26 +282,26 @@ typedef struct /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger * @{ */ -#define SDADC_EXT_TRIG_TIM13_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM14_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM16_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM17_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM12_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM12_CC2 ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM15_CC2 ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM2_CC3 ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM2_CC4 ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM3_CC1 ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM3_CC2 ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM3_CC3 ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM4_CC1 ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM4_CC2 ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM4_CC3 ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_TIM19_CC2 ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */ -#define SDADC_EXT_TRIG_TIM19_CC3 ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */ -#define SDADC_EXT_TRIG_TIM19_CC4 ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */ -#define SDADC_EXT_TRIG_EXTI11 ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ -#define SDADC_EXT_TRIG_EXTI15 ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ +#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U) /*!< Trigger source for SDADC1 */ +#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U) /*!< Trigger source for SDADC2 */ +#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U) /*!< Trigger source for SDADC3 */ +#define SDADC_EXT_TRIG_EXTI11 (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ +#define SDADC_EXT_TRIG_EXTI15 (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ /** * @} */ @@ -319,7 +319,7 @@ typedef struct /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay * @{ */ -#define SDADC_INJECTED_DELAY_NONE ((uint32_t)0x00000000) /*!< No delay on injected conversion */ +#define SDADC_INJECTED_DELAY_NONE (0x00000000U) /*!< No delay on injected conversion */ #define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */ /** * @} @@ -328,8 +328,8 @@ typedef struct /** @defgroup SDADC_MultimodeType SDADC Multimode Type * @{ */ -#define SDADC_MULTIMODE_SDADC1_SDADC2 ((uint32_t)0x00000000) /*!< Get conversion values for SDADC1 and SDADC2 */ -#define SDADC_MULTIMODE_SDADC1_SDADC3 ((uint32_t)0x00000001) /*!< Get conversion values for SDADC1 and SDADC3 */ +#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */ +#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */ /** * @} */ @@ -337,10 +337,10 @@ typedef struct /** @defgroup SDADC_ErrorCode SDADC Error Code * @{ */ -#define SDADC_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define SDADC_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */ -#define SDADC_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */ -#define SDADC_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */ +#define SDADC_ERROR_NONE (0x00000000U) /*!< No error */ +#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001U) /*!< Overrun occurs during regular conversion */ +#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002U) /*!< Overrun occurs during injected conversion */ +#define SDADC_ERROR_DMA (0x00000003U) /*!< DMA error occurs */ /** * @} */ @@ -501,7 +501,7 @@ typedef struct ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \ ((MODE) == SDADC_COMMON_MODE_VDDA)) -#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF) +#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU) /* Just one channel of the 9 channels can be selected for regular conversion */ #define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \ @@ -515,7 +515,7 @@ typedef struct ((CHANNEL) == SDADC_CHANNEL_8)) /* Any or all of the 9 channels can be selected for injected conversion */ -#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF)) +#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU)) #define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard.h index 8b9b7f09b30da46486e670cc1b29cf753a2d0e80..c60c0bbac0279e91f6844160ce62dbd7722b0a04 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention @@ -55,7 +55,6 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types * @{ */ @@ -72,12 +71,12 @@ typedef struct uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ - uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits. - Only 1.5 stop bits are authorized in SmartCard mode. */ + uint32_t StopBits; /*!< Specifies the number of stop bits. + This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ uint16_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref SMARTCARD_Parity - @note The parity is enabled by default (PCE is forced to 1). + @note The parity is enabled by default (PCE is forced to 1U). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit. */ @@ -98,9 +97,9 @@ typedef struct Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ - uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */ + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */ - uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */ + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled in case of parity error. @@ -114,10 +113,10 @@ typedef struct Block Wait Time (BWT). It is coded over 24 bits. */ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. - This parameter can be any value from 0x0 to 0xFF */ + This parameter can be any value from 0x0 to 0xFFU */ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in - receive and transmit mode). When set to 0, retransmission is + receive and transmit mode). When set to 0U, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling an error) */ @@ -230,13 +229,13 @@ typedef struct uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ @@ -261,12 +260,12 @@ typedef struct */ typedef enum { - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ }SMARTCARD_ClockSourceTypeDef; /** @@ -281,13 +280,13 @@ typedef enum /** @defgroup SMARTCARD_Error SMARTCARD Error * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ /** * @} */ @@ -295,12 +294,12 @@ typedef enum /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ -#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */ /** * @} */ -/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits * @{ */ #define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */ @@ -312,8 +311,8 @@ typedef enum /** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ -#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */ /** * @} */ @@ -321,9 +320,9 @@ typedef enum /** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode * @{ */ -#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) -#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) -#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) +#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */ /** * @} */ @@ -331,8 +330,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) -#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) +#define SMARTCARD_POLARITY_LOW (0x00000000U) /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */ /** * @} */ @@ -340,8 +339,8 @@ typedef enum /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) -#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) +#define SMARTCARD_PHASE_1EDGE (0x00000000U) /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */ /** * @} */ @@ -349,8 +348,8 @@ typedef enum /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) +#define SMARTCARD_LASTBIT_DISABLE (0x00000000U) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ /** * @} */ @@ -358,8 +357,8 @@ typedef enum /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method * @{ */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */ /** * @} */ @@ -368,8 +367,8 @@ typedef enum /** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ -#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_DISABLE (0x00000000U) /*!< SMARTCARD NACK transmission enabled */ /** * @} */ @@ -377,23 +376,23 @@ typedef enum /** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) +#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U) /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */ /** * @} */ -/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type +/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) +#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */ /** * @} */ @@ -401,8 +400,8 @@ typedef enum /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ /** * @} */ @@ -410,8 +409,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ /** * @} */ @@ -419,8 +418,8 @@ typedef enum /** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ /** * @} */ @@ -428,8 +427,8 @@ typedef enum /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ /** * @} */ @@ -437,8 +436,8 @@ typedef enum /** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ /** * @} */ @@ -446,8 +445,8 @@ typedef enum /** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ /** * @} */ @@ -455,8 +454,8 @@ typedef enum /** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -466,24 +465,24 @@ typedef enum * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000) -#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000) -#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000) -#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000) -#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800) -#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080) -#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040) -#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020) -#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010) -#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008) -#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004) -#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002) -#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001) +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ /** * @} */ -/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition +/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -494,34 +493,34 @@ typedef enum * @{ */ -#define SMARTCARD_IT_PE ((uint16_t)0x0028) -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) -#define SMARTCARD_IT_TC ((uint16_t)0x0626) -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) -#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) +#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */ -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) -#define SMARTCARD_IT_NE ((uint16_t)0x0200) -#define SMARTCARD_IT_FE ((uint16_t)0x0100) +#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */ -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */ /** * @} */ -/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags +/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags * @{ */ -#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ /** * @} */ @@ -529,7 +528,7 @@ typedef enum /** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register * @{ */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ +#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ /** * @} */ @@ -537,7 +536,7 @@ typedef enum /** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register * @{ */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */ +#define SMARTCARD_GTPR_GT_LSB_POS ( 8U) /*!< SMARTCARD guard time value LSB position in GTPR register */ /** * @} */ @@ -545,7 +544,7 @@ typedef enum /** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register * @{ */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */ +#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U) /*!< SMARTCARD block length LSB position in RTOR register */ /** * @} */ @@ -553,16 +552,16 @@ typedef enum /** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask * @{ */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /*!< SMARTCARD interruptions flags mask */ /** * @} */ -/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters * @{ */ -#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */ /** * @} */ @@ -583,7 +582,7 @@ typedef enum #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0) + } while(0U) /** @brief Flush the Smartcard Data registers. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -593,20 +592,20 @@ typedef enum do{ \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__: specifies the SMARTCARD Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: - * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag - * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag - * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag - * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag - * @arg SMARTCARD_CLEAR_IDLEF: Idle line detected clear flag - * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag - * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag - * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None */ #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -644,22 +643,21 @@ typedef enum /** @brief Check whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag - * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag - * @arg SMARTCARD_FLAG_BUSY: Busy flag - * @arg SMARTCARD_FLAG_EOBF: End of block flag - * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag - * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag - * @arg SMARTCARD_FLAG_TC: Transmission complete flag - * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag - * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag - * @arg SMARTCARD_FLAG_ORE: Overrun error flag - * @arg SMARTCARD_FLAG_NE: Noise error flag - * @arg SMARTCARD_FLAG_FE: Framing error flag - * @arg SMARTCARD_FLAG_PE: Parity error flag + * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_BUSY Busy flag + * @arg @ref SMARTCARD_FLAG_EOBF End of block flag + * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag + * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag + * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag + * @arg @ref SMARTCARD_FLAG_NE Noise error flag + * @arg @ref SMARTCARD_FLAG_FE Framing error flag + * @arg @ref SMARTCARD_FLAG_PE Parity error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) @@ -667,109 +665,101 @@ typedef enum /** @brief Enable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOB: End of block interrupt - * @arg SMARTCARD_IT_RTO: Receive timeout interrupt - * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_PE: Parity error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOB: End of block interrupt - * @arg SMARTCARD_IT_RTO: Receive timeout interrupt - * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_PE: Parity error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT__: specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOB: End of block interrupt - * @arg SMARTCARD_IT_RTO: Receive timeout interrupt - * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_ORE: Overrun error interrupt - * @arg SMARTCARD_IT_NE: Noise error interrupt - * @arg SMARTCARD_IT_FE: Framing error interrupt - * @arg SMARTCARD_IT_PE: Parity error interrupt + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt + * @arg @ref SMARTCARD_IT_NE Noise error interrupt + * @arg @ref SMARTCARD_IT_FE Framing error interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT__: specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOB: End of block interrupt - * @arg SMARTCARD_IT_RTO: Receive timeout interrupt - * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt - * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt - * @arg SMARTCARD_IT_ORE: Overrun error interrupt - * @arg SMARTCARD_IT_NE: Noise error interrupt - * @arg SMARTCARD_IT_FE: Framing error interrupt - * @arg SMARTCARD_IT_PE: Parity error interrupt + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt + * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag - * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag - * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag - * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag - * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag - * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag - * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag - * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag * @retval None */ #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __REQ__: specifies the request flag to set * This parameter can be one of the following values: - * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive data flush Request - * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request + * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request * * @retval None */ @@ -789,14 +779,12 @@ typedef enum /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -810,34 +798,34 @@ typedef enum * @{ */ -/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the - * maximum clock on F3 (i.e. 72 MHz) divided by the oversampling used - * on the SMARTCARD (i.e. 16). +/** @brief Check the Baud rate range. + * @note The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz) + * divided by the oversampling used on the SMARTCARD (i.e. 16). * @param __BAUDRATE__: Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U) /** @brief Check the block length range. * @note The maximum SMARTCARD block length is 0xFF. * @param __LENGTH__: block length. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) /** @brief Check the receiver timeout value. * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. * @param __TIMEOUTVALUE__: receiver timeout value. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** @brief Check the SMARTCARD autoretry counter value. * @note The maximum number of retransmissions is 0x7. * @param __COUNT__: number of retransmissions. * @retval Test result (TRUE or FALSE) */ -#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) /** * @brief Ensure that SMARTCARD frame length is valid. @@ -867,7 +855,7 @@ typedef enum * @param __MODE__: SMARTCARD communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00)) +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U)) /** * @brief Ensure that SMARTCARD frame polarity is valid. @@ -1001,15 +989,16 @@ typedef enum #include "stm32f3xx_hal_smartcard_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions +/** @addtogroup SMARTCARD_Exported_Functions * @{ */ -/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions +/* Initialization and de-initialization functions ****************************/ + +/** @addtogroup SMARTCARD_Exported_Functions_Group1 * @{ */ -/* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); @@ -1019,29 +1008,42 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); * @} */ -/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions +/* IO operation functions *****************************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group2 * @{ */ -/* IO operation functions *****************************************************/ + HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard); + void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ -/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions +/* Peripheral State and Error functions ***************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group3 * @{ */ -/* Peripheral State and Error functions ***************************************/ + HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard_ex.h index 33b5af8cea3ad3f04d59c695ed7aa3ee55184d03..f52c68b0b4a24bd425cec182d38d3841bae8b041 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention @@ -56,20 +56,20 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup SMARTCARD_Extended_Exported_Macros SMARTCARDEx Exported Macros +/* Exported macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros * @{ */ -/** @brief Reports the SMARTCARD clock source. - * @param __HANDLE__: specifies the SMARTCARD Handle - * @param __CLOCKSOURCE__ : output variable +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__: output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -104,9 +104,9 @@ { \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #else -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -175,7 +175,7 @@ { \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #endif /** @@ -188,8 +188,9 @@ */ /* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions +/* IO operation methods *******************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 * @{ */ @@ -199,8 +200,6 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); -/* Peripheral State and Error functions ***************************************/ - /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smbus.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smbus.h index f958db4a76cbed49ee54c7347578e87cb37e626b..06b337a944b9f44fb93f0dcd7a3acc19cb9de0fe 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smbus.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_smbus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smbus.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention @@ -99,7 +99,7 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) + (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; @@ -111,16 +111,16 @@ typedef struct * @brief HAL State definition * @{ */ -#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */ -#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */ -#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -129,15 +129,15 @@ typedef struct * @brief SMBUS Error Code definition * @{ */ -#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */ -#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */ -#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */ -#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */ -#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */ +#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ /** * @} */ @@ -185,8 +185,8 @@ typedef struct /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter * @{ */ -#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) -#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ @@ -194,8 +194,8 @@ typedef struct /** @defgroup SMBUS_addressing_mode SMBUS addressing mode * @{ */ -#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) -#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) +#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) +#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) /** * @} */ @@ -204,43 +204,43 @@ typedef struct * @{ */ -#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) -#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +#define SMBUS_DUALADDRESS_DISABLE (0x00000000U) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ -/** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks +/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks * @{ */ -#define SMBUS_OA2_NOMASK ((uint8_t)0x00) -#define SMBUS_OA2_MASK01 ((uint8_t)0x01) -#define SMBUS_OA2_MASK02 ((uint8_t)0x02) -#define SMBUS_OA2_MASK03 ((uint8_t)0x03) -#define SMBUS_OA2_MASK04 ((uint8_t)0x04) -#define SMBUS_OA2_MASK05 ((uint8_t)0x05) -#define SMBUS_OA2_MASK06 ((uint8_t)0x06) -#define SMBUS_OA2_MASK07 ((uint8_t)0x07) +#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ -/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode +/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode * @{ */ -#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) -#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN +#define SMBUS_GENERALCALL_DISABLE (0x00000000U) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ -/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode * @{ */ -#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) -#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +#define SMBUS_NOSTRETCH_DISABLE (0x00000000U) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ @@ -248,8 +248,8 @@ typedef struct /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode * @{ */ -#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) -#define SMBUS_PEC_ENABLE I2C_CR1_PECEN +#define SMBUS_PEC_DISABLE (0x00000000U) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN /** * @} */ @@ -257,18 +257,18 @@ typedef struct /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode * @{ */ -#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) -#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) -#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) +#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN /** * @} */ -/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition * @{ */ -#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) +#define SMBUS_SOFTEND_MODE (0x00000000U) #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE @@ -280,7 +280,7 @@ typedef struct * @{ */ -#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) +#define SMBUS_NO_STARTSTOP (0x00000000U) #define SMBUS_GENERATE_STOP I2C_CR2_STOP #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define SMBUS_GENERATE_START_WRITE I2C_CR2_START @@ -288,16 +288,28 @@ typedef struct * @} */ -/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition +/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition * @{ */ -#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ +#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) /** * @} */ @@ -308,17 +320,17 @@ typedef struct * - XXXXXXXX : Interrupt control mask * @{ */ -#define SMBUS_IT_ERRI I2C_CR1_ERRIE -#define SMBUS_IT_TCI I2C_CR1_TCIE -#define SMBUS_IT_STOPI I2C_CR1_STOPIE -#define SMBUS_IT_NACKI I2C_CR1_NACKIE -#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE -#define SMBUS_IT_RXI I2C_CR1_RXIE -#define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) -#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) -#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) /** * @} */ @@ -330,22 +342,22 @@ typedef struct * @{ */ -#define SMBUS_FLAG_TXE I2C_ISR_TXE -#define SMBUS_FLAG_TXIS I2C_ISR_TXIS -#define SMBUS_FLAG_RXNE I2C_ISR_RXNE -#define SMBUS_FLAG_ADDR I2C_ISR_ADDR -#define SMBUS_FLAG_AF I2C_ISR_NACKF -#define SMBUS_FLAG_STOPF I2C_ISR_STOPF -#define SMBUS_FLAG_TC I2C_ISR_TC -#define SMBUS_FLAG_TCR I2C_ISR_TCR -#define SMBUS_FLAG_BERR I2C_ISR_BERR -#define SMBUS_FLAG_ARLO I2C_ISR_ARLO -#define SMBUS_FLAG_OVR I2C_ISR_OVR -#define SMBUS_FLAG_PECERR I2C_ISR_PECERR -#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define SMBUS_FLAG_ALERT I2C_ISR_ALERT -#define SMBUS_FLAG_BUSY I2C_ISR_BUSY -#define SMBUS_FLAG_DIR I2C_ISR_DIR +#define SMBUS_FLAG_TXE I2C_ISR_TXE +#define SMBUS_FLAG_TXIS I2C_ISR_TXIS +#define SMBUS_FLAG_RXNE I2C_ISR_RXNE +#define SMBUS_FLAG_ADDR I2C_ISR_ADDR +#define SMBUS_FLAG_AF I2C_ISR_NACKF +#define SMBUS_FLAG_STOPF I2C_ISR_STOPF +#define SMBUS_FLAG_TC I2C_ISR_TC +#define SMBUS_FLAG_TCR I2C_ISR_TCR +#define SMBUS_FLAG_BERR I2C_ISR_BERR +#define SMBUS_FLAG_ARLO I2C_ISR_ARLO +#define SMBUS_FLAG_OVR I2C_ISR_OVR +#define SMBUS_FLAG_PECERR I2C_ISR_PECERR +#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define SMBUS_FLAG_ALERT I2C_ISR_ALERT +#define SMBUS_FLAG_BUSY I2C_ISR_BUSY +#define SMBUS_FLAG_DIR I2C_ISR_DIR /** * @} */ @@ -399,7 +411,7 @@ typedef struct /** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__ specifies the SMBUS Handle. - * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. + * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. * This parameter can be one of the following values: * @arg @ref SMBUS_IT_ERRI Errors interrupt enable * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable @@ -436,7 +448,7 @@ typedef struct * * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) +#define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. @@ -521,6 +533,7 @@ typedef struct #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ ((MODE) == SMBUS_AUTOEND_MODE) || \ ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ @@ -538,7 +551,13 @@ typedef struct ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ + IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) @@ -546,8 +565,8 @@ typedef struct #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) -#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) +#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) @@ -555,18 +574,9 @@ typedef struct #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) -#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Functions SMBUS Private Functions - * @{ - */ -/* Private functions are defined in stm32f3xx_hal_smbus.c file */ /** * @} */ @@ -577,8 +587,8 @@ typedef struct */ /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); @@ -591,13 +601,22 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +/** + * @} + */ +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -609,7 +628,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ +/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -626,8 +651,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ + * @{ + */ /* Peripheral State and Errors functions **************************************************/ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); @@ -641,7 +666,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); * @} */ - +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32f3xx_hal_smbus.c file */ +/** + * @} + */ /** * @} @@ -654,6 +686,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} */ + #ifdef __cplusplus } #endif diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi.h index 3866d91d7daa33ba63e2aa5b8e7975c5ad761a56..bf9a96c42815554c7664599dd2561ec7c802fd65 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi.h @@ -1,9 +1,9 @@ - /** +/** ****************************************************************************** * @file stm32f3xx_hal_spi.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -40,7 +40,7 @@ #define __STM32F3xx_HAL_SPI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -92,14 +92,14 @@ typedef struct uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not . + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. This parameter can be a value of @ref SPI_TI_mode */ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. CRC Length is only used with Data8 and Data16, not other data size @@ -114,18 +114,19 @@ typedef struct } SPI_InitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL SPI State structure definition */ typedef enum { - HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ - HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */ -}HAL_SPI_StateTypeDef; + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; /** * @brief SPI handle Structure definition @@ -150,9 +151,9 @@ typedef struct __SPI_HandleTypeDef uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */ + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */ + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ @@ -164,14 +165,13 @@ typedef struct __SPI_HandleTypeDef __IO uint32_t ErrorCode; /*!< SPI Error code */ -}SPI_HandleTypeDef; +} SPI_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup SPI_Exported_Constants SPI Exported Constants * @{ */ @@ -179,23 +179,22 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Error_Code SPI Error Code * @{ */ -#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */ -#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */ -#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */ -#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */ -#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */ -#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ -#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ /** * @} */ - /** @defgroup SPI_Mode SPI Mode * @{ */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_SLAVE (0x00000000U) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /** * @} @@ -204,7 +203,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Direction SPI Direction Mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES (0x00000000U) #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE /** @@ -214,19 +213,19 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) -#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) -#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) -#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) -#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) -#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) -#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) -#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) -#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) -#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) -#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) -#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) -#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) +#define SPI_DATASIZE_4BIT (0x00000300U) +#define SPI_DATASIZE_5BIT (0x00000400U) +#define SPI_DATASIZE_6BIT (0x00000500U) +#define SPI_DATASIZE_7BIT (0x00000600U) +#define SPI_DATASIZE_8BIT (0x00000700U) +#define SPI_DATASIZE_9BIT (0x00000800U) +#define SPI_DATASIZE_10BIT (0x00000900U) +#define SPI_DATASIZE_11BIT (0x00000A00U) +#define SPI_DATASIZE_12BIT (0x00000B00U) +#define SPI_DATASIZE_13BIT (0x00000C00U) +#define SPI_DATASIZE_14BIT (0x00000D00U) +#define SPI_DATASIZE_15BIT (0x00000E00U) +#define SPI_DATASIZE_16BIT (0x00000F00U) /** * @} */ @@ -234,7 +233,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_LOW (0x00000000U) #define SPI_POLARITY_HIGH SPI_CR1_CPOL /** * @} @@ -243,18 +242,18 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_1EDGE (0x00000000U) #define SPI_PHASE_2EDGE SPI_CR1_CPHA /** * @} */ -/** @defgroup SPI_Slave_Select_management SPI Slave Select management +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) /** * @} */ @@ -263,7 +262,7 @@ typedef struct __SPI_HandleTypeDef * @{ */ #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP -#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000) +#define SPI_NSS_PULSE_DISABLE (0x00000000U) /** * @} */ @@ -271,31 +270,31 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /** * @} */ -/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission * @{ */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_MSB (0x00000000U) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST /** * @} */ -/** @defgroup SPI_TI_mode SPI TI mode +/** @defgroup SPI_TI_mode SPI TI Mode * @{ */ -#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_DISABLE (0x00000000U) #define SPI_TIMODE_ENABLE SPI_CR2_FRF /** * @} @@ -304,7 +303,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN /** * @} @@ -317,9 +316,9 @@ typedef struct __SPI_HandleTypeDef * SPI_CRC_LENGTH_8BIT : CRC 8bit * SPI_CRC_LENGTH_16BIT : CRC 16bit */ -#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000) -#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001) -#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002) +#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) +#define SPI_CRC_LENGTH_8BIT (0x00000001U) +#define SPI_CRC_LENGTH_16BIT (0x00000002U) /** * @} */ @@ -334,16 +333,13 @@ typedef struct __SPI_HandleTypeDef * level is greater or equal to 1/4(8 bits). */ #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000) +#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) /** * @} */ -/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition - * @brief SPI Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition * @{ */ #define SPI_IT_TXE SPI_CR2_TXEIE @@ -353,23 +349,18 @@ typedef struct __SPI_HandleTypeDef * @} */ - -/** @defgroup SPI_Flag_definition SPI Flag definition - * @brief Flag definition - * Elements values convention: 0xXXXXYYYY - * - XXXX : Flag register Index - * - YYYY : Flag mask +/** @defgroup SPI_Flags_definition SPI Flags Definition * @{ */ -#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ -#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ -#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ -#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ -#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ -#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ -#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ -#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ /** * @} */ @@ -377,10 +368,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ */ -#define SPI_FTLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800) -#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000) -#define SPI_FTLVL_FULL ((uint32_t)0x1800) +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) /** * @} @@ -389,10 +380,10 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_FRLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200) -#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400) -#define SPI_FRLVL_FULL ((uint32_t)0x0600) +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) /** * @} */ @@ -401,29 +392,41 @@ typedef struct __SPI_HandleTypeDef * @} */ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ /** @brief Reset SPI handle state. - * @param __HANDLE__: SPI handle. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enable or disable the specified SPI interrupts. +/** @brief Enable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. * @param __HANDLE__: specifies the SPI Handle. @@ -441,7 +444,7 @@ typedef struct __SPI_HandleTypeDef * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag * @arg SPI_FLAG_CRCERR: CRC error flag @@ -465,64 +468,61 @@ typedef struct __SPI_HandleTypeDef /** @brief Clear the SPI MODF pending flag. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_modf; \ - tmpreg_modf = (__HANDLE__)->Instance->SR; \ - (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ - UNUSED(tmpreg_modf); \ - } while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) /** @brief Clear the SPI OVR pending flag. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_ovr; \ - tmpreg_ovr = (__HANDLE__)->Instance->DR; \ - tmpreg_ovr = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_ovr); \ - } while(0) +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) /** @brief Clear the SPI FRE pending flag. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * * @retval None */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_fre; \ - tmpreg_fre = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_fre); \ - } while(0) +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + }while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** * @} */ -/* Private macros --------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros * @{ */ @@ -531,34 +531,34 @@ typedef struct __SPI_HandleTypeDef * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ - (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ - ((MODE) == SPI_DIRECTION_1LINE)) +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE)) #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_1LINE)) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ ((DATASIZE) == SPI_DATASIZE_15BIT) || \ @@ -580,19 +580,19 @@ typedef struct __SPI_HandleTypeDef #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ ((CPHA) == SPI_PHASE_2EDGE)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ ((NSS) == SPI_NSS_HARD_INPUT) || \ ((NSS) == SPI_NSS_HARD_OUTPUT)) #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ ((NSSP) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) @@ -609,8 +609,9 @@ typedef struct __SPI_HandleTypeDef ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0)) +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) /** * @} @@ -624,34 +625,40 @@ typedef struct __SPI_HandleTypeDef * @{ */ -/* Initialization and de-initialization functions ****************************/ /** @addtogroup SPI_Exported_Functions_Group1 * @{ */ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /** * @} */ -/* IO operation functions *****************************************************/ /** @addtogroup SPI_Exported_Functions_Group2 * @{ */ +/* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); @@ -661,14 +668,15 @@ void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); /** * @} */ -/* Peripheral State and Error functions ***************************************/ /** @addtogroup SPI_Exported_Functions_Group3 * @{ */ +/* Peripheral State and Error functions ***************************************/ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi_ex.h index bea8657169b431809ca8f20032b4a18046e82fcb..fac69db0dda8470c785851fa842eeb4ac4951ae6 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_spi_ex.h @@ -1,9 +1,9 @@ - /** +/** ****************************************************************************** * @file stm32f3xx_hal_spi_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SPI HAL Extended module. ****************************************************************************** * @attention @@ -40,7 +40,7 @@ #define __STM32F3xx_HAL_SPI_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -56,7 +56,7 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPIEx_Exported_Functions * @{ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sram.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sram.h index 2b93c55003dec57c53cc694a81e8b737f85fb4a3..d7c10105ffadae9514cd6c31a10d76ae0cbdcb4f 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sram.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sram.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -65,10 +65,10 @@ */ typedef enum { - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ }HAL_SRAM_StateTypeDef; diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim.h index 421b6ff385743172f3950a99a0b0206165869a0a..c1e4f99f58f2df3072bd46e7b993cf01eb901ca4 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -64,7 +64,7 @@ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ @@ -79,11 +79,14 @@ typedef struct uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: + This means in PWM mode that (N+1U) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** @@ -95,7 +98,7 @@ typedef struct This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -127,7 +130,7 @@ typedef struct This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -151,7 +154,7 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ } TIM_OnePulse_InitTypeDef; @@ -170,7 +173,7 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ } TIM_IC_InitTypeDef; /** @@ -191,7 +194,7 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -203,7 +206,7 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ } TIM_Encoder_InitTypeDef; @@ -219,7 +222,7 @@ typedef struct uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ }TIM_ClockConfigTypeDef; /** @@ -236,7 +239,7 @@ typedef struct uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter can be a value of @ref TIM_ClearInput_Prescaler */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ }TIM_ClearInputConfigTypeDef; /** @@ -252,7 +255,7 @@ typedef struct { uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ }TIM_SlaveConfigTypeDef; @@ -261,10 +264,10 @@ typedef struct { */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; @@ -273,10 +276,10 @@ typedef enum */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; @@ -307,7 +310,7 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** @@ -318,7 +321,7 @@ typedef struct * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */ /** * @} */ @@ -326,10 +329,10 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ +#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */ +#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */ +#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */ /** * @} */ @@ -337,7 +340,7 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_UP (0x0000U) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 @@ -349,9 +352,19 @@ typedef struct /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV1 (0x0000U) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ + /** * @} */ @@ -359,7 +372,7 @@ typedef struct /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_DISABLE (0x0000U) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) /** * @} @@ -368,7 +381,7 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_HIGH (0x0000U) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) /** * @} @@ -377,7 +390,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCNPOLARITY_HIGH (0x0000U) #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) /** * @} @@ -387,7 +400,7 @@ typedef struct * @{ */ #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_RESET (0x0000U) /** * @} */ @@ -396,7 +409,7 @@ typedef struct * @{ */ #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_RESET (0x0000U) /** * @} */ @@ -414,11 +427,11 @@ typedef struct /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be +#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be +#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */ /** * @} */ @@ -426,7 +439,7 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ @@ -438,7 +451,7 @@ typedef struct * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_REPETITIVE (0x0000U) /** * @} */ @@ -472,7 +485,7 @@ typedef struct * @{ */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_SOFTWARE (0x0000U) /** * @} @@ -516,7 +529,7 @@ typedef struct */ #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR0 (0x0000U) #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) @@ -575,7 +588,7 @@ typedef struct * @{ */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_DISABLE (0x0000U) /** * @} */ @@ -584,7 +597,7 @@ typedef struct * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_DISABLE (0x0000U) /** * @} */ @@ -592,7 +605,7 @@ typedef struct /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_OFF (0x0000U) #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) @@ -604,7 +617,7 @@ typedef struct * @{ */ #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_DISABLE (0x0000U) /** * @} */ @@ -612,7 +625,7 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) +#define TIM_BREAKPOLARITY_LOW (0x0000U) #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) /** * @} @@ -621,7 +634,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U) /** * @} */ @@ -629,7 +642,7 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET (0x0000U) #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -644,8 +657,8 @@ typedef struct /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode * @{ */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U) +#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U) /** * @} */ @@ -653,15 +666,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 (0x0000U) +#define TIM_TS_ITR1 (0x0010U) +#define TIM_TS_ITR2 (0x0020U) +#define TIM_TS_ITR3 (0x0030U) +#define TIM_TS_TI1F_ED (0x0040U) +#define TIM_TS_TI1FP1 (0x0050U) +#define TIM_TS_TI2FP2 (0x0060U) +#define TIM_TS_ETRF (0x0070U) +#define TIM_TS_NONE (0xFFFFU) /** * @} */ @@ -692,7 +705,7 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_CH1 (0x0000U) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) /** * @} @@ -701,24 +714,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) /** * @} */ @@ -726,13 +739,13 @@ typedef struct /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -740,10 +753,10 @@ typedef struct /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE (0x0001U) +#define TIM_CCx_DISABLE (0x0000U) +#define TIM_CCxN_ENABLE (0x0004U) +#define TIM_CCxN_DISABLE (0x0000U) /** * @} */ @@ -785,14 +798,14 @@ typedef struct */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ - } while(0) + } while(0U) /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ /** @@ -803,14 +816,23 @@ typedef struct */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ - } while(0) + } while(0U) + +/* The Main Output Enable of a timer instance is disabled unconditionally */ +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__: TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled uncondiotionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** * @brief Enables the specified TIM interrupt. @@ -979,7 +1001,7 @@ typedef struct do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Autoreload Register value on runtime @@ -1005,7 +1027,7 @@ typedef struct (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Clock Division value on runtime @@ -1037,7 +1059,7 @@ typedef struct do{ \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Input Capture prescaler on runtime @@ -1052,9 +1074,9 @@ typedef struct */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register @@ -1100,7 +1122,7 @@ typedef struct do{ \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) + }while(0U) /** * @} @@ -1137,6 +1159,8 @@ typedef struct ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ ((DIV) == TIM_CLOCKDIVISION_DIV4)) +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ ((STATE) == TIM_OCFAST_ENABLE)) @@ -1174,7 +1198,7 @@ typedef struct ((MODE) == TIM_ENCODERMODE_TI2) || \ ((MODE) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1199,7 +1223,7 @@ typedef struct ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) @@ -1209,7 +1233,7 @@ typedef struct ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ ((STATE) == TIM_OSSR_DISABLE)) @@ -1269,7 +1293,7 @@ typedef struct ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU) #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) @@ -1293,7 +1317,7 @@ typedef struct ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) /** @brief Set TIM IC prescaler * @param __HANDLE__: TIM handle @@ -1303,9 +1327,9 @@ typedef struct */ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) /** @brief Reset TIM IC prescaler * @param __HANDLE__: TIM handle @@ -1326,9 +1350,9 @@ typedef struct */ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) /** @brief Reset TIM IC polarity * @param __HANDLE__: TIM handle diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim_ex.h index 21ecf512ca3c9115f79b9f866ec3382b78c2513b..ec8eaf91553c43eb0cee5f523b2cf31c2b69226d 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention @@ -73,9 +73,9 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */ } TIM_HallSensor_InitTypeDef; #if defined(STM32F373xC) || defined(STM32F378xx) @@ -104,7 +104,7 @@ typedef struct uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity @@ -133,19 +133,19 @@ typedef struct uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the brek input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ uint32_t Break2State; /*!< TIM Break2 State This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity This parameter can be a value of @ref TIMEx_Break2_Polarity */ uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; @@ -180,11 +180,11 @@ typedef struct { /** @defgroup TIMEx_Channel TIMEx Channel * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_ALL ((uint32_t)0x0018) +#define TIM_CHANNEL_1 (0x0000U) +#define TIM_CHANNEL_2 (0x0004U) +#define TIM_CHANNEL_3 (0x0008U) +#define TIM_CHANNEL_4 (0x000CU) +#define TIM_CHANNEL_ALL (0x0018U) /** * @} */ @@ -192,7 +192,7 @@ typedef struct { /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING (0x0000U) #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) @@ -207,8 +207,8 @@ typedef struct { /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR (0x0001U) +#define TIM_CLEARINPUTSOURCE_NONE (0x0000U) /** * @} */ @@ -216,7 +216,7 @@ typedef struct { /** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_DISABLE (0x0000U) #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) @@ -229,10 +229,10 @@ typedef struct { * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ @@ -243,26 +243,26 @@ typedef struct { /** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_OR (0x00000013) +#define TIM_DMABASE_CR1 (0x00000000U) +#define TIM_DMABASE_CR2 (0x00000001U) +#define TIM_DMABASE_SMCR (0x00000002U) +#define TIM_DMABASE_DIER (0x00000003U) +#define TIM_DMABASE_SR (0x00000004U) +#define TIM_DMABASE_EGR (0x00000005U) +#define TIM_DMABASE_CCMR1 (0x00000006U) +#define TIM_DMABASE_CCMR2 (0x00000007U) +#define TIM_DMABASE_CCER (0x00000008U) +#define TIM_DMABASE_CNT (0x00000009U) +#define TIM_DMABASE_PSC (0x0000000AU) +#define TIM_DMABASE_ARR (0x0000000BU) +#define TIM_DMABASE_RCR (0x0000000CU) +#define TIM_DMABASE_CCR1 (0x0000000DU) +#define TIM_DMABASE_CCR2 (0x0000000EU) +#define TIM_DMABASE_CCR3 (0x0000000FU) +#define TIM_DMABASE_CCR4 (0x00000010U) +#define TIM_DMABASE_BDTR (0x00000011U) +#define TIM_DMABASE_DCR (0x00000012U) +#define TIM_DMABASE_OR (0x00000013U) /** * @} */ @@ -275,13 +275,13 @@ typedef struct { /** @defgroup TIMEx_Channel TIMEx Channel * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) +#define TIM_CHANNEL_1 (0x0000U) +#define TIM_CHANNEL_2 (0x0004U) +#define TIM_CHANNEL_3 (0x0008U) +#define TIM_CHANNEL_4 (0x000CU) +#define TIM_CHANNEL_5 (0x0010U) +#define TIM_CHANNEL_6 (0x0014U) +#define TIM_CHANNEL_ALL (0x003CU) /** * @} */ @@ -289,7 +289,7 @@ typedef struct { /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING (0x0000U) #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) @@ -312,9 +312,9 @@ typedef struct { /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR (0x0001U) +#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U) +#define TIM_CLEARINPUTSOURCE_NONE (0x0000U) /** * @} */ @@ -322,7 +322,7 @@ typedef struct { /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable * @{ */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) +#define TIM_BREAK2_DISABLE (0x00000000U) #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /** * @} @@ -331,7 +331,7 @@ typedef struct { /** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity * @{ */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) +#define TIM_BREAK2POLARITY_LOW (0x00000000U) #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) /** * @} @@ -340,7 +340,7 @@ typedef struct { /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) * @{ */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) +#define TIM_TRGO2_RESET (0x00000000U) #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) @@ -363,7 +363,7 @@ typedef struct { /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_SLAVEMODE_DISABLE (0x0000U) #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) @@ -377,10 +377,10 @@ typedef struct { * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ @@ -392,29 +392,29 @@ typedef struct { /** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_CCMR3 (0x00000015) -#define TIM_DMABASE_CCR5 (0x00000016) -#define TIM_DMABASE_CCR6 (0x00000017) -#define TIM_DMABASE_OR (0x00000018) +#define TIM_DMABASE_CR1 (0x00000000U) +#define TIM_DMABASE_CR2 (0x00000001U) +#define TIM_DMABASE_SMCR (0x00000002U) +#define TIM_DMABASE_DIER (0x00000003U) +#define TIM_DMABASE_SR (0x00000004U) +#define TIM_DMABASE_EGR (0x00000005U) +#define TIM_DMABASE_CCMR1 (0x00000006U) +#define TIM_DMABASE_CCMR2 (0x00000007U) +#define TIM_DMABASE_CCER (0x00000008U) +#define TIM_DMABASE_CNT (0x00000009U) +#define TIM_DMABASE_PSC (0x0000000AU) +#define TIM_DMABASE_ARR (0x0000000BU) +#define TIM_DMABASE_RCR (0x0000000CU) +#define TIM_DMABASE_CCR1 (0x0000000DU) +#define TIM_DMABASE_CCR2 (0x0000000EU) +#define TIM_DMABASE_CCR3 (0x0000000FU) +#define TIM_DMABASE_CCR4 (0x00000010U) +#define TIM_DMABASE_BDTR (0x00000011U) +#define TIM_DMABASE_DCR (0x00000012U) +#define TIM_DMABASE_CCMR3 (0x00000015U) +#define TIM_DMABASE_CCR5 (0x00000016U) +#define TIM_DMABASE_CCR6 (0x00000017U) +#define TIM_DMABASE_OR (0x00000018U) /** * @} */ @@ -425,43 +425,73 @@ typedef struct { #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F303x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup TIMEx_Remap TIMEx Remapping * @{ */ -#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */ -#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */ -#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */ +#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ +#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ +#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ /** * @} */ #endif /* STM32F302xE || */ /* STM32F302xC || */ - /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F303x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + +#if defined(STM32F334x8) +/** @defgroup TIMEx_Remap TIMEx Remapping 1 + * @{ + */ +#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ +#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ +#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ +/** + * @} + */ + +/** @defgroup TIMEx_Remap2 TIMEx Remapping 2 + * @{ + */ +#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ +/** + * @} + */ +#endif /* STM32F334x8 */ + #if defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup TIMEx_Remap TIMEx Remapping 1 * @{ */ -#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */ -#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */ -#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */ +#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ +#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ +#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ /** * @} */ @@ -469,15 +499,15 @@ typedef struct { /** @defgroup TIMEx_Remap2 TIMEx Remapping 2 * @{ */ -#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */ -#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */ -#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */ -#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */ -#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */ +#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ +#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ /** * @} */ @@ -487,22 +517,22 @@ typedef struct { /** @defgroup TIMEx_Remap TIMEx Remapping 1 * @{ */ -#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */ -#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */ -#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */ -#define TIM_TIM20_ADC3_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM20_ADC3_AWD1 (0x00000001) /*!< TIM20_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM20_ADC3_AWD2 (0x00000002) /*!< TIM20_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM20_ADC3_AWD3 (0x00000003) /*!< TIM20_ETR is connected to ADC3 AWD3 */ +#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ +#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */ +#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ +#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */ /** * @} */ @@ -510,19 +540,19 @@ typedef struct { /** @defgroup TIMEx_Remap2 TIMEx Remapping 2 * @{ */ -#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */ -#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */ -#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */ -#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */ -#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */ -#define TIM_TIM20_ADC4_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ -#define TIM_TIM20_ADC4_AWD1 (0x00000004) /*!< TIM20_ETR is connected to ADC4 AWD1 */ -#define TIM_TIM20_ADC4_AWD2 (0x00000008) /*!< TIM20_ETR is connected to ADC4 AWD2 */ -#define TIM_TIM20_ADC4_AWD3 (0x0000000C) /*!< TIM20_ETR is connected to ADC4 AWD3 */ +#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ +#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */ +#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */ /** * @} */ @@ -533,14 +563,14 @@ typedef struct { /** @defgroup TIMEx_Remap TIMEx remapping * @{ */ -#define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */ -#define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */ -#define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */ -#define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */ -#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */ -#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */ -#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */ -#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */ +#define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */ +#define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */ +#define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */ +#define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */ +#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ +#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ /** * @} */ @@ -550,10 +580,10 @@ typedef struct { defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ @@ -608,7 +638,7 @@ typedef struct { ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ ((BASE) == TIM_DMABASE_CR2) || \ @@ -675,7 +705,7 @@ typedef struct { ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) -#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF) +#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU) #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \ ((STATE) == TIM_BREAK2_DISABLE)) @@ -708,7 +738,7 @@ typedef struct { ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ ((BASE) == TIM_DMABASE_CR2) || \ @@ -740,7 +770,7 @@ typedef struct { #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F303x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\ @@ -754,9 +784,27 @@ typedef struct { #endif /* STM32F302xE || */ /* STM32F302xC || */ - /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F303x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ +#if defined(STM32F334x8) +#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ + ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\ + ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\ + ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\ + ((REMAP1) == TIM_TIM16_GPIO) ||\ + ((REMAP1) == TIM_TIM16_RTC) ||\ + ((REMAP1) == TIM_TIM16_HSE) ||\ + ((REMAP1) == TIM_TIM16_MCO)) + +#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\ + ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\ + ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\ + ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\ + ((REMAP2) == TIM_TIM16_NONE)) + +#endif /* STM32F334x8 */ + #if defined(STM32F303xC) || defined(STM32F358xx) #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\ @@ -838,14 +886,14 @@ typedef struct { defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000)) +#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ -#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /** * @} @@ -873,7 +921,7 @@ typedef struct { * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) /** * @brief Gets the TIM Capture Compare Register value on runtime @@ -887,7 +935,42 @@ typedef struct { * @retval None */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) + +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) + #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ @@ -937,6 +1020,49 @@ typedef struct { ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ @@ -1036,14 +1162,14 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); #if defined(STM32F303xE) || defined(STM32F398xx) || \ - defined(STM32F303xC) || defined(STM32F358xx) + defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8) HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2); #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F303x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ defined(STM32F373xC) || defined(STM32F378xx) HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tsc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tsc.h index 9f7dfa88996bdcdf454a6d4ccdcef69ead73132a..332b7fecd06e508e06a77f63e2f813054bd3617d 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tsc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_tsc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tsc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of TSC HAL module. ****************************************************************************** * @attention @@ -64,10 +64,10 @@ */ typedef enum { - HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ - HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ - HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ - HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ + HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */ } HAL_TSC_StateTypeDef; /** @@ -75,8 +75,8 @@ typedef enum */ typedef enum { - TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ - TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ + TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */ } TSC_GroupStatusTypeDef; /** @@ -91,7 +91,7 @@ typedef struct uint32_t SpreadSpectrum; /*!< Spread spectrum activation This parameter can be a value of @ref TSC_CTPulseLL_Config */ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation - This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 127U */ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler @@ -144,22 +144,22 @@ typedef struct /** @defgroup TSC_CTPulseHL_Config CTPulse High Length * @{ */ -#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) -#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) -#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) -#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) -#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) -#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) -#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) -#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) -#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) -#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) -#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) -#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) -#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) -#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) -#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) -#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) +#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U)) +#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U)) +#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U)) +#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U)) +#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U)) +#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U)) +#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U)) +#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U)) +#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U)) +#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U)) +#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U)) +#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U)) +#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U)) +#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U)) +#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U)) +#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U)) /** * @} */ @@ -167,22 +167,22 @@ typedef struct /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length * @{ */ -#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) -#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) -#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) -#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) -#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) -#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) -#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) -#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) -#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) -#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) -#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) -#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) -#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) -#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) -#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) -#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) +#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U)) +#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U)) +#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U)) +#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U)) +#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U)) +#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U)) +#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U)) +#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U)) +#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U)) +#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U)) +#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U)) +#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U)) +#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U)) +#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U)) +#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U)) +#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U)) /** * @} */ @@ -190,7 +190,7 @@ typedef struct /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler * @{ */ -#define TSC_SS_PRESC_DIV1 ((uint32_t)0) +#define TSC_SS_PRESC_DIV1 (0U) #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) /** * @} @@ -199,14 +199,14 @@ typedef struct /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler * @{ */ -#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) -#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) -#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) -#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) -#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) -#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) -#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) -#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) +#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U)) +#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U)) +#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U)) +#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U)) +#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U)) +#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U)) +#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U)) +#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U)) /** * @} */ @@ -214,13 +214,13 @@ typedef struct /** @defgroup TSC_MaxCount_Value Max Count Value * @{ */ -#define TSC_MCV_255 ((uint32_t)(0 << 5)) -#define TSC_MCV_511 ((uint32_t)(1 << 5)) -#define TSC_MCV_1023 ((uint32_t)(2 << 5)) -#define TSC_MCV_2047 ((uint32_t)(3 << 5)) -#define TSC_MCV_4095 ((uint32_t)(4 << 5)) -#define TSC_MCV_8191 ((uint32_t)(5 << 5)) -#define TSC_MCV_16383 ((uint32_t)(6 << 5)) +#define TSC_MCV_255 ((uint32_t)(0U << 5U)) +#define TSC_MCV_511 ((uint32_t)(1U << 5U)) +#define TSC_MCV_1023 ((uint32_t)(2U << 5U)) +#define TSC_MCV_2047 ((uint32_t)(3U << 5U)) +#define TSC_MCV_4095 ((uint32_t)(4U << 5U)) +#define TSC_MCV_8191 ((uint32_t)(5U << 5U)) +#define TSC_MCV_16383 ((uint32_t)(6U << 5U)) /** * @} */ @@ -228,7 +228,7 @@ typedef struct /** @defgroup TSC_IO_Default_Mode IO Default Mode * @{ */ -#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) +#define TSC_IODEF_OUT_PP_LOW (0U) #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) /** * @} @@ -237,7 +237,7 @@ typedef struct /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity * @{ */ -#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) +#define TSC_SYNC_POLARITY_FALLING (0U) #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) /** * @} @@ -246,7 +246,7 @@ typedef struct /** @defgroup TSC_Acquisition_Mode Acquisition Mode * @{ */ -#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) +#define TSC_ACQ_MODE_NORMAL (0U) #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) /** * @} @@ -255,10 +255,10 @@ typedef struct /** @defgroup TSC_IO_Mode IO Mode * @{ */ -#define TSC_IOMODE_UNUSED ((uint32_t)0) -#define TSC_IOMODE_CHANNEL ((uint32_t)1) -#define TSC_IOMODE_SHIELD ((uint32_t)2) -#define TSC_IOMODE_SAMPLING ((uint32_t)3) +#define TSC_IOMODE_UNUSED (0U) +#define TSC_IOMODE_CHANNEL (1U) +#define TSC_IOMODE_SHIELD (2U) +#define TSC_IOMODE_SAMPLING (3U) /** * @} */ @@ -284,76 +284,76 @@ typedef struct /** @defgroup TSC_Group_definition Group definition * @{ */ -#define TSC_NB_OF_GROUPS (8) - -#define TSC_GROUP1 ((uint32_t)0x00000001) -#define TSC_GROUP2 ((uint32_t)0x00000002) -#define TSC_GROUP3 ((uint32_t)0x00000004) -#define TSC_GROUP4 ((uint32_t)0x00000008) -#define TSC_GROUP5 ((uint32_t)0x00000010) -#define TSC_GROUP6 ((uint32_t)0x00000020) -#define TSC_GROUP7 ((uint32_t)0x00000040) -#define TSC_GROUP8 ((uint32_t)0x00000080) -#define TSC_ALL_GROUPS ((uint32_t)0x000000FF) - -#define TSC_GROUP1_IDX ((uint32_t)0) -#define TSC_GROUP2_IDX ((uint32_t)1) -#define TSC_GROUP3_IDX ((uint32_t)2) -#define TSC_GROUP4_IDX ((uint32_t)3) -#define TSC_GROUP5_IDX ((uint32_t)4) -#define TSC_GROUP6_IDX ((uint32_t)5) -#define TSC_GROUP7_IDX ((uint32_t)6) -#define TSC_GROUP8_IDX ((uint32_t)7) - -#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) -#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) -#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) -#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) -#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F) - -#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) -#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) -#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) -#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) -#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0) - -#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) -#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) -#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) -#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) -#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) - -#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) -#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) -#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) -#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) -#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) - -#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) -#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) -#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) -#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) -#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) - -#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) -#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) -#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) -#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) -#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) - -#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) -#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) -#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) -#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) -#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) - -#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) -#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) -#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) -#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) -#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) - -#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) +#define TSC_NB_OF_GROUPS (8U) + +#define TSC_GROUP1 (0x00000001U) +#define TSC_GROUP2 (0x00000002U) +#define TSC_GROUP3 (0x00000004U) +#define TSC_GROUP4 (0x00000008U) +#define TSC_GROUP5 (0x00000010U) +#define TSC_GROUP6 (0x00000020U) +#define TSC_GROUP7 (0x00000040U) +#define TSC_GROUP8 (0x00000080U) +#define TSC_ALL_GROUPS (0x000000FFU) + +#define TSC_GROUP1_IDX (0U) +#define TSC_GROUP2_IDX (1U) +#define TSC_GROUP3_IDX (2U) +#define TSC_GROUP4_IDX (3U) +#define TSC_GROUP5_IDX (4U) +#define TSC_GROUP6_IDX (5U) +#define TSC_GROUP7_IDX (6U) +#define TSC_GROUP8_IDX (7U) + +#define TSC_GROUP1_IO1 (0x00000001U) +#define TSC_GROUP1_IO2 (0x00000002U) +#define TSC_GROUP1_IO3 (0x00000004U) +#define TSC_GROUP1_IO4 (0x00000008U) +#define TSC_GROUP1_ALL_IOS (0x0000000FU) + +#define TSC_GROUP2_IO1 (0x00000010U) +#define TSC_GROUP2_IO2 (0x00000020U) +#define TSC_GROUP2_IO3 (0x00000040U) +#define TSC_GROUP2_IO4 (0x00000080U) +#define TSC_GROUP2_ALL_IOS (0x000000F0U) + +#define TSC_GROUP3_IO1 (0x00000100U) +#define TSC_GROUP3_IO2 (0x00000200U) +#define TSC_GROUP3_IO3 (0x00000400U) +#define TSC_GROUP3_IO4 (0x00000800U) +#define TSC_GROUP3_ALL_IOS (0x00000F00U) + +#define TSC_GROUP4_IO1 (0x00001000U) +#define TSC_GROUP4_IO2 (0x00002000U) +#define TSC_GROUP4_IO3 (0x00004000U) +#define TSC_GROUP4_IO4 (0x00008000U) +#define TSC_GROUP4_ALL_IOS (0x0000F000U) + +#define TSC_GROUP5_IO1 (0x00010000U) +#define TSC_GROUP5_IO2 (0x00020000U) +#define TSC_GROUP5_IO3 (0x00040000U) +#define TSC_GROUP5_IO4 (0x00080000U) +#define TSC_GROUP5_ALL_IOS (0x000F0000U) + +#define TSC_GROUP6_IO1 (0x00100000U) +#define TSC_GROUP6_IO2 (0x00200000U) +#define TSC_GROUP6_IO3 (0x00400000U) +#define TSC_GROUP6_IO4 (0x00800000U) +#define TSC_GROUP6_ALL_IOS (0x00F00000U) + +#define TSC_GROUP7_IO1 (0x01000000U) +#define TSC_GROUP7_IO2 (0x02000000U) +#define TSC_GROUP7_IO3 (0x04000000U) +#define TSC_GROUP7_IO4 (0x08000000U) +#define TSC_GROUP7_ALL_IOS (0x0F000000U) + +#define TSC_GROUP8_IO1 (0x10000000U) +#define TSC_GROUP8_IO2 (0x20000000U) +#define TSC_GROUP8_IO3 (0x40000000U) +#define TSC_GROUP8_IO4 (0x80000000U) +#define TSC_GROUP8_ALL_IOS (0xF0000000U) + +#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU) /** * @} */ @@ -555,7 +555,7 @@ typedef struct * @retval SET or RESET */ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ -((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) +((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) /** * @} @@ -603,7 +603,7 @@ typedef struct #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) -#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) +#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U))) #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) @@ -637,7 +637,7 @@ typedef struct #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) -#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS))) +#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS))) /** * @} diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart.h index ba5430ad5c909d175d5d6a3da6f7fe926bd96d3f..8d6f20a90fdda22b7137d00556d404706c25b420 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -68,16 +68,16 @@ typedef struct The baud rate register is computed using the following formula: - If oversampling is 16 or in LIN mode, Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] + - If oversampling is 8U, + Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ + Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length */ + This parameter can be a value of @ref UARTEx_Word_Length. */ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ + This parameter can be a value of @ref UART_Stop_Bits. */ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref UART_Parity @@ -87,14 +87,14 @@ typedef struct word length is set to 8 data bits). */ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode */ + This parameter can be a value of @ref UART_Mode. */ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U). + This parameter can be a value of @ref UART_Over_Sampling. */ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock @@ -108,36 +108,36 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */ + This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv */ + This parameter can be a value of @ref UART_Tx_Inv. */ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv */ + This parameter can be a value of @ref UART_Rx_Inv. */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv */ + This parameter can be a value of @ref UART_Data_Inv. */ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap */ + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable */ + This parameter can be a value of @ref UART_Overrun_Disable. */ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */ + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. This parameter can be a value of @ref UART_AutoBaudRate_Enable */ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */ + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First */ + This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; /** @@ -151,9 +151,9 @@ typedef struct be filled up. */ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UART_WakeUp_Address_Length */ + This parameter can be a value of @ref UART_WakeUp_Address_Length. */ - uint8_t Address; /*!< UART/USART node address (7-bit long max) */ + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ } UART_WakeUpTypeDef; /** @@ -221,12 +221,12 @@ typedef enum */ typedef enum { - UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }UART_ClockSourceTypeDef; /** @@ -244,13 +244,13 @@ typedef struct uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ uint16_t Mask; /*!< UART Rx RDR register mask */ @@ -258,7 +258,7 @@ typedef struct DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management and also related to Tx operations. @@ -283,12 +283,13 @@ typedef struct /** @defgroup UART_Error UART Error * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */ /** * @} */ @@ -297,7 +298,7 @@ typedef struct * @{ */ #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */ #define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */ #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */ /** @@ -307,7 +308,7 @@ typedef struct /** @defgroup UART_Parity UART Parity * @{ */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define UART_PARITY_NONE (0x00000000U) /*!< No parity */ #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** @@ -317,7 +318,7 @@ typedef struct /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */ +#define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */ #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */ #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */ #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */ @@ -338,7 +339,7 @@ typedef struct /** @defgroup UART_State UART State * @{ */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */ +#define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */ #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */ /** * @} @@ -347,7 +348,7 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16U */ #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ /** * @} @@ -356,7 +357,7 @@ typedef struct /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */ #define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */ /** * @} @@ -365,7 +366,7 @@ typedef struct /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */ #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */ @@ -376,7 +377,7 @@ typedef struct /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */ +#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */ #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */ /** * @} @@ -385,7 +386,7 @@ typedef struct /** @defgroup UART_LIN UART Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */ +#define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */ #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */ /** * @} @@ -394,7 +395,7 @@ typedef struct /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */ #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */ /** * @} @@ -403,7 +404,7 @@ typedef struct /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */ +#define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */ #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */ /** * @} @@ -412,7 +413,7 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */ +#define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */ #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */ /** * @} @@ -421,7 +422,7 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */ #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */ /** * @} @@ -430,7 +431,7 @@ typedef struct /** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */ #define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */ /** * @} @@ -439,7 +440,7 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */ #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */ /** * @} @@ -450,28 +451,28 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define UART_FLAG_REACK ((uint32_t)0x00400000) -#define UART_FLAG_TEACK ((uint32_t)0x00200000) -#define UART_FLAG_WUF ((uint32_t)0x00100000) -#define UART_FLAG_RWU ((uint32_t)0x00080000) -#define UART_FLAG_SBKF ((uint32_t)0x00040000) -#define UART_FLAG_CMF ((uint32_t)0x00020000) -#define UART_FLAG_BUSY ((uint32_t)0x00010000) -#define UART_FLAG_ABRF ((uint32_t)0x00008000) -#define UART_FLAG_ABRE ((uint32_t)0x00004000) -#define UART_FLAG_EOBF ((uint32_t)0x00001000) -#define UART_FLAG_RTOF ((uint32_t)0x00000800) -#define UART_FLAG_CTS ((uint32_t)0x00000400) -#define UART_FLAG_CTSIF ((uint32_t)0x00000200) -#define UART_FLAG_LBDF ((uint32_t)0x00000100) -#define UART_FLAG_TXE ((uint32_t)0x00000080) -#define UART_FLAG_TC ((uint32_t)0x00000040) -#define UART_FLAG_RXNE ((uint32_t)0x00000020) -#define UART_FLAG_IDLE ((uint32_t)0x00000010) -#define UART_FLAG_ORE ((uint32_t)0x00000008) -#define UART_FLAG_NE ((uint32_t)0x00000004) -#define UART_FLAG_FE ((uint32_t)0x00000002) -#define UART_FLAG_PE ((uint32_t)0x00000001) +#define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */ +#define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */ +#define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */ +#define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */ +#define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */ +#define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */ +#define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */ +#define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */ +#define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */ +#define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */ +#define UART_FLAG_NE (0x00000004U) /*!< UART noise error */ +#define UART_FLAG_FE (0x00000002U) /*!< UART frame error */ +#define UART_FLAG_PE (0x00000001U) /*!< UART parity error */ /** * @} */ @@ -486,31 +487,19 @@ typedef struct * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ -#define UART_IT_PE ((uint16_t)0x0028) -#define UART_IT_TXE ((uint16_t)0x0727) -#define UART_IT_TC ((uint16_t)0x0626) -#define UART_IT_RXNE ((uint16_t)0x0525) -#define UART_IT_IDLE ((uint16_t)0x0424) -#define UART_IT_LBD ((uint16_t)0x0846) -#define UART_IT_CTS ((uint16_t)0x096A) -#define UART_IT_CM ((uint16_t)0x112E) -#define UART_IT_WUF ((uint16_t)0x1476) - -/** Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - */ -#define UART_IT_ERR ((uint16_t)0x0060) - -/** Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - */ -#define UART_IT_ORE ((uint16_t)0x0300) -#define UART_IT_NE ((uint16_t)0x0200) -#define UART_IT_FE ((uint16_t)0x0100) +#define UART_IT_PE (0x0028U) /*!< UART parity error interruption */ +#define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */ +#define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */ +#define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */ +#define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */ +#define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */ +#define UART_IT_CM (0x112EU) /*!< UART character match interruption */ +#define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */ +#define UART_IT_ERR (0x0060U) /*!< UART error interruption */ +#define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */ +#define UART_IT_NE (0x0200U) /*!< UART noise error interruption */ +#define UART_IT_FE (0x0100U) /*!< UART frame error interruption */ /** * @} */ @@ -518,17 +507,17 @@ typedef struct /** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags * @{ */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ +#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ /** * @} @@ -537,11 +526,11 @@ typedef struct /** @defgroup UART_Request_Parameters UART Request Parameters * @{ */ -#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ /** * @} */ @@ -549,15 +538,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */ /** * @} */ @@ -565,7 +554,7 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */ #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ /** * @} @@ -574,7 +563,7 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */ #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ /** * @} @@ -583,7 +572,7 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */ #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ /** * @} @@ -592,7 +581,7 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */ #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ /** * @} @@ -601,7 +590,7 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */ #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ /** * @} @@ -610,7 +599,7 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */ #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */ /** * @} @@ -619,7 +608,7 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */ #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ /** * @} @@ -628,7 +617,7 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */ #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ /** * @} @@ -637,7 +626,7 @@ typedef struct /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable * @{ */ -#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */ #define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */ /** * @} @@ -646,7 +635,7 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */ #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */ /** * @} @@ -655,7 +644,7 @@ typedef struct /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) +#define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -663,9 +652,9 @@ typedef struct /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) -#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) -#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) +#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */ /** * @} */ @@ -673,7 +662,7 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */ #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */ /** * @} @@ -682,7 +671,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */ /** * @} */ @@ -690,7 +679,7 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ /** * @} */ @@ -698,7 +687,7 @@ typedef struct /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ */ -#define UART_IT_MASK ((uint32_t)0x001F) /*!< UART interruptions flags mask */ +#define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */ /** * @} */ @@ -711,7 +700,6 @@ typedef struct * @} */ - /** * @} */ @@ -728,33 +716,33 @@ typedef struct #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) + } while(0U) /** @brief Flush the UART Data registers. - * @param __HANDLE__: UART handle. + * @param __HANDLE__: specifies the UART Handle. * @retval None */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__: specifies the UART Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: - * @arg UART_CLEAR_PEF, Parity Error Clear Flag - * @arg UART_CLEAR_FEF, Framing Error Clear Flag - * @arg UART_CLEAR_NEF, Noise detected Clear Flag - * @arg UART_CLEAR_OREF, OverRun Error Clear Flag - * @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag - * @arg UART_CLEAR_TCF, Transmission Complete Clear Flag - * @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag (not available on all devices) - * @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag - * @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag - * @arg UART_CLEAR_EOBF, End Of Block Clear Flag (not available on all devices) - * @arg UART_CLEAR_CMF, Character Match Clear Flag - * @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag (not available on all devices) + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices) + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag + * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices) + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices) * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -791,162 +779,146 @@ typedef struct /** @brief Check whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral (datasheet: up to five USART/UARTs) * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg UART_FLAG_REACK: Receive enable acknowledge flag - * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag - * @arg UART_FLAG_WUF: Wake up from stop mode flag - * @arg UART_FLAG_RWU: Receiver wake up flag - * @arg UART_FLAG_SBKF: Send Break flag - * @arg UART_FLAG_CMF: Character match flag - * @arg UART_FLAG_BUSY: Busy flag - * @arg UART_FLAG_ABRF: Auto Baud rate detection flag - * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag - * @arg UART_FLAG_EOBF: End of block flag - * @arg UART_FLAG_RTOF: Receiver timeout flag - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg UART_FLAG_LBD: LIN Break detection flag - * @arg UART_FLAG_TXE: Transmit data register empty flag - * @arg UART_FLAG_TC: Transmission Complete flag - * @arg UART_FLAG_RXNE: Receive data register not empty flag - * @arg UART_FLAG_IDLE: Idle Line detection flag - * @arg UART_FLAG_ORE: OverRun Error flag - * @arg UART_FLAG_NE: Noise Error flag - * @arg UART_FLAG_FE: Framing Error flag - * @arg UART_FLAG_PE: Parity Error flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_EOBF End of block flag + * @arg @ref UART_FLAG_RTOF Receiver timeout flag + * @arg @ref UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5) + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __INTERRUPT__: specifies the UART interrupt source to enable. * This parameter can be one of the following values: - * @arg UART_IT_WUF: Wakeup from stop mode interrupt - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __INTERRUPT__: specifies the UART interrupt source to disable. * This parameter can be one of the following values: - * @arg UART_IT_WUF: Wakeup from stop mode interrupt - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __IT__: specifies the UART interrupt to check. * This parameter can be one of the following values: - * @arg UART_IT_WUF: Wakeup from stop mode interrupt - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ORE: OverRun Error interrupt - * @arg UART_IT_NE: Noise Error interrupt - * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5) + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_ORE Overrun Error interrupt + * @arg @ref UART_IT_NE Noise Error interrupt + * @arg @ref UART_IT_FE Framing Error interrupt + * @arg @ref UART_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __IT__: specifies the UART interrupt source to check. * This parameter can be one of the following values: - * @arg UART_IT_WUF: Wakeup from stop mode interrupt - * @arg UART_IT_CM: Character match interrupt - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ORE: OverRun Error interrupt - * @arg UART_IT_NE: Noise Error interrupt - * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5) + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @arg @ref UART_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK))) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg UART_CLEAR_PEF: Parity Error Clear Flag - * @arg UART_CLEAR_FEF: Framing Error Clear Flag - * @arg UART_CLEAR_NEF: Noise detected Clear Flag - * @arg UART_CLEAR_OREF: OverRun Error Clear Flag - * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag - * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag - * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag - * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag - * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag - * @arg UART_CLEAR_EOBF: End Of Block Clear Flag - * @arg UART_CLEAR_CMF: Character Match Clear Flag - * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag + * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag * @retval None */ #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. * @param __HANDLE__: specifies the UART Handle. - * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or - * UART peripheral. (datasheet: up to five USART/UARTs) * @param __REQ__: specifies the request flag to set * This parameter can be one of the following values: - * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request - * @arg UART_SENDBREAK_REQUEST: Send Break Request - * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request - * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) /** @brief Enable the UART one bit sample method. * @param __HANDLE__: specifies the UART Handle. @@ -962,14 +934,12 @@ typedef struct /** @brief Enable UART. * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) -/** @brief Disable UART +/** @brief Disable UART. * @param __HANDLE__: specifies the UART Handle. - * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -990,7 +960,7 @@ typedef struct do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) + } while(0U) /** @brief Disable CTS flow control. * @note This macro allows to disable CTS hardware flow control for a given UART instance, @@ -1008,7 +978,7 @@ typedef struct do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) + } while(0U) /** @brief Enable RTS flow control. * @note This macro allows to enable RTS hardware flow control for a given UART instance, @@ -1026,7 +996,7 @@ typedef struct do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) + } while(0U) /** @brief Disable RTS flow control. * @note This macro allows to disable RTS hardware flow control for a given UART instance, @@ -1044,7 +1014,7 @@ typedef struct do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) + } while(0U) /** * @} @@ -1054,40 +1024,39 @@ typedef struct /** @defgroup UART_Private_Macros UART Private Macros * @{ */ - /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__: UART clock. * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__: UART clock. * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) -/** @brief Check UART Baud rate +/** @brief Check UART Baud rate. * @param __BAUDRATE__: Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001) +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U) /** @brief Check UART assertion time. * @param __TIME__: 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** @brief Check UART deassertion time. * @param __TIME__: 5-bit value deassertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) /** * @brief Ensure that UART frame number of stop bits is valid. @@ -1124,7 +1093,7 @@ typedef struct * @param __MODE__: UART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that UART state is valid. @@ -1163,9 +1132,9 @@ typedef struct * @param __MODE__: UART auto Baud rate detection mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) /** @@ -1346,11 +1315,12 @@ typedef struct ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + /** * @} */ -/* Include UART HAL Extension module */ +/* Include UART HAL Extended module */ #include "stm32f3xx_hal_uart_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -1389,12 +1359,23 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); /** * @} @@ -1439,11 +1420,12 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); + /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart_ex.h index 682ddeb153a93f797d7604c37216e70408533da6..2f5440626f34f0cdf29851cbe11241a1ebc6dfd2 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_uart_ex.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f3xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 - * @brief Header file of UART HAL Extension module. + * @version V1.4.0 + * @date 16-December-2016 + * @brief Header file of UART HAL Extended module. ****************************************************************************** * @attention * @@ -66,12 +66,12 @@ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) +#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */ #else -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ @@ -100,15 +100,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @} */ -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - /* IO operation functions *****************************************************/ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); -/** - * @} - */ /** @addtogroup UARTEx_Exported_Functions_Group3 * @{ @@ -119,6 +111,8 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + /** * @} */ @@ -139,7 +133,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -250,10 +244,10 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -288,9 +282,9 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #else -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -359,7 +353,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ @@ -382,36 +376,36 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ -} while(0) +} while(0U) #else #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ @@ -419,25 +413,25 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ -} while(0) +} while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart.h index d27b1879c12ff3fed0d462e3c11ff16e812fee7b..34907f85c0da7c52a01347b83d45a572d00e2e09 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_usart.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -100,14 +100,14 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; /** @@ -115,12 +115,12 @@ typedef enum */ typedef enum { - USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ }USART_ClockSourceTypeDef; @@ -137,13 +137,13 @@ typedef struct uint16_t TxXferSize; /*!< USART Tx Transfer size */ - uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ uint16_t RxXferSize; /*!< USART Rx Transfer size */ - uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ uint16_t Mask; /*!< USART Rx RDR register mask */ @@ -151,11 +151,11 @@ typedef struct DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ - __IO uint32_t ErrorCode; /*!< USART Error code */ + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; @@ -171,12 +171,12 @@ typedef struct /** @defgroup USART_Error USART Error * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ /** * @} */ @@ -184,10 +184,10 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */ +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */ /** * @} */ @@ -195,7 +195,7 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define USART_PARITY_NONE (0x00000000U) /*!< No parity */ #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** @@ -215,7 +215,7 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */ +#define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */ #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */ /** * @} @@ -224,8 +224,8 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */ -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */ +#define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */ +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */ /** * @} */ @@ -233,7 +233,7 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */ +#define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */ #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */ /** * @} @@ -242,7 +242,7 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */ #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */ /** * @} @@ -262,19 +262,20 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */ -#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */ -#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */ -#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */ -#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */ -#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */ -#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */ -#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */ -#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */ -#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */ -#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */ +#define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */ +#define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */ +#define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */ +#define USART_FLAG_LBDF (0x00000100U) /*!< USART LIN break detection flag */ +#define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */ +#define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */ +#define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */ +#define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */ +#define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */ +#define USART_FLAG_NE (0x00000004U) /*!< USART noise error */ +#define USART_FLAG_FE (0x00000002U) /*!< USART frame error */ +#define USART_FLAG_PE (0x00000001U) /*!< USART parity error */ /** * @} */ @@ -290,15 +291,15 @@ typedef struct * @{ */ -#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */ -#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */ -#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */ -#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */ -#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */ -#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */ -#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */ -#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */ -#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */ +#define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */ +#define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */ +#define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */ +#define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */ +#define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */ +#define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */ +#define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */ +#define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */ +#define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */ /** * @} */ @@ -320,7 +321,7 @@ typedef struct /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ */ -#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */ +#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */ /** * @} */ @@ -348,24 +349,24 @@ typedef struct do{ \ SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \ - } while(0) + } while(0U) /** @brief Check whether the specified USART flag is set or not. * @param __HANDLE__: specifies the USART Handle * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg USART_FLAG_REACK: Receive enable acknowledge flag - * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag - * @arg USART_FLAG_BUSY: Busy flag - * @arg USART_FLAG_CTS: CTS Change flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_CTS CTS Change flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) @@ -374,13 +375,13 @@ typedef struct * @param __HANDLE__: specifies the USART Handle. * @param __FLAG__: specifies the flag to check. * This parameter can be any combination of the following values: - * @arg USART_CLEAR_PEF - * @arg USART_CLEAR_FEF - * @arg USART_CLEAR_NEF - * @arg USART_CLEAR_OREF - * @arg USART_CLEAR_IDLEF - * @arg USART_CLEAR_TCF - * @arg USART_CLEAR_CTSF + * @arg @ref USART_CLEAR_PEF + * @arg @ref USART_CLEAR_FEF + * @arg @ref USART_CLEAR_NEF + * @arg @ref USART_CLEAR_OREF + * @arg @ref USART_CLEAR_IDLEF + * @arg @ref USART_CLEAR_TCF + * @arg @ref USART_CLEAR_CTSF * @retval None */ #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -419,32 +420,32 @@ typedef struct * @param __HANDLE__: specifies the USART Handle. * @param __INTERRUPT__: specifies the USART interrupt source to enable. * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__: specifies the USART Handle. * @param __INTERRUPT__: specifies the USART interrupt source to disable. * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) @@ -452,34 +453,34 @@ typedef struct * @param __HANDLE__: specifies the USART Handle. * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U))) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__: specifies the USART Handle. * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \ (((uint16_t)(__IT__)) & USART_IT_MASK))) @@ -488,13 +489,13 @@ typedef struct * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg USART_CLEAR_PEF: Parity Error Clear Flag - * @arg USART_CLEAR_FEF: Framing Error Clear Flag - * @arg USART_CLEAR_NEF: Noise detected Clear Flag - * @arg USART_CLEAR_OREF: OverRun Error Clear Flag - * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag - * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag - * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag * @retval None */ #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) @@ -503,8 +504,8 @@ typedef struct * @param __HANDLE__: specifies the USART Handle. * @param __REQ__: specifies the request flag to set. * This parameter can be one of the following values: - * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request * * @retval None */ @@ -546,10 +547,10 @@ typedef struct /** @brief Check USART Baud rate. * @param __BAUDRATE__: Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) + * divided by the smallest oversampling used on the USART (i.e. 8). * @retval Test result (TRUE or FALSE). */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U) /** * @brief Ensure that USART frame number of stop bits is valid. @@ -575,7 +576,7 @@ typedef struct * @param __MODE__: USART communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00) && ((__MODE__) != (uint32_t)0x00)) +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) /** * @brief Ensure that USART clock state is valid. @@ -619,7 +620,7 @@ typedef struct * @} */ -/* Include USART HAL Extension module */ +/* Include USART HAL Extended module */ #include "stm32f3xx_hal_usart_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -658,6 +659,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); @@ -665,6 +670,7 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart); /** * @} diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart_ex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart_ex.h index 2cd7937bbfcf9f8a57e71975bee4ac40e3930740..166ab662a348748ffbf953587a5bdc3469b37cd6 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart_ex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_usart_ex.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f3xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 - * @brief Header file of USART HAL Extension module. + * @version V1.4.0 + * @date 16-December-2016 + * @brief Header file of USART HAL Extended module. ****************************************************************************** * @attention * @@ -50,7 +50,7 @@ * @{ */ -/** @defgroup USARTEx USARTEx +/** @addtogroup USARTEx * @{ */ @@ -67,10 +67,10 @@ defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ #else -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F334x8 || */ @@ -79,7 +79,6 @@ * @} */ - /** * @} */ @@ -89,14 +88,14 @@ * @{ */ -/** @brief Reports the USART clock source. - * @param __HANDLE__: specifies the USART Handle - * @param __CLOCKSOURCE__ : output variable +/** @brief Report the USART clock source. + * @param __HANDLE__: specifies the USART Handle. + * @param __CLOCKSOURCE__: output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -131,9 +130,9 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #else -#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -202,7 +201,7 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0U) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ /** @brief Compute the USART mask to apply to retrieve the received data @@ -223,36 +222,36 @@ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x003F ; \ + (__HANDLE__)->Mask = 0x003FU ; \ } \ } \ -} while(0) +} while(0U) #else #define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ @@ -260,25 +259,25 @@ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x01FF ; \ + (__HANDLE__)->Mask = 0x01FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ } \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ { \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ { \ - (__HANDLE__)->Mask = 0x00FF ; \ + (__HANDLE__)->Mask = 0x00FFU ; \ } \ else \ { \ - (__HANDLE__)->Mask = 0x007F ; \ + (__HANDLE__)->Mask = 0x007FU ; \ } \ } \ -} while(0) +} while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ @@ -306,11 +305,6 @@ */ /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ -/* Peripheral Control functions ***********************************************/ -/* Peripheral State and Error functions ***************************************/ - /** * @} diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_wwdg.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_wwdg.h index 676481f586ebc1f0d9ebb095870652d500ffe341..f8fd231acaf4628cada30b72ef35c4f4c98533b6 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_wwdg.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_wwdg.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -69,10 +69,10 @@ typedef struct This parameter can be a value of @ref WWDG_Prescaler */ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU */ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU */ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ @@ -119,10 +119,10 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096U)/1U */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096U)/2U */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096U)/4U */ +#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096U)/8U */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_adc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_adc.h index 572b4f38e9e09b55be877fb7a7ef558c8cbc1185..d02092395be7bc08ab514112bb3a17f891d07168 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_adc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_adc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -5960,7 +5960,8 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular. + * without conversion stop command on going on group regular, + * without ADC disable command on going. * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None @@ -6142,7 +6143,8 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * @note On this STM32 serie, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, - * without conversion stop command on going on group injected. + * without conversion stop command on going on group injected, + * without ADC disable command on going. * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion * @param ADCx ADC instance * @retval None diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_bus.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_bus.h index 502f0619f4a0e6398f27c4b0f1df79a76e03981f..ba7dd8907ff7793cf72e7229daafee1c70fa96bb 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_bus.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_bus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_bus.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of BUS LL module. @verbatim diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_comp.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_comp.h index 098c405dae8b92d8f4a91e0d76eb52b0d9b11da0..c77780135c257b321a28b467b0e4b86d1ef4d422 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_comp.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_comp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_comp.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of COMP LL module. ****************************************************************************** * @attention @@ -56,7 +56,7 @@ extern "C" { /* (comparator output blanking, ...) (refer to reference manual). */ /* - STM32F37x: */ /* COMP IP with 2 instances */ -/* This file contains the drivers of these ADC IP, located in 2 area */ +/* This file contains the drivers of these COMP IP, located in 2 area */ /* delimited by compilation switches. */ #if defined(COMP_V1_3_0_0) @@ -173,16 +173,29 @@ typedef struct /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection * @{ */ -#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7 (COMP instance availability depends on the selected device) (exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO1, PA7, PD12, PD11, PA0 are not available and are replaced respectively by PA3, PB13, PB11, PC1) (exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: in LL_COMP_INPUT_PLUS_IO1, PD11 is replaced by PB11)) */ -#if defined(COMP_CSR_COMPxNONINSEL) -#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 ( pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7 (COMP instance availability depends on the selected device) (exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO2, PD14, PE7 are not available and are replaced respectively by PB14, PB0) (exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: input plus IO2 available only on COMP instance: COMP6)) */ +#if !defined(COMP_CSR_COMPxNONINSEL) +#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, PA3 for COMP2 (except STM32F334xx: PA7), PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */ +#define LL_COMP_INPUT_PLUS_IO2 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO2: Same as IO1 */ #else -#define LL_COMP_INPUT_PLUS_IO2 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO2 (PB11 for COMP6 (COMP instance availability depends on the selected device) (Device without comparator input plus configurable: corresponds to setting "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to other STM32F3 devices, depending on comparator instance (refer to reference manual)) */ +#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */ +#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 (pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7) (COMP instance availability depends on the selected device) */ #endif #if defined(STM32F302xC) || defined(STM32F302xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx) #define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */ + +/* Note: Comparator input plus specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + #elif defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) -#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */ +#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP2 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */ + +/* Note: Comparator input plus specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + #endif /** * @} @@ -196,17 +209,27 @@ typedef struct #define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ #define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to VrefInt */ #define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F302xE) +/* This device has no comparator input minus DAC1_CH2 */ +#else #define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ -#if defined(STM32F301x8) || defined(STM32F318xx) -/* This device has no comparator input minus IO1 */ -#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) -#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2 (COMP instance availability depends on the selected device)) */ +#endif +#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) +#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2) */ #else #define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2, PD15 for COMP3, PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, PC0 for COMP7 (COMP instance availability depends on the selected device)) */ #endif #define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO2 ( PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, PB15 for COMP6 (COMP instance availability depends on the selected device)) */ -#if defined(STM32F301x8) || defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) || defined(STM32F373xC) || defined(STM32F378xx) +#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F302x8) || defined(STM32F303x8) || defined(STM32F328xx) +/* This device has no comparator input minus IO3 */ +#else +#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */ +#endif +#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */ +#if defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) #define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMPxINSEL_3 ) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */ +#else +/* This device has no comparator input minus DAC2_CH1 */ #endif /** * @} @@ -235,10 +258,10 @@ typedef struct #define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */ #define LL_COMP_OUTPUT_TIM1_BKIN2 (COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2 (BKIN2) */ -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#if defined(STM32F301x8) || defined(STM32F318xx) /* Note: Output redirection specific to COMP instance: COMP2 */ #define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM1_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ /* Note: Output redirection specific to COMP instance: COMP4 */ @@ -250,12 +273,32 @@ typedef struct #define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */ #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */ -#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) +/* Note: Output redirection specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +/* Note: Some output redirections cannot have a generic naming, */ +/* due to literal value different depending on COMP instance. */ +/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */ +/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */ +#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +/* Note: Output redirection specific to COMP instances, defined with */ +/* partially generic naming grouping COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + +#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)|| defined(STM32F302x8) /* Note: Output redirection specific to COMP instance: COMP2, COMP4 */ #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */ /* Note: Output redirection specific to COMP instance: COMP2 */ #define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM1_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ #define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ @@ -269,32 +312,80 @@ typedef struct #define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */ #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */ +/* Note: Output redirection specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +/* Note: Some output redirections cannot have a generic naming, */ +/* due to literal value different depending on COMP instance. */ +/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */ +/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */ +#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +/* Note: Output redirection specific to COMP instances, defined with */ +/* partially generic naming grouping COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + #elif defined(STM32F302xC) || defined(STM32F302xE) /* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4 */ #define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */ /* Note: Output redirection specific to COMP instance: COMP1, COMP2 */ -#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ /* Note: Output redirection specific to COMP instance: COMP4 */ -#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */ -#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */ -#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */ -#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */ +#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */ +#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */ +#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */ +#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */ /* Note: Output redirection specific to COMP instance: COMP6 */ -#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */ -#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */ -#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */ -#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */ -#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */ + +/* Note: Output redirection specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +/* Note: Some output redirections cannot have a generic naming, */ +/* due to literal value different depending on COMP instance. */ +/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */ +/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */ +#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +/* Note: Output redirection specific to COMP instances, defined with */ +/* partially generic naming grouping COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ #elif defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx) /* Note: Output redirection common to all COMP instances */ -#define LL_COMP_OUTPUT_TIM8_BKIN (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input (BKIN) */ -#define LL_COMP_OUTPUT_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */ -#define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */ +#define LL_COMP_OUTPUT_TIM8_BKIN (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input (BKIN) */ +#define LL_COMP_OUTPUT_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */ +#define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */ #if defined(STM32F303xE) || defined(STM32F398xx) #define LL_COMP_OUTPUT_TIM20_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input (BKIN) */ #define LL_COMP_OUTPUT_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */ @@ -309,9 +400,9 @@ typedef struct /* Note: Output redirection specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */ #define LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 OCREF clear (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */ /* Note: Output redirection specific to COMP instance: COMP1, COMP2 */ -#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */ -#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ #if defined(STM32F303xE) || defined(STM32F398xx) #define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */ #endif @@ -319,28 +410,65 @@ typedef struct #define LL_COMP_OUTPUT_TIM3_IC2_COMP3 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM3 input capture 2 (specific to COMP instance: COMP3) */ #define LL_COMP_OUTPUT_TIM4_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP3) */ #define LL_COMP_OUTPUT_TIM15_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP3) */ -#define LL_COMP_OUTPUT_TIM15_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */ +#define LL_COMP_OUTPUT_TIM15_BKIN_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */ /* Note: Output redirection specific to COMP instance: COMP4 */ #define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */ -#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */ +#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */ #define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */ #define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */ /* Note: Output redirection specific to COMP instance: COMP5 */ #define LL_COMP_OUTPUT_TIM2_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP5) */ -#define LL_COMP_OUTPUT_TIM4_IC3_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */ +#define LL_COMP_OUTPUT_TIM4_IC3_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */ #define LL_COMP_OUTPUT_TIM17_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM17 input capture 1 (specific to COMP instance: COMP5) */ -#define LL_COMP_OUTPUT_TIM16_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 break input (BKIN) */ +#define LL_COMP_OUTPUT_TIM16_BKIN_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 break input (BKIN) */ /* Note: Output redirection specific to COMP instance: COMP6 */ #define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */ #define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */ -#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */ +#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */ #define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */ #define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */ /* Note: Output redirection specific to COMP instance: COMP7 */ #define LL_COMP_OUTPUT_TIM1_IC2_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP7) */ #define LL_COMP_OUTPUT_TIM2_IC3_COMP7 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP7) */ #define LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM17 OCREF clear (specific to COMP instance: COMP7) */ -#define LL_COMP_OUTPUT_TIM17_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */ +#define LL_COMP_OUTPUT_TIM17_BKIN_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */ + +/* Note: Output redirection specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +/* Note: Some output redirections cannot have a generic naming, */ +/* due to literal value different depending on COMP instance. */ +/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */ +/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */ +#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM1_IC2 LL_COMP_OUTPUT_TIM1_IC2_COMP7 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC1 LL_COMP_OUTPUT_TIM2_IC1_COMP5 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC3 LL_COMP_OUTPUT_TIM2_IC3_COMP7 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC2 LL_COMP_OUTPUT_TIM3_IC2_COMP3 /*!< COMP output connected to TIM3 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP3 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC3 LL_COMP_OUTPUT_TIM4_IC3_COMP5 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM8_OCCLR LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 /*!< COMP output connected to TIM8 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_IC1 LL_COMP_OUTPUT_TIM15_IC1_COMP3 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP3 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP5 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM17_IC1 LL_COMP_OUTPUT_TIM17_IC1_COMP5 /*!< COMP output connected to TIM17 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM17_BKIN LL_COMP_OUTPUT_TIM17_BKIN_COMP7 /*!< COMP output connected to TIM17 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM17_OCCLR LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 /*!< COMP output connected to TIM17 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#if defined(STM32F303xE) || defined(STM32F398xx) +#define LL_COMP_OUTPUT_TIM20_OCCLR LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 /*!< COMP output connected to TIM20 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#endif #endif #endif @@ -374,21 +502,43 @@ typedef struct #define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */ #define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */ +/* Note: Output blanking source specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + #elif defined(STM32F302xE) || defined(STM32F302xC) /* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */ #define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2) */ #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */ #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */ /* Note: Output blanking source specific to COMP instance: COMP4 */ -#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */ -#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */ +#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */ +#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */ /* Note: Output blanking source specific to COMP instance: COMP6 */ -#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */ -#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */ +#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */ + +/* Note: Output blanking source specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ #elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) /* Note: Output blanking source specific to COMP instance: COMP1, COMP2, COMP7 */ -#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2, COMP7) */ +#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2, COMP7) */ /* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */ #define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */ #define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */ @@ -397,10 +547,23 @@ typedef struct /* Note: Output blanking source specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */ #define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */ /* Note: Output blanling source specific to COMP instance: COMP6, COMP7 */ -#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (COMP_CSR_COMPxBLANKING_2) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6, COMP7) */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (COMP_CSR_COMPxBLANKING_2) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6, COMP7) */ /* Note: Output blanking source specific to COMP instance: COMP4 */ #define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */ #define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */ + +/* Note: Output blanking source specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM8_OC5 LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 /*!< Comparator output blanking source TIM8 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ + #endif #endif /** @@ -566,8 +729,8 @@ typedef struct * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2) * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2) * - * (1) Parameter available on devices: STM32F303xC/D/E, STM32F358xx, STM32F398xx, STM32F302xC/D/E - * (2) Parameter available on devices: STM32F303xC/D/E, STM32F358xx, STM32F398xx + * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC + * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC * @retval None */ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) @@ -593,8 +756,8 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2) * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2) * - * (1) Parameter available on devices: STM32F303xC/D/E, STM32F358xx, STM32F398xx, STM32F302xC/D/E - * (2) Parameter available on devices: STM32F303xC/D/E, STM32F358xx, STM32F398xx + * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC + * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC */ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) { @@ -624,7 +787,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1) * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) * - * (1) Parameter available only on devices: STM32F303xB/C, STM32F358xC + * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC * @retval None */ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode) @@ -648,7 +811,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1) * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1) * - * (1) Parameter available only on devices: STM32F303xB/C, STM32F358xC + * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC */ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) { @@ -687,24 +850,24 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT * @arg @ref LL_COMP_INPUT_MINUS_VREFINT * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 - * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3) * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2) - * @arg @ref LL_COMP_INPUT_MINUS_IO1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO1 * @arg @ref LL_COMP_INPUT_MINUS_IO2 - * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8.\n - * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx, STM32F37xx. + * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n + * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n + * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n * @param InputPlus This parameter can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) - * @arg @ref LL_COMP_INPUT_PLUS_IO2 (2) - * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (3) - * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (4) + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) * - * (1) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO1, PA7, PD12, PD11, PA0 are not available and are replaced respectively by PA3, PB13, PB11, PC1.\n - * Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: in LL_COMP_INPUT_PLUS_IO1, PD11 is replaced by PB11.\n - * (2) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO2, PD14, PE7 are not available and are replaced respectively by PB14, PB0.\n - * Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: input plus IO2 available only on COMP instance: COMP6.\n - * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, defined(STM32F358xx, STM32F398xx).\n - * (4) Parameter available on devices: STM32F301x8, STM32F318xx, STM32F302x8. + * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n + * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n + * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. * @retval None */ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus) @@ -741,17 +904,14 @@ __STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMin * @rmtoll CSR NONINSEL LL_COMP_SetInputPlus * @param COMPx Comparator instance * @param InputPlus This parameter can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) - * @arg @ref LL_COMP_INPUT_PLUS_IO2 (2) - * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (3) - * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (4) + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) * - * (1) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO1, PA7, PD12, PD11, PA0 are not available and are replaced respectively by PA3, PB13, PB11, PC1.\n - * Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: in LL_COMP_INPUT_PLUS_IO1, PD11 is replaced by PB11.\n - * (2) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO2, PD14, PE7 are not available and are replaced respectively by PB14, PB0.\n - * Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: input plus IO2 available only on COMP instance: COMP6.\n - * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, defined(STM32F358xx, STM32F398xx).\n - * (4) Parameter available on devices: STM32F301x8, STM32F318xx, STM32F302x8. + * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n + * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n + * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. * @retval None */ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus) @@ -779,13 +939,14 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @rmtoll CSR NONINSEL LL_COMP_GetInputPlus * @param COMPx Comparator instance * @retval Returned value can be one of the following values: - * @arg @ref LL_COMP_INPUT_PLUS_IO1 (1) - * @arg @ref LL_COMP_INPUT_PLUS_IO2 (2) + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2) + * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3) * - * (1) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO1, PA7, PD12, PD11, PA0 are not available and are replaced respectively by PA3, PB13, PB11, PC1.\n - Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: in LL_COMP_INPUT_PLUS_IO1, PD11 is replaced by PB11.\n - * (2) Exception on devices STM32F302x6/8, STM32F303x6/8: in LL_COMP_INPUT_PLUS_IO2, PD14, PE7 are not available and are replaced respectively by PB14, PB0.\n - * Exception on devices STM32F302x6/8/D/E, STM32F303x6/8/D/E, STM32F398xE: input plus IO2 available only on COMP instance: COMP6. + * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n + * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n + * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8. */ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) { @@ -823,12 +984,15 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT * @arg @ref LL_COMP_INPUT_MINUS_VREFINT * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 - * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3) * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2) - * @arg @ref LL_COMP_INPUT_MINUS_IO1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO1 * @arg @ref LL_COMP_INPUT_MINUS_IO2 - * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8.\n - * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx, STM32F37xx. + * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n + * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n + * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n * @retval None */ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus) @@ -849,12 +1013,15 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT * @arg @ref LL_COMP_INPUT_MINUS_VREFINT * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 - * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 + * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3) * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2) - * @arg @ref LL_COMP_INPUT_MINUS_IO1 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO1 * @arg @ref LL_COMP_INPUT_MINUS_IO2 - * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8.\n - * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx, STM32F37xx. + * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1) + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n + * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n + * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n */ __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) { @@ -871,7 +1038,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1) * @arg @ref LL_COMP_HYSTERESIS_HIGH (1) * - * (1) Parameter available only on devices: STM32F303xB/C, STM32F358xC + * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC * @retval None */ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis) @@ -895,7 +1062,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1) * @arg @ref LL_COMP_HYSTERESIS_HIGH (1) * - * (1) Parameter available only on devices: STM32F303xB/C, STM32F358xC + * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC */ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) { @@ -936,12 +1103,12 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4) * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4) * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4) - * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP24 (6) + * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6) * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2) - * @arg @ref LL_COMP_OUTPUT_TIM1_IC4_COMP2 (2) + * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1) * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3) - * @arg @ref LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 (3) + * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3) * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5) * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4) @@ -1000,12 +1167,12 @@ __STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t Ou * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4) * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4) * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4) - * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP24 (6) + * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6) * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2) - * @arg @ref LL_COMP_OUTPUT_TIM1_IC4_COMP2 (2) + * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1) * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3) - * @arg @ref LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 (3) + * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3) * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3) * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5) * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4) @@ -1427,6 +1594,10 @@ typedef struct #define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ #define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ #define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */ +#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO2 (pin PA6 for COMP1 & COMP2) */ +#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1 & COMP2) */ +#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1 & COMP2) */ +#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */ /** * @} */ @@ -1447,14 +1618,36 @@ typedef struct */ /* Note: Output redirection is common for COMP1 and COMP2 */ #define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) */ -#define LL_COMP_OUTPUT_TIM16_BKIN (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM16 break input (BKIN) */ -#define LL_COMP_OUTPUT_TIM4_IC1 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM4 input capture 1 */ -#define LL_COMP_OUTPUT_TIM4_OCCLR (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM4 OCREF clear */ #define LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2) /*!< COMP output connected to TIM2 input capture 4 */ #define LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear */ -#define LL_COMP_OUTPUT_TIM3_IC1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 */ -#define LL_COMP_OUTPUT_TIM3_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear */ +/* Note: Output redirection specific to COMP instance: COMP1 */ +#define LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) (specific to COMP instance: COMP1) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP1) */ +#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1) */ +#define LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM5 input capture 4 (specific to COMP instance: COMP1) */ +#define LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM5 OCREF clear (specific to COMP instance: COMP1) */ + +/* Note: Output redirection specific to COMP instance: COMP2 */ +#define LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM16 break input (BKIN) (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM4 OCREF clear (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */ +#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2) */ + +/* Note: Output redirection specific to COMP instances, defined with */ +/* generic naming not taking into account COMP instance constraints. */ +/* Refer to literal definitions above for COMP instance constraints. */ +/* Note: Some output redirections cannot have a generic naming, */ +/* due to literal value different depending on COMP instance. */ +/* (For exemple: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and */ +/* LL_COMP_OUTPUT_TIM3_IC1_COMP2). */ +#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 /*!< COMP output connected to TIM4 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1 /*!< COMP output connected to TIM5 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ +#define LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 /*!< COMP output connected to TIM5 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */ /** * @} */ @@ -1671,6 +1864,10 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 * @param InputPlus This parameter can be one of the following values: * @arg @ref LL_COMP_INPUT_PLUS_IO1 * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1) @@ -1752,6 +1949,10 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 * @retval None */ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus) @@ -1776,6 +1977,10 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @arg @ref LL_COMP_INPUT_MINUS_IO2 + * @arg @ref LL_COMP_INPUT_MINUS_IO3 + * @arg @ref LL_COMP_INPUT_MINUS_IO4 + * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 */ __STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) { diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_cortex.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_cortex.h index e92f0602bb7d348078b61167c0ce40c81febb138..db812b5357f5984a46f6b36f61632a3c9d51995f 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_cortex.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_cortex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CORTEX LL module. @verbatim ============================================================================== diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_crc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_crc.h index 27f433e7b7dcf80976d5485dbc962eafe67317a7..c3504c09731a3d94d65bb6b130d8c9db19ca10f3 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_crc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_crc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of CRC LL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dac.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dac.h index f795249b7ce2ae8a084c6502b08ce4ed27b7afaf..6cc69d28a72faf03b2b32e41336487519c06cbe6 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dac.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_dac.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -70,8 +70,8 @@ extern "C" { /* - channel bits position into register SWTRIG */ /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ -#define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ @@ -82,22 +82,22 @@ extern "C" { #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U) -#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U) -#define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U) +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) -#define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) @@ -105,13 +105,13 @@ extern "C" { /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -238,7 +238,7 @@ typedef struct */ #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ @@ -248,7 +248,7 @@ typedef struct #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F303x8) || defined(STM32F328xx) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ @@ -256,7 +256,7 @@ typedef struct #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ @@ -264,13 +264,13 @@ typedef struct #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F301x8) || defined(STM32F318xx) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F373xC) || defined(STM32F378xx) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ @@ -280,7 +280,7 @@ typedef struct #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F334x8) -#define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ @@ -298,7 +298,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** @@ -308,7 +308,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ @@ -327,7 +327,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ @@ -346,7 +346,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2) @@ -361,8 +361,8 @@ typedef struct /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ -#define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ /** * @} */ @@ -400,7 +400,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -413,7 +413,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ /** * @} */ @@ -533,7 +533,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U)) + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dma.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dma.h index b7c90fd971ad1cf25dc72d7b49bde91695215fe1..90d43c2206e88b1d88b6185a0cf0582948909b41 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dma.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_dma.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DMA LL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_exti.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_exti.h index b501e63ed68be799253a8fb9057e17d86661f4cb..03d671c205dcd0f4db0573755f209eadfd97c74e 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_exti.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_exti.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_exti.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -127,7 +127,9 @@ typedef struct #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ #endif #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ #if defined(EXTI_IMR_IM20) #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ @@ -167,14 +169,29 @@ typedef struct #if defined(EXTI_32_63_SUPPORT) #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#if defined(EXTI_IMR2_IM33) #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif +#if defined(EXTI_IMR2_IM34) #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif +#if defined(EXTI_IMR2_IM35) #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif +#if defined(EXTI_IMR2_IM36) #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif +#if defined(EXTI_IMR2_IM37) #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#endif +#if defined(EXTI_IMR2_IM38) #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#endif +#if defined(EXTI_IMR2_IM39) #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#endif #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + #endif #define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_fmc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_fmc.h index 6ac08fd8ed1430cea4191ad424415d1afa4e6fd5..d051b08dd898e256c32b481f53700653aa3e2e3f 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_fmc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_fmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_fmc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_gpio.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_gpio.h index 52c048cb0224fbdcc760480d102818e53d6bfd51..cddcaf28411c16f2b9de6aa82f0ce127d85bb164 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_gpio.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_gpio.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention @@ -462,7 +462,6 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) { diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_hrtim.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_hrtim.h index 71b46129f70e5f5dfff46b48f0c0ffbbbfdab8b6..8fb080bfcddc384972699ba03044f2ce325fbf33 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_hrtim.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_hrtim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_hrtim.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of HRTIM LL module. ****************************************************************************** * @attention @@ -307,7 +307,7 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_ES_INIT HRTIM Exported Init structure +/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure * @{ */ /* TO BE COMPLETED */ @@ -1414,7 +1414,7 @@ operation */ * @{ */ -/** @defgroup HRTIM_EM_WRITE_READ Common Write and read registers Macros +/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ @@ -1605,7 +1605,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) { - SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> POSITION_VAL(HRTIM_MCR_MCEN)) & HRTIM_CR1_UDIS_MASK)); + SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); } /** @@ -1629,7 +1629,7 @@ __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) { - CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> POSITION_VAL(HRTIM_MCR_MCEN)) & HRTIM_CR1_UDIS_MASK)); + CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); } /** @@ -1653,7 +1653,7 @@ __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) { - SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> POSITION_VAL(HRTIM_MCR_MCEN)) & HRTIM_CR2_SWUPD_MASK)); + SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); } /** @@ -1676,8 +1676,7 @@ __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers */ __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) { - SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> POSITION_VAL(HRTIM_MCR_MCEN)) << POSITION_VAL( - HRTIM_CR2_MRST)) & HRTIM_CR2_SWRST_MASK)); + SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK)); } /** @@ -1807,134 +1806,134 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Configure an ADC trigger. * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n - * @rmtoll CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n - * @rmtoll CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n - * @rmtoll CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n - * @rmtoll ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig + * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n + * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n + * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n + * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n + * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n + * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n + * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig * @param HRTIMx High Resolution Timer instance * @param ADCTrig This parameter can be one of the following values: * @arg @ref LL_HRTIM_ADCTRIG_1 @@ -2033,9 +2032,9 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT /** * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register. * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n - * @rmtoll CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n - * @rmtoll CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n - * @rmtoll CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate + * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n + * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n + * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate * @note When the preload is disabled in the source timer, the HRTIM_ADCxR * registers are not preloaded either: a write access will result in an * immediate update of the trigger source. @@ -2063,9 +2062,9 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A /** * @brief Get the source timer triggering the update of the HRTIM_ADCxR register. * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n - * @rmtoll CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n - * @rmtoll CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n - * @rmtoll CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate + * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n + * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n + * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate * @param HRTIMx High Resolution Timer instance * @param ADCTrig This parameter can be one of the following values: * @arg @ref LL_HRTIM_ADCTRIG_1 @@ -2089,130 +2088,130 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion. * @rmtoll ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n - * @rmtoll ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc + * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n + * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n + * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n + * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n + * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc * @param HRTIMx High Resolution Timer instance * @param ADCTrig This parameter can be one of the following values: * @arg @ref LL_HRTIM_ADCTRIG_1 @@ -2302,130 +2301,130 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT /** * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion. * @rmtoll ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n - * @rmtoll ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc + * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n + * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n + * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n + * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n + * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc * @param HRTIMx High Resolution Timer instance * @param ADCTrig This parameter can be one of the following values: * @arg @ref LL_HRTIM_ADCTRIG_1 @@ -2514,7 +2513,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Configure the DLL calibration mode. * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n - * @rmtoll DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration + * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration * @param HRTIMx High Resolution Timer instance * @param Mode This parameter can be one of the following values: * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT @@ -2622,7 +2621,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui /** * @brief Set the timer clock prescaler ratio. * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n - * @rmtoll TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler + * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0]. * @note The prescaling ratio cannot be modified once the timer counter is enabled. * @param HRTIMx High Resolution Timer instance @@ -2646,7 +2645,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); } @@ -2654,7 +2653,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Get the timer clock prescaler ratio * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n - * @rmtoll TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler + * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2675,7 +2674,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); } @@ -2683,9 +2682,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable). * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n - * @rmtoll MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n - * @rmtoll TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n - * @rmtoll TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode + * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n + * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n + * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2702,7 +2701,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); } @@ -2710,9 +2709,9 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get the counter operating mode mode * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n - * @rmtoll MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n - * @rmtoll TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n - * @rmtoll TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode + * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n + * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n + * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2728,7 +2727,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); } @@ -2736,7 +2735,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint /** * @brief Enable the half duty-cycle mode. * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n - * @rmtoll TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode + * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR) * active register is automatically updated with HRTIM_MPER/2 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written. @@ -2752,7 +2751,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2760,7 +2759,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the half duty-cycle mode. * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n - * @rmtoll TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode + * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2773,7 +2772,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_HALF); } @@ -2781,7 +2780,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Indicate whether half duty-cycle mode is enabled for a given timer. * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n - * @rmtoll TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode + * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2794,7 +2793,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF); } @@ -2802,7 +2801,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, u /** * @brief Enable the timer start when receiving a synchronization input event. * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n - * @rmtoll TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync + * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2815,7 +2814,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2823,7 +2822,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Disable the timer start when receiving a synchronization input event. * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n - * @rmtoll TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync + * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2836,7 +2835,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -2844,7 +2843,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint /** * @brief Indicate whether the timer start when receiving a synchronization input event. * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n - * @rmtoll TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync + * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2857,7 +2856,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM); } @@ -2865,7 +2864,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx /** * @brief Enable the timer reset when receiving a synchronization input event. * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n - * @rmtoll TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync + * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2878,7 +2877,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2886,7 +2885,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Disable the timer reset when receiving a synchronization input event. * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n - * @rmtoll TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync + * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2899,7 +2898,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -2907,7 +2906,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint /** * @brief Indicate whether the timer reset when receiving a synchronization input event. * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n - * @rmtoll TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync + * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2920,7 +2919,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM); } @@ -2928,7 +2927,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx /** * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n - * @rmtoll TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig + * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2946,7 +2945,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); } @@ -2954,7 +2953,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n - * @rmtoll TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig + * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -2971,7 +2970,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); } @@ -2979,7 +2978,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Enable the timer registers preload mechanism. * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n - * @rmtoll TIMxCR PREEN LL_HRTIM_TIM_EnablePreload + * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload * @note When the preload mode is enabled, accessed registers are shadow registers. * Their content is transferred into the active register after an update request, * either software or synchronized with an event. @@ -2995,7 +2994,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3003,7 +3002,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the timer registers preload mechanism. * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n - * @rmtoll TIMxCR PREEN LL_HRTIM_TIM_DisablePreload + * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3016,7 +3015,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -3024,7 +3023,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the timer registers preload mechanism is enabled. * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n - * @rmtoll TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload + * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3037,7 +3036,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN); } @@ -3045,12 +3044,12 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, ui /** * @brief Set the timer register update trigger. * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n - * @rmtoll TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig + * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n + * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n + * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n + * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n + * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n + * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3080,7 +3079,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3088,11 +3087,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Set the timer register update trigger. * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n - * @rmtoll TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n - * @rmtoll TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n - * @rmtoll TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n - * @rmtoll TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n - * @rmtoll TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig + * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n + * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n + * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n + * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n + * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3121,7 +3120,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -3129,7 +3128,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])). * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n - * @rmtoll TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating + * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3159,7 +3158,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); } @@ -3167,7 +3166,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Get the timer registers update condition. * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n - * @rmtoll TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating + * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3196,7 +3195,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); } @@ -3215,7 +3214,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); @@ -3235,7 +3234,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); @@ -3255,7 +3254,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL); @@ -3264,7 +3263,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIM /** * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode). * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n - * @rmtoll TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode + * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode * @note In auto-delayed mode the compare match occurs independently from the timer counter value. * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: @@ -3286,17 +3285,17 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIM __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2); - MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), Mode); + MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } /** * @brief Get the functioning mode of the compare unit. * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n - * @rmtoll TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode + * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -3315,7 +3314,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2); @@ -3325,7 +3324,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint /** * @brief Set the timer counter value. * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n - * @rmtoll CNTxR CNTx LL_HRTIM_TIM_SetCounter + * CNTxR CNTx LL_HRTIM_TIM_SetCounter * @note This function can only be called when the timer is stopped. * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least * significant bits of the counter are not significant. They cannot be @@ -3345,7 +3344,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); @@ -3354,7 +3353,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Get actual timer counter value. * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n - * @rmtoll CNTxR CNTx LL_HRTIM_TIM_GetCounter + * CNTxR CNTx LL_HRTIM_TIM_GetCounter * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3367,7 +3366,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); @@ -3376,7 +3375,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Set the timer period value. * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n - * @rmtoll PERxR PERx LL_HRTIM_TIM_SetPeriod + * PERxR PERx LL_HRTIM_TIM_SetPeriod * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3390,7 +3389,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); @@ -3399,7 +3398,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Get actual timer period value. * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n - * @rmtoll PERxR PERx LL_HRTIM_TIM_GetPeriod + * PERxR PERx LL_HRTIM_TIM_GetPeriod * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3412,7 +3411,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); @@ -3421,7 +3420,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Set the timer repetition period value. * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n - * @rmtoll REPxR REPx LL_HRTIM_TIM_SetRepetition + * REPxR REPx LL_HRTIM_TIM_SetRepetition * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3435,7 +3434,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); @@ -3444,7 +3443,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual timer repetition period value. * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n - * @rmtoll REPxR REPx LL_HRTIM_TIM_GetRepetition + * REPxR REPx LL_HRTIM_TIM_GetRepetition * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3457,7 +3456,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); @@ -3466,7 +3465,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Set the compare value of the compare unit 1. * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n - * @rmtoll CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1 + * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3482,7 +3481,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); @@ -3491,7 +3490,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Get actual compare value of the compare unit 1. * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n - * @rmtoll CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1 + * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3506,7 +3505,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); @@ -3515,7 +3514,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the compare value of the compare unit 2. * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n - * @rmtoll CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2 + * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3531,7 +3530,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); @@ -3540,7 +3539,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Get actual compare value of the compare unit 2. * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n - * @rmtoll CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n + * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3555,7 +3554,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); @@ -3564,7 +3563,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the compare value of the compare unit 3. * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n - * @rmtoll CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3 + * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3580,7 +3579,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); @@ -3589,7 +3588,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Get actual compare value of the compare unit 3. * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n - * @rmtoll CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3 + * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3604,7 +3603,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); @@ -3613,7 +3612,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the compare value of the compare unit 4. * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n - * @rmtoll CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4 + * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3629,7 +3628,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); @@ -3638,7 +3637,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Get actual compare value of the compare unit 4. * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n - * @rmtoll CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4 + * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -3653,7 +3652,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); @@ -3662,35 +3661,35 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the reset trigger of a timer counter. * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n - * @rmtoll RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig + * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n + * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n + * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig * @note The reset of the timer counter can be triggered by up to 30 events * that can be selected among the following sources: * @arg The timing unit: Compare 2, Compare 4 and Update (3 events). @@ -3740,7 +3739,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); @@ -3749,35 +3748,35 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Get actual reset trigger of a timer counter. * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n - * @rmtoll RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig + * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n + * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n + * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -3820,7 +3819,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); @@ -3840,7 +3839,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); @@ -3860,7 +3859,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); @@ -3869,37 +3868,37 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the trigger of a capture unit for a given timer. * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n - * @rmtoll CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig + * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n + * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -3948,7 +3947,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, uint32_t CaptureTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4)); WRITE_REG(*pReg, CaptureTrig); @@ -3957,37 +3956,37 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual trigger of a capture unit for a given timer. * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n - * @rmtoll CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig + * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n + * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4034,7 +4033,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4)); return (READ_REG(*pReg)); @@ -4054,7 +4053,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); @@ -4074,7 +4073,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); @@ -4094,7 +4093,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN); @@ -4103,7 +4102,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u /** * @brief Set the delayed protection (DLYPRT) mode. * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n - * @rmtoll OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode + * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode * @note This function must be called prior enabling the delayed protection * @note Balanced Idle mode is only available in push-pull mode * @param HRTIMx High Resolution Timer instance @@ -4138,7 +4137,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); @@ -4147,7 +4146,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get the delayed protection (DLYPRT) mode. * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n - * @rmtoll OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode + * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4179,7 +4178,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); @@ -4200,7 +4199,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); @@ -4221,7 +4220,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); @@ -4241,7 +4240,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN); @@ -4250,10 +4249,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin /** * @brief Enable the fault channel(s) for a given timer. * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n - * @rmtoll FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n - * @rmtoll FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n - * @rmtoll FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n - * @rmtoll FLTxR FLT5EN LL_HRTIM_TIM_EnableFault + * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n + * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n + * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n + * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4271,7 +4270,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); @@ -4280,10 +4279,10 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Disable the fault channel(s) for a given timer. * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n - * @rmtoll FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n - * @rmtoll FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n - * @rmtoll FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n - * @rmtoll FLTxR FLT5EN LL_HRTIM_TIM_DisableFault + * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n + * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n + * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n + * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4301,7 +4300,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); @@ -4310,10 +4309,10 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Indicate whether the fault channel is enabled for a given timer. * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n - * @rmtoll FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n - * @rmtoll FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n - * @rmtoll FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n - * @rmtoll FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault + * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n + * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n + * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n + * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4331,7 +4330,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, Fault) == (Fault)); @@ -4352,7 +4351,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); @@ -4361,11 +4360,11 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Define how the timer behaves during a burst mode operation. * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n - * @rmtoll BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n - * @rmtoll BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n - * @rmtoll BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n - * @rmtoll BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n - * @rmtoll BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption + * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n + * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n + * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n + * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n + * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption * @note This function must not be called when the burst mode is enabled * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: @@ -4382,18 +4381,18 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer); } /** * @brief Retrieve how the timer behaves during a burst mode operation. * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n - * @rmtoll BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n - * @rmtoll BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n - * @rmtoll BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n - * @rmtoll BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n - * @rmtoll BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption + * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n + * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n + * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n + * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n + * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -4408,42 +4407,42 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); } /** * @brief Program which registers are to be written by Burst DMA transfers. * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIAEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n - * @rmtoll BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA + * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIAEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n + * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -4494,7 +4493,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer)); WRITE_REG(*pReg, Registers); } @@ -4516,7 +4515,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); @@ -4538,7 +4537,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); @@ -4547,15 +4546,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIM /** * @brief Set the event filter for a given timer. * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n - * @rmtoll EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter + * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n + * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter * @note This function must not be called when the timer counter is enabled. * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: @@ -4606,15 +4605,15 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual event filter settings for a given timer. * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n - * @rmtoll EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter + * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n + * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4663,15 +4662,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint /** * @brief Enable or disable event latch mechanism for a given timer. * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n - * @rmtoll EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus + * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n + * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus * @note This function must not be called when the timer counter is enabled. * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: @@ -4709,15 +4708,15 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin /** * @brief Get actual event latch status for a given timer. * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n - * @rmtoll EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus + * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n + * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4760,8 +4759,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, /** * @brief Configure the dead time insertion feature for a given timer. * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n - * @rmtoll DTxR SDTF LL_HRTIM_DT_Config\n - * @rmtoll DTxR SDRT LL_HRTIM_DT_Config + * DTxR SDTF LL_HRTIM_DT_Config\n + * DTxR SDRT LL_HRTIM_DT_Config * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_A @@ -4777,7 +4776,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); @@ -4806,7 +4805,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u */ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); @@ -4834,7 +4833,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); @@ -4855,7 +4854,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); @@ -4875,7 +4874,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); @@ -4898,7 +4897,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); @@ -4920,7 +4919,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); @@ -4941,10 +4940,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); - MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << POSITION_VAL(HRTIM_DTR_DTF)); + MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } /** @@ -4961,10 +4960,10 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); - return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> POSITION_VAL(HRTIM_DTR_DTF)); + return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } /** @@ -4984,7 +4983,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); @@ -5006,7 +5005,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); @@ -5026,7 +5025,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); @@ -5046,7 +5045,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); @@ -5066,7 +5065,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); @@ -5086,7 +5085,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); @@ -5103,8 +5102,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Configure the chopper stage for a given timer. * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n - * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_Config\n - * @rmtoll CHPxR STRTPW LL_HRTIM_CHP_Config + * CHPxR CARDTY LL_HRTIM_CHP_Config\n + * CHPxR STRTPW LL_HRTIM_CHP_Config * @note This function must not be called if the chopper mode is already * enabled for one of the timer outputs. * @param HRTIMx High Resolution Timer instance @@ -5122,7 +5121,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); @@ -5162,7 +5161,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, */ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); @@ -5198,7 +5197,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); @@ -5230,7 +5229,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); @@ -5258,7 +5257,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); @@ -5297,7 +5296,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); @@ -5333,7 +5332,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_TACEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); @@ -5350,69 +5349,69 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Set the timer output set source. * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n - * @rmtoll SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc + * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n + * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5471,69 +5470,69 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Get the timer output set source. * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n - * @rmtoll SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc + * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n + * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5591,69 +5590,69 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin /** * @brief Set the timer output reset source. * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n - * @rmtoll RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc + * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n + * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5712,69 +5711,69 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Get the timer output set source. * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n - * @rmtoll RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc + * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n + * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5832,17 +5831,17 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, u /** * @brief Configure a timer output. * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR POL2 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR IDLEM2 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR IDLES2 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR FAULT2 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR CHP2 LL_HRTIM_OUT_Config\n - * @rmtoll OUTxR DIDL2 LL_HRTIM_OUT_Config + * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n + * OUTxR IDLES1 LL_HRTIM_OUT_Config\n + * OUTxR FAULT1 LL_HRTIM_OUT_Config\n + * OUTxR CHP1 LL_HRTIM_OUT_Config\n + * OUTxR DIDL1 LL_HRTIM_OUT_Config\n + * OUTxR POL2 LL_HRTIM_OUT_Config\n + * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n + * OUTxR IDLES2 LL_HRTIM_OUT_Config\n + * OUTxR FAULT2 LL_HRTIM_OUT_Config\n + * OUTxR CHP2 LL_HRTIM_OUT_Config\n + * OUTxR DIDL2 LL_HRTIM_OUT_Config * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5876,7 +5875,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, /** * @brief Set the polarity of a timer output. * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n - * @rmtoll OUTxR POL2 LL_HRTIM_OUT_SetPolarity + * OUTxR POL2 LL_HRTIM_OUT_SetPolarity * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5905,7 +5904,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou /** * @brief Get actual polarity of the timer output. * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n - * @rmtoll OUTxR POL2 LL_HRTIM_OUT_GetPolarity + * OUTxR POL2 LL_HRTIM_OUT_GetPolarity * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5933,7 +5932,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the output IDLE mode. * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n - * @rmtoll OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode + * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode * @note This function must not be called when the burst mode is active * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: @@ -5963,7 +5962,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou /** * @brief Get actual output IDLE mode. * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n - * @rmtoll OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode + * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -5991,7 +5990,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the output IDLE level. * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n - * @rmtoll OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel + * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel * @note This function must be called prior enabling the timer. * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE. * @param HRTIMx High Resolution Timer instance @@ -6022,7 +6021,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O /** * @brief Get actual output IDLE level. * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n - * @rmtoll OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel + * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6050,7 +6049,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Set the output FAULT state. * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n - * @rmtoll OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState + * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState * @note This function must not called when the timer is enabled and a fault * channel is enabled at timer level. * @param HRTIMx High Resolution Timer instance @@ -6083,7 +6082,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual FAULT state. * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n - * @rmtoll OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState + * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6113,7 +6112,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Set the output chopper mode. * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n - * @rmtoll OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode + * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode * @note This function must not called when the timer is enabled. * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: @@ -6143,7 +6142,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual output chopper mode * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n - * @rmtoll OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode + * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6171,7 +6170,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint /** * @brief Set the output burst mode entry mode. * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n - * @rmtoll OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode + * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode * @note This function must not called when the timer is enabled. * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: @@ -6201,7 +6200,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual output burst mode entry mode. * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n - * @rmtoll OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode + * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6230,7 +6229,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint * @brief Get the level (active or inactive) of the designated output when the * delayed protection was triggered. * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n - * @rmtoll TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus + * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6253,15 +6252,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> - POSITION_VAL(HRTIM_TIMISR_O1STAT)); + HRTIM_TIMISR_O1STAT_Pos); } /** * @brief Force the timer output to its active or inactive level. * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n - * @rmtoll RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n - * @rmtoll SETx2R SST LL_HRTIM_OUT_ForceLevel\n - * @rmtoll RSTx2R SRT LL_HRTIM_OUT_ForceLevel + * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n + * SETx2R SST LL_HRTIM_OUT_ForceLevel\n + * RSTx2R SRT LL_HRTIM_OUT_ForceLevel * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6290,7 +6289,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out /** * @brief Get actual output level, before the output stage (chopper, polarity). * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n - * @rmtoll TIMxISR O2CPY LL_HRTIM_OUT_GetLevel + * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel * @param HRTIMx High Resolution Timer instance * @param Output This parameter can be one of the following values: * @arg @ref LL_HRTIM_OUTPUT_TA1 @@ -6313,7 +6312,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> - POSITION_VAL(HRTIM_TIMISR_O1CPY)); + HRTIM_TIMISR_O1CPY_Pos); } /** @@ -6327,45 +6326,45 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O /** * @brief Configure external event conditioning. * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE1POL LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE2SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE2POL LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE2SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE2FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE3SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE3POL LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE3SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE3FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE4SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE4POL LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE4SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE4FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE5SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE5POL LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE5SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR1 EE5FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE6SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE6POL LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE6SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE6FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE7SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE7POL LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE7SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE7FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE8SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE8POL LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE8SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE8FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE9SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE9POL LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE9SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE9FAST LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE10SRC LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE10POL LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE10SNS LL_HRTIM_EE_Config\n - * @rmtoll EECR2 EE10FAST LL_HRTIM_EE_Config + * EECR1 EE1POL LL_HRTIM_EE_Config\n + * EECR1 EE1SNS LL_HRTIM_EE_Config\n + * EECR1 EE1FAST LL_HRTIM_EE_Config\n + * EECR1 EE2SRC LL_HRTIM_EE_Config\n + * EECR1 EE2POL LL_HRTIM_EE_Config\n + * EECR1 EE2SNS LL_HRTIM_EE_Config\n + * EECR1 EE2FAST LL_HRTIM_EE_Config\n + * EECR1 EE3SRC LL_HRTIM_EE_Config\n + * EECR1 EE3POL LL_HRTIM_EE_Config\n + * EECR1 EE3SNS LL_HRTIM_EE_Config\n + * EECR1 EE3FAST LL_HRTIM_EE_Config\n + * EECR1 EE4SRC LL_HRTIM_EE_Config\n + * EECR1 EE4POL LL_HRTIM_EE_Config\n + * EECR1 EE4SNS LL_HRTIM_EE_Config\n + * EECR1 EE4FAST LL_HRTIM_EE_Config\n + * EECR1 EE5SRC LL_HRTIM_EE_Config\n + * EECR1 EE5POL LL_HRTIM_EE_Config\n + * EECR1 EE5SNS LL_HRTIM_EE_Config\n + * EECR1 EE5FAST LL_HRTIM_EE_Config\n + * EECR2 EE6SRC LL_HRTIM_EE_Config\n + * EECR2 EE6POL LL_HRTIM_EE_Config\n + * EECR2 EE6SNS LL_HRTIM_EE_Config\n + * EECR2 EE6FAST LL_HRTIM_EE_Config\n + * EECR2 EE7SRC LL_HRTIM_EE_Config\n + * EECR2 EE7POL LL_HRTIM_EE_Config\n + * EECR2 EE7SNS LL_HRTIM_EE_Config\n + * EECR2 EE7FAST LL_HRTIM_EE_Config\n + * EECR2 EE8SRC LL_HRTIM_EE_Config\n + * EECR2 EE8POL LL_HRTIM_EE_Config\n + * EECR2 EE8SNS LL_HRTIM_EE_Config\n + * EECR2 EE8FAST LL_HRTIM_EE_Config\n + * EECR2 EE9SRC LL_HRTIM_EE_Config\n + * EECR2 EE9POL LL_HRTIM_EE_Config\n + * EECR2 EE9SNS LL_HRTIM_EE_Config\n + * EECR2 EE9FAST LL_HRTIM_EE_Config\n + * EECR2 EE10SRC LL_HRTIM_EE_Config\n + * EECR2 EE10POL LL_HRTIM_EE_Config\n + * EECR2 EE10SNS LL_HRTIM_EE_Config\n + * EECR2 EE10FAST LL_HRTIM_EE_Config * @note This function must not be called when the timer counter is enabled. * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel. * @note Fast mode is available only for LL_HRTIM_EVENT_1..5. @@ -6400,15 +6399,15 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u /** * @brief Set the external event source. * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n - * @rmtoll EECR2 EE10SRC LL_HRTIM_EE_SetSrc + * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n + * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n + * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n + * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n + * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n + * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n + * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n + * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n + * EECR2 EE10SRC LL_HRTIM_EE_SetSrc * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6439,15 +6438,15 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u /** * @brief Get actual external event source. * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n - * @rmtoll EECR2 EE10SRC LL_HRTIM_EE_GetSrc + * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n + * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n + * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n + * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n + * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n + * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n + * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n + * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n + * EECR2 EE10SRC LL_HRTIM_EE_GetSrc * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6477,15 +6476,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Even /** * @brief Set the polarity of an external event. * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n - * @rmtoll EECR2 EE10POL LL_HRTIM_EE_SetPolarity + * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n + * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n + * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n + * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n + * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n + * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n + * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n + * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n + * EECR2 EE10POL LL_HRTIM_EE_SetPolarity * @note This function must not be called when the timer counter is enabled. * @note Event polarity is only significant when event detection is level-sensitive. * @param HRTIMx High Resolution Timer instance @@ -6516,15 +6515,15 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve /** * @brief Get actual polarity setting of an external event. * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n - * @rmtoll EECR2 EE10POL LL_HRTIM_EE_GetPolarity + * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n + * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n + * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n + * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n + * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n + * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n + * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n + * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n + * EECR2 EE10POL LL_HRTIM_EE_GetPolarity * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6552,15 +6551,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Set the sensitivity of an external event. * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n - * @rmtoll EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity + * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n + * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n + * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n + * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n + * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n + * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n + * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n + * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n + * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6592,15 +6591,15 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Get actual sensitivity setting of an external event. * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n - * @rmtoll EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity + * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n + * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n + * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n + * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n + * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n + * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n + * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n + * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n + * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6630,15 +6629,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Set the fast mode of an external event. * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n - * @rmtoll EECR2 EE10FAST LL_HRTIM_EE_SetFastMode + * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n + * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n + * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n + * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n + * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n + * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n + * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n + * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n + * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode * @note This function must not be called when the timer counter is enabled. * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: @@ -6663,15 +6662,15 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve /** * @brief Get actual fast mode setting of an external event. * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n - * @rmtoll EECR2 EE10FAST LL_HRTIM_EE_GetFastMode + * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n + * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n + * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n + * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n + * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n + * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n + * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n + * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n + * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 @@ -6694,10 +6693,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Set the digital noise filter of a external event. * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n - * @rmtoll EECR3 EE7F LL_HRTIM_EE_SetFilter\n - * @rmtoll EECR3 EE8F LL_HRTIM_EE_SetFilter\n - * @rmtoll EECR3 EE9F LL_HRTIM_EE_SetFilter\n - * @rmtoll EECR3 EE10F LL_HRTIM_EE_SetFilter + * EECR3 EE7F LL_HRTIM_EE_SetFilter\n + * EECR3 EE8F LL_HRTIM_EE_SetFilter\n + * EECR3 EE9F LL_HRTIM_EE_SetFilter\n + * EECR3 EE10F LL_HRTIM_EE_SetFilter * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_6 @@ -6734,10 +6733,10 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event /** * @brief Get actual digital noise filter setting of a external event. * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n - * @rmtoll EECR3 EE7F LL_HRTIM_EE_GetFilter\n - * @rmtoll EECR3 EE8F LL_HRTIM_EE_GetFilter\n - * @rmtoll EECR3 EE9F LL_HRTIM_EE_GetFilter\n - * @rmtoll EECR3 EE10F LL_HRTIM_EE_GetFilter + * EECR3 EE7F LL_HRTIM_EE_GetFilter\n + * EECR3 EE8F LL_HRTIM_EE_GetFilter\n + * EECR3 EE9F LL_HRTIM_EE_GetFilter\n + * EECR3 EE10F LL_HRTIM_EE_GetFilter * @param HRTIMx High Resolution Timer instance * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_6 @@ -6814,15 +6813,15 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) /** * @brief Configure fault signal conditioning. * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT2P LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT3P LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT4P LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR2 FLT5P LL_HRTIM_FLT_Config\n - * @rmtoll FLTINR2 FLT5SRC LL_HRTIM_FLT_Config + * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n + * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n + * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n + * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n + * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n + * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n + * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n + * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n + * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config * @note This function must not be called when the fault channel is enabled. * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: @@ -6848,10 +6847,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, /** * @brief Set the source of a fault signal. * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n - * @rmtoll FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n - * @rmtoll FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n - * @rmtoll FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n - * @rmtoll FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc + * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n + * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n + * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n + * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc * @note This function must not be called when the fault channel is enabled. * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: @@ -6876,10 +6875,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, /** * @brief Get actual source of a fault signal. * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n - * @rmtoll FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n - * @rmtoll FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n - * @rmtoll FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n - * @rmtoll FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc + * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n + * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n + * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n + * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -6902,10 +6901,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fau /** * @brief Set the polarity of a fault signal. * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n - * @rmtoll FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n - * @rmtoll FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n - * @rmtoll FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n - * @rmtoll FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity + * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n + * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n + * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n + * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity * @note This function must not be called when the fault channel is enabled. * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: @@ -6930,10 +6929,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa /** * @brief Get actual polarity of a fault signal. * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n - * @rmtoll FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n - * @rmtoll FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n - * @rmtoll FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n - * @rmtoll FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity + * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n + * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n + * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n + * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -6956,10 +6955,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Set the digital noise filter of a fault signal. * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n - * @rmtoll FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n - * @rmtoll FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n - * @rmtoll FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n - * @rmtoll FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter + * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n + * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n + * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n + * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter * @note This function must not be called when the fault channel is enabled. * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: @@ -6998,10 +6997,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul /** * @brief Get actual digital noise filter setting of a fault signal. * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n - * @rmtoll FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n - * @rmtoll FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n - * @rmtoll FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n - * @rmtoll FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter + * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n + * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n + * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n + * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7070,10 +7069,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) /** * @brief Lock the fault signal conditioning settings. * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n - * @rmtoll FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n - * @rmtoll FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n - * @rmtoll FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n - * @rmtoll FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock + * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n + * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n + * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n + * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7094,10 +7093,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) /** * @brief Enable the fault circuitry for the designated fault input. * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n - * @rmtoll FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n - * @rmtoll FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n - * @rmtoll FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n - * @rmtoll FLTINR2 FLT5E LL_HRTIM_FLT_Enable + * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n + * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n + * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n + * FLTINR2 FLT5E LL_HRTIM_FLT_Enable * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7118,10 +7117,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) /** * @brief Disable the fault circuitry for for the designated fault input. * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n - * @rmtoll FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n - * @rmtoll FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n - * @rmtoll FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n - * @rmtoll FLTINR2 FLT5E LL_HRTIM_FLT_Disable + * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n + * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n + * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n + * FLTINR2 FLT5E LL_HRTIM_FLT_Disable * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7142,10 +7141,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) /** * @brief Indicate whether the fault circuitry is enabled for a given fault input. * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n - * @rmtoll FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n - * @rmtoll FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n - * @rmtoll FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n - * @rmtoll FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled + * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n + * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n + * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n + * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled * @param HRTIMx High Resolution Timer instance * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7175,8 +7174,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Configure the burst mode controller. * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n - * @rmtoll BMCR BMCLK LL_HRTIM_BM_Config\n - * @rmtoll BMCR BMPRSC LL_HRTIM_BM_Config + * BMCR BMCLK LL_HRTIM_BM_Config\n + * BMCR BMPRSC LL_HRTIM_BM_Config * @param HRTIMx High Resolution Timer instance * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS @@ -7350,37 +7349,37 @@ __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) /** * @brief Set the burst mode controller trigger * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TARST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TAREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TBRST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TBREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TCRST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TCREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TDRST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TDREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TERST LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TEREP LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n - * @rmtoll BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig + * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n + * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n + * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n + * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n + * BMTRGR TARST LL_HRTIM_BM_SetTrig\n + * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n + * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n + * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n + * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n + * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n + * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n + * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n + * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR TERST LL_HRTIM_BM_SetTrig\n + * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n + * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n + * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n + * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n + * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n + * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n + * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n + * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig * @param HRTIMx High Resolution Timer instance * @param Trig This parameter can be a combination of the following values: * @arg @ref LL_HRTIM_BM_TRIG_NONE @@ -7425,37 +7424,37 @@ __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig) /** * @brief Get actual burst mode controller trigger. * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TARST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TAREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TBRST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TBREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TCRST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TCREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TDRST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TDREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TERST LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TEREP LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n - * @rmtoll BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig + * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n + * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n + * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n + * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n + * BMTRGR TARST LL_HRTIM_BM_GetTrig\n + * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n + * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n + * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n + * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n + * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n + * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n + * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n + * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR TERST LL_HRTIM_BM_GetTrig\n + * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n + * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n + * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n + * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n + * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n + * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n + * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n + * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig * @param HRTIMx High Resolution Timer instance * @retval Trig This parameter can be a combination of the following values: * @arg @ref LL_HRTIM_BM_TRIG_NONE @@ -7828,7 +7827,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) /** * @brief Clear the update interrupt flag for a given timer (including the master timer) . * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n - * @rmtoll TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE + * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7841,7 +7840,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); @@ -7850,7 +7849,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n - * @rmtoll TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE + * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7863,7 +7862,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)); @@ -7872,7 +7871,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin /** * @brief Clear the repetition interrupt flag for a given timer (including the master timer) . * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n - * @rmtoll TIMxICR REPC LL_HRTIM_ClearFlag_REP + * TIMxICR REPC LL_HRTIM_ClearFlag_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7885,7 +7884,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); @@ -7895,7 +7894,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n - * @rmtoll TIMxISR REP LL_HRTIM_IsActiveFlag_REP + * TIMxISR REP LL_HRTIM_IsActiveFlag_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7908,7 +7907,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)); @@ -7917,7 +7916,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Clear the compare 1 match interrupt for a given timer (including the master timer). * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n - * @rmtoll TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1 + * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7930,7 +7929,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); @@ -7939,7 +7938,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n - * @rmtoll TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1 + * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7952,7 +7951,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)); @@ -7961,7 +7960,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Clear the compare 2 match interrupt for a given timer (including the master timer). * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n - * @rmtoll TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2 + * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7974,7 +7973,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); @@ -7983,7 +7982,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n - * @rmtoll TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2 + * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -7996,7 +7995,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)); @@ -8005,7 +8004,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Clear the compare 3 match interrupt for a given timer (including the master timer). * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n - * @rmtoll TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3 + * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8018,7 +8017,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); @@ -8027,7 +8026,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n - * @rmtoll TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3 + * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8040,7 +8039,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)); @@ -8049,7 +8048,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 /** * @brief Clear the compare 4 match interrupt for a given timer (including the master timer). * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n - * @rmtoll TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4 + * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8062,7 +8061,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); @@ -8071,7 +8070,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) . * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n - * @rmtoll TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4 + * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8084,7 +8083,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)); @@ -8104,7 +8103,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); @@ -8124,7 +8123,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)); @@ -8144,7 +8143,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); @@ -8164,7 +8163,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)); @@ -8184,7 +8183,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); @@ -8204,7 +8203,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)); @@ -8224,7 +8223,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); @@ -8244,7 +8243,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)); @@ -8264,7 +8263,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); @@ -8284,7 +8283,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)); @@ -8304,7 +8303,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); @@ -8324,7 +8323,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)); @@ -8344,7 +8343,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); @@ -8364,7 +8363,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)); @@ -8384,7 +8383,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C); @@ -8404,7 +8403,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)); @@ -8718,7 +8717,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) /** * @brief Enable the update interrupt for a given timer. * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n - * @rmtoll TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE + * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8731,7 +8730,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); @@ -8740,7 +8739,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti /** * @brief Disable the update interrupt for a given timer. * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n - * @rmtoll TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE + * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8753,7 +8752,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); @@ -8762,7 +8761,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Indicate whether the update interrupt is enabled for a given timer. * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n - * @rmtoll TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE + * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8775,7 +8774,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)); @@ -8784,7 +8783,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint /** * @brief Enable the repetition interrupt for a given timer. * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n - * @rmtoll TIMxDIER REPIE LL_HRTIM_EnableIT_REP + * TIMxDIER REPIE LL_HRTIM_EnableIT_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8797,7 +8796,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); @@ -8806,7 +8805,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer /** * @brief Disable the repetition interrupt for a given timer. * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n - * @rmtoll TIMxDIER REPIE LL_HRTIM_DisableIT_REP + * TIMxDIER REPIE LL_HRTIM_DisableIT_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8819,7 +8818,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); @@ -8828,7 +8827,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Indicate whether the repetition interrupt is enabled for a given timer. * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n - * @rmtoll TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP + * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8841,7 +8840,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)); @@ -8850,7 +8849,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Enable the compare 1 interrupt for a given timer. * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n - * @rmtoll TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1 + * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8863,7 +8862,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); @@ -8872,7 +8871,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Disable the compare 1 interrupt for a given timer. * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n - * @rmtoll TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1 + * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8885,7 +8884,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); @@ -8894,7 +8893,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare 1 interrupt is enabled for a given timer. * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n - * @rmtoll TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1 + * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8907,7 +8906,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)); @@ -8916,7 +8915,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Enable the compare 2 interrupt for a given timer. * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n - * @rmtoll TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2 + * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8929,7 +8928,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); @@ -8938,7 +8937,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Disable the compare 2 interrupt for a given timer. * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n - * @rmtoll TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2 + * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8951,7 +8950,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); @@ -8960,7 +8959,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare 2 interrupt is enabled for a given timer. * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n - * @rmtoll TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2 + * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8973,7 +8972,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)); @@ -8982,7 +8981,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Enable the compare 3 interrupt for a given timer. * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n - * @rmtoll TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3 + * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -8995,7 +8994,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); @@ -9004,7 +9003,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Disable the compare 3 interrupt for a given timer. * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n - * @rmtoll TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3 + * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9017,7 +9016,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); @@ -9026,7 +9025,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare 3 interrupt is enabled for a given timer. * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n - * @rmtoll TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3 + * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9039,7 +9038,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)); @@ -9048,7 +9047,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Enable the compare 4 interrupt for a given timer. * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n - * @rmtoll TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4 + * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9061,7 +9060,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); @@ -9070,7 +9069,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time /** * @brief Disable the compare 4 interrupt for a given timer. * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n - * @rmtoll TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4 + * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9083,7 +9082,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); @@ -9092,7 +9091,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim /** * @brief Indicate whether the compare 4 interrupt is enabled for a given timer. * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n - * @rmtoll TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4 + * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9105,7 +9104,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)); @@ -9125,7 +9124,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); @@ -9145,7 +9144,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); @@ -9165,7 +9164,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)); @@ -9185,7 +9184,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); @@ -9205,7 +9204,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); @@ -9225,7 +9224,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)); @@ -9245,7 +9244,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); @@ -9265,7 +9264,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); @@ -9285,7 +9284,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)); @@ -9305,7 +9304,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); @@ -9325,7 +9324,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); @@ -9345,7 +9344,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)); @@ -9365,7 +9364,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); @@ -9385,7 +9384,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); @@ -9405,7 +9404,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)); @@ -9425,7 +9424,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); @@ -9445,7 +9444,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); @@ -9465,7 +9464,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)); @@ -9485,7 +9484,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); @@ -9505,7 +9504,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); @@ -9525,7 +9524,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)); @@ -9545,7 +9544,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); @@ -9565,7 +9564,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); @@ -9585,7 +9584,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)); @@ -9635,7 +9634,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) /** * @brief Enable the update DMA request for a given timer. * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n - * @rmtoll TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE + * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9648,7 +9647,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); @@ -9657,7 +9656,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ /** * @brief Disable the update DMA request for a given timer. * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n - * @rmtoll TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE + * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9670,7 +9669,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); @@ -9679,7 +9678,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 /** * @brief Indicate whether the update DMA request is enabled for a given timer. * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n - * @rmtoll TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE + * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9692,7 +9691,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)); @@ -9701,7 +9700,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, /** * @brief Enable the repetition DMA request for a given timer. * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n - * @rmtoll TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP + * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9714,7 +9713,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); @@ -9723,7 +9722,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T /** * @brief Disable the repetition DMA request for a given timer. * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n - * @rmtoll TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP + * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9736,7 +9735,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); @@ -9745,7 +9744,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the repetition DMA request is enabled for a given timer. * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n - * @rmtoll TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP + * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9758,7 +9757,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)); @@ -9767,7 +9766,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uin /** * @brief Enable the compare 1 DMA request for a given timer. * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n - * @rmtoll TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1 + * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9780,7 +9779,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); @@ -9789,7 +9788,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the compare 1 DMA request for a given timer. * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n - * @rmtoll TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1 + * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9802,7 +9801,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); @@ -9811,7 +9810,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the compare 1 DMA request is enabled for a given timer. * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n - * @rmtoll TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1 + * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9824,7 +9823,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)); @@ -9833,7 +9832,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, ui /** * @brief Enable the compare 2 DMA request for a given timer. * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n - * @rmtoll TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2 + * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9846,7 +9845,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); @@ -9855,7 +9854,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the compare 2 DMA request for a given timer. * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n - * @rmtoll TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2 + * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9868,7 +9867,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); @@ -9877,7 +9876,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the compare 2 DMA request is enabled for a given timer. * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n - * @rmtoll TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2 + * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9890,7 +9889,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)); @@ -9899,7 +9898,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, ui /** * @brief Enable the compare 3 DMA request for a given timer. * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n - * @rmtoll TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3 + * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9912,7 +9911,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); @@ -9921,7 +9920,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the compare 3 DMA request for a given timer. * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n - * @rmtoll TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3 + * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9934,7 +9933,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); @@ -9943,7 +9942,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the compare 3 DMA request is enabled for a given timer. * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n - * @rmtoll TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3 + * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9956,7 +9955,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)); @@ -9965,7 +9964,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, ui /** * @brief Enable the compare 4 DMA request for a given timer. * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n - * @rmtoll TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4 + * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -9978,7 +9977,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); @@ -9987,7 +9986,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Disable the compare 4 DMA request for a given timer. * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n - * @rmtoll TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4 + * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -10000,7 +9999,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); @@ -10009,7 +10008,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t /** * @brief Indicate whether the compare 4 DMA request is enabled for a given timer. * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n - * @rmtoll TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4 + * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4 * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER @@ -10022,7 +10021,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)); @@ -10042,7 +10041,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); @@ -10062,7 +10061,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); @@ -10082,7 +10081,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)); @@ -10102,7 +10101,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); @@ -10122,7 +10121,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); @@ -10142,7 +10141,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)); @@ -10162,7 +10161,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); @@ -10182,7 +10181,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); @@ -10202,7 +10201,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)); @@ -10222,7 +10221,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); @@ -10242,7 +10241,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); @@ -10262,7 +10261,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)); @@ -10282,7 +10281,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); @@ -10302,7 +10301,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); @@ -10322,7 +10321,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)); @@ -10342,7 +10341,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); @@ -10362,7 +10361,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); @@ -10382,7 +10381,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)); @@ -10402,7 +10401,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); @@ -10422,7 +10421,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); @@ -10442,7 +10441,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)); @@ -10462,7 +10461,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); @@ -10482,7 +10481,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); @@ -10502,7 +10501,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(HRTIM_MCR_MCEN)); + register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)); diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_i2c.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_i2c.h index dd718dc532edcff3dcd60c67e2975f04286a0747..676732b5c62987a9a1e5e5d9d15a530e3b690b53 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_i2c.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_i2c.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of I2C LL module. ****************************************************************************** * @attention @@ -63,16 +63,6 @@ extern "C" { /** @defgroup I2C_LL_Private_Constants I2C Private Constants * @{ */ -/* Defines used for the bit position in the register and perform offsets */ -#define I2C_POSITION_CR1_DNF (uint32_t)POSITION_VAL(I2C_CR1_DNF) -#define I2C_POSITION_CR2_NBYTES (uint32_t)POSITION_VAL(I2C_CR2_NBYTES) -#define I2C_POSITION_TIMINGR_PRESC (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC) -#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL) -#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL) -#define I2C_POSITION_TIMINGR_SCLH (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH) -#define I2C_POSITION_TIMINGR_SCLL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL) -#define I2C_POSITION_ISR_ADDCODE (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE) -#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB) /** * @} */ @@ -388,11 +378,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -463,7 +453,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF)); + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); } /** @@ -479,7 +469,7 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt */ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) { - MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF); + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); } /** @@ -490,7 +480,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital */ __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF); + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } /** @@ -920,7 +910,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) */ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } /** @@ -931,7 +921,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } /** @@ -942,7 +932,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } /** @@ -953,7 +943,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } /** @@ -964,7 +954,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL); + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } /** @@ -1112,7 +1102,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo uint32_t TimeoutB) { MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, - TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB)); + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); } /** @@ -1187,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) { - WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB); + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1200,7 +1190,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB); + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } /** @@ -1936,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) */ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES); + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); } /** @@ -1947,7 +1937,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer */ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES); + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } /** @@ -2120,7 +2110,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr { MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request); + SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } /** @@ -2146,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) { - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1); + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_iwdg.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_iwdg.h index 176eee7fb2abc3d0754e1797cf9b082349ce518c..c3832199df6541cf97749e4330a3e4b051448afc 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_iwdg.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_iwdg.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_opamp.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_opamp.h index f6645b01965f1878f618380bb06a24ffbd50e101..74978715d7a365d933995347e0f81b7896956dfd 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_opamp.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_opamp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_opamp.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of OPAMP LL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_pwr.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_pwr.h index a60aaf2fd2bc83e931bc14622804bdc154dc428c..07acabc6dc0ba16df1dbe42263fc10bbba653ac0 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_pwr.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_pwr.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -58,11 +58,8 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ - /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants @@ -85,15 +82,15 @@ extern "C" { */ #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ -#endif -#if defined (PWR_CSR_VREFINTRDYF) +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ -#endif +#endif /* PWR_CSR_VREFINTRDYF */ #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ #endif /* PWR_CSR_EWUP3 */ /** @@ -104,9 +101,9 @@ extern "C" { /** @defgroup PWR_LL_EC_MODE_PWR Mode Power * @{ */ -#define LL_PWR_MODE_STOP_MAINREGU ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ /** * @} */ @@ -115,14 +112,14 @@ extern "C" { /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode * @{ */ -#define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ /** - * @} - */ + * @} + */ #endif /* PWR_CR_LPDS */ -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level * @{ */ @@ -137,14 +134,13 @@ extern "C" { /** * @} */ -#endif - +#endif /* PWR_PVD_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins -* @{ -*/ + * @{ + */ #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ -#if defined (PWR_CSR_EWUP3) +#if defined(PWR_CSR_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ #endif /* PWR_CSR_EWUP3 */ /** @@ -155,13 +151,13 @@ extern "C" { * @{ */ #if defined(SDADC1) -#define LL_PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN) /*!< Enable SDADC1 */ +#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */ #endif /* SDADC1 */ #if defined(SDADC2) -#define LL_PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN) /*!< Enable SDADC2 */ +#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */ #endif /* SDADC2 */ #if defined(SDADC3) -#define LL_PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN) /*!< Enable SDADC3 */ +#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */ #endif /* SDADC3 */ /** * @} @@ -202,7 +198,6 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions * @{ @@ -211,7 +206,6 @@ extern "C" { /** @defgroup PWR_LL_EF_Configuration Configuration * @{ */ - /** * @brief Enables the SDADC peripheral functionality * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n @@ -260,7 +254,6 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx) return (READ_BIT(PWR->CR, Analogx) == (Analogx)); } - /** * @brief Enable access to the backup domain * @rmtoll CR DBP LL_PWR_EnableBkUpAccess @@ -321,7 +314,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) /** * @brief Set power down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_SetPowerMode\n - * CR LPDS LL_PWR_SetPowerMode + * @rmtoll CR LPDS LL_PWR_SetPowerMode * @param PDMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -335,8 +328,8 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) /** * @brief Get power down mode when CPU enters deepsleep - * @rmtoll CR PDDS LL_PWR_GetPowerMode - * CR LPDS LL_PWR_SetPowerMode + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU @@ -347,7 +340,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector * @rmtoll CR PLS LL_PWR_SetPVDLevel @@ -414,13 +407,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); } -#endif +#endif /* PWR_PVD_SUPPORT */ /** * @brief Enable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n - * CSR EWUP2 LL_PWR_EnableWakeUpPin\n - * CSR EWUP3 LL_PWR_EnableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -437,8 +430,8 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) /** * @brief Disable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n - * CSR EWUP2 LL_PWR_DisableWakeUpPin\n - * CSR EWUP3 LL_PWR_DisableWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -455,8 +448,8 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) /** * @brief Check if the WakeUp PINx functionality is enabled * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 @@ -470,6 +463,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); } + /** * @} */ @@ -498,7 +492,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); } -#if defined (PWR_PVD_SUPPORT) +#if defined(PWR_PVD_SUPPORT) /** * @brief Indicate whether VDD voltage is below the selected PVD threshold * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO @@ -508,9 +502,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); } -#endif +#endif /* PWR_PVD_SUPPORT */ -#if defined (PWR_CSR_VREFINTRDYF) +#if defined(PWR_CSR_VREFINTRDYF) /** * @brief Get Internal Reference VrefInt Flag * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY @@ -520,10 +514,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) { return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); } -#endif - - - +#endif /* PWR_CSR_VREFINTRDYF */ /** * @brief Clear Standby Flag * @rmtoll CR CSBF LL_PWR_ClearFlag_SB @@ -543,8 +534,6 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) { SET_BIT(PWR->CR, PWR_CR_CWUF); } - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function * @{ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rcc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rcc.h index 23cbd024412c09da581392174d9eb5d2056eb3d0..e3463520dbbe2fc0aa74c924b47e21947a6838b5 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rcc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_rcc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -580,32 +580,32 @@ typedef struct #endif /* RCC_CFGR_ADCPRE */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection * @{ */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDADCPRE_DIV1 /*!< SDADC CLK not divided */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDADCPRE_DIV2 /*!< SDADC CLK divided by 2 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDADCPRE_DIV4 /*!< SDADC CLK divided by 4 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDADCPRE_DIV6 /*!< SDADC CLK divided by 6 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDADCPRE_DIV8 /*!< SDADC CLK divided by 8 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDADCPRE_DIV10 /*!< SDADC CLK divided by 10 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDADCPRE_DIV12 /*!< SDADC CLK divided by 12 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDADCPRE_DIV14 /*!< SDADC CLK divided by 14 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDADCPRE_DIV16 /*!< SDADC CLK divided by 16 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDADCPRE_DIV20 /*!< SDADC CLK divided by 20 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDADCPRE_DIV24 /*!< SDADC CLK divided by 24 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDADCPRE_DIV28 /*!< SDADC CLK divided by 28 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDADCPRE_DIV32 /*!< SDADC CLK divided by 32 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDADCPRE_DIV36 /*!< SDADC CLK divided by 36 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDADCPRE_DIV40 /*!< SDADC CLK divided by 40 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDADCPRE_DIV44 /*!< SDADC CLK divided by 44 */ -#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDADCPRE_DIV48 /*!< SDADC CLK divided by 48 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */ /** * @} */ -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source * @{ @@ -752,16 +752,16 @@ typedef struct #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source * @{ */ -#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDADCPRE /*!< SDADC Clock source selection */ +#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */ /** * @} */ -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection @@ -1741,10 +1741,10 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) } #endif /* RCC_CFGR_ADCPRE */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) /** * @brief Configure SDADCx clock source - * @rmtoll CFGR SDADCPRE LL_RCC_SetSDADCClockSource + * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource * @param SDADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 @@ -1767,9 +1767,9 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) */ __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource) { - MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, SDADCxSource); + MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource); } -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ /** * @brief Get USARTx clock source @@ -2059,10 +2059,10 @@ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) } #endif /* RCC_CFGR_ADCPRE */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) /** * @brief Get SDADCx clock source - * @rmtoll CFGR SDADCPRE LL_RCC_GetSDADCClockSource + * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource * @param SDADCx This parameter can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSOURCE * @retval Returned value can be one of the following values: @@ -2088,7 +2088,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx) { return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx)); } -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ /** * @} @@ -2806,9 +2806,9 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)) uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource); -#endif /*RCC_CFGR_SDADCPRE */ +#endif /*RCC_CFGR_SDPRE */ #if defined(CEC) uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); #endif /* CEC */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rtc.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rtc.h index 07ef8673aeab6100a4d8cd5b141074fd4cb04328..6cae32436ee4ccbceb3a35c6c3bc857630fb7128 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rtc.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_rtc.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -63,8 +63,8 @@ extern "C" { * @{ */ /* Masks Definition */ -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU) +#define RTC_INIT_MASK (0xFFFFFFFFU) +#define RTC_RSF_MASK (0xFFFFFF5FU) /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h index 8f0e171ac6e0361b8155f278e59ae92fc0ea6c44..bdfc780cb1bb940a100afd06128a1ed0920481d1 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_spi.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SPI LL module. ****************************************************************************** * @attention @@ -165,7 +165,7 @@ typedef struct * @{ */ #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ -#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /*!< Slave configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ /** * @} */ @@ -173,7 +173,7 @@ typedef struct /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol * @{ */ -#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ /** * @} @@ -182,7 +182,7 @@ typedef struct /** @defgroup SPI_LL_EC_PHASE Clock Phase * @{ */ -#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ /** * @} @@ -191,7 +191,7 @@ typedef struct /** @defgroup SPI_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ /** * @} @@ -200,7 +200,7 @@ typedef struct /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler * @{ */ -#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ @@ -216,7 +216,7 @@ typedef struct * @{ */ #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ -#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /*!< Data is transmitted/received with the MSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ /** * @} */ @@ -224,7 +224,7 @@ typedef struct /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode * @{ */ -#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ @@ -236,7 +236,7 @@ typedef struct * @{ */ #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ -#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ /** * @} @@ -266,7 +266,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation * @{ */ -#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ /** * @} @@ -276,7 +276,7 @@ typedef struct /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length * @{ */ -#define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< 8-bit CRC length */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ /** * @} @@ -285,7 +285,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ /** * @} @@ -294,7 +294,7 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level * @{ */ -#define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ @@ -305,7 +305,7 @@ typedef struct /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level * @{ */ -#define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U) /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ @@ -316,8 +316,8 @@ typedef struct /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity * @{ */ -#define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Select DMA parity Even */ -#define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U) /*!< Select DMA parity Odd */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ /** * @} @@ -1511,7 +1511,7 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ @@ -1522,7 +1522,7 @@ typedef struct /** @defgroup I2S_LL_EC_POLARITY Clock Polarity * @{ */ -#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ /** * @} @@ -1531,7 +1531,7 @@ typedef struct /** @defgroup I2S_LL_EC_STANDARD I2s Standard * @{ */ -#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /*!< I2S standard philips */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ @@ -1543,7 +1543,7 @@ typedef struct /** @defgroup I2S_LL_EC_MODE Operation Mode * @{ */ -#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ @@ -1554,7 +1554,7 @@ typedef struct /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor * @{ */ -#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ /** * @} @@ -1565,7 +1565,7 @@ typedef struct /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output * @{ */ -#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ /** * @} @@ -1575,16 +1575,16 @@ typedef struct * @{ */ -#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /*!< Audio Frequency configuration 192000 Hz */ -#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /*!< Audio Frequency configuration 96000 Hz */ -#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /*!< Audio Frequency configuration 48000 Hz */ -#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /*!< Audio Frequency configuration 44100 Hz */ -#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /*!< Audio Frequency configuration 32000 Hz */ -#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /*!< Audio Frequency configuration 22050 Hz */ -#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /*!< Audio Frequency configuration 16000 Hz */ -#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /*!< Audio Frequency configuration 11025 Hz */ -#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /*!< Audio Frequency configuration 8000 Hz */ -#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /*!< Audio Freq not specified. Register I2SDIV = 2 */ +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_system.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_system.h index 7d26bba6a0ec18dcc1e44ecfdd60bd2666125f18..fef7a327ce3cdc8617fbd02f850372a9f2070015 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_system.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_system.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_system.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -205,8 +205,8 @@ extern "C" { #define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */ #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/ #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) -#define LL_SYSCFG_TIM18_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */ -#define LL_SYSCFG_TIM18_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */ +#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */ +#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */ #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/ /** * @} @@ -640,7 +640,7 @@ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap) * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*) - * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*) * * (*) value not defined in all devices. * @retval None @@ -847,6 +847,186 @@ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); +} + /** * @brief Configure source input for the EXTI external interrupt. * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_tim.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_tim.h index 31af9531cd6d4674cb6d8eec8b44a022704147c6..75d8b029542ed170d947180ed3a65b5d7992016f 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_tim.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_tim.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of TIM LL module. ****************************************************************************** * @attention @@ -136,8 +136,8 @@ static const uint8_t SHIFT_TAB_OISx[] = */ -#define TIMx_OR_RMP_SHIFT ((uint32_t)16U) -#define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU) +#define TIMx_OR_RMP_SHIFT (16U) +#define TIMx_OR_RMP_MASK (0x0000FFFFU) #if defined(TIM1) #define TIM1_OR_RMP_MASK ((uint32_t)(TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT)) #endif /* TIM1 */ @@ -248,7 +248,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. @@ -306,6 +306,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. @@ -429,6 +430,93 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + +#if defined(TIM_BDTR_BKF) + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + +#endif /* TIM_BDTR_BKF */ +#if defined(TIM_BDTR_BK2E) + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + +#endif /* TIM_BDTR_BK2E */ + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + /** * @} */ @@ -464,6 +552,37 @@ typedef struct * @} */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE ((uint32_t)0x00000000U) /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ +#if defined(TIM_BDTR_BK2E) + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ +#endif /* TIM_BDTR_BK2E */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /** @defgroup TIM_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. * @{ @@ -483,8 +602,8 @@ typedef struct /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source * @{ */ -#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ /** * @} */ @@ -492,8 +611,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ /** * @} */ @@ -501,11 +620,11 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /*!BDTR, TIM_BDTR_BKE); } -#if defined(TIM_BDTR_BKF) +#if defined(TIM_BDTR_BKF) /** * @brief Configure the break input. * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -3802,10 +3922,10 @@ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) * @{ */ /** - * @brief Set the OCREF clear source + * @brief Set the OCREF clear input source * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT * @note This function can only be used in Output compare and PWM modes. - * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource * @param TIMx Timer instance * @param OCRefClearInputSource This parameter can be one of the following values: * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR @@ -3819,8 +3939,8 @@ __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t /** * @} */ - #endif /* TIM_SMCR_OCCS */ + /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management * @{ */ @@ -4797,6 +4917,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ @@ -4821,5 +4943,4 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType #endif #endif /* __STM32F3xx_LL_TIM_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_usart.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_usart.h index 1ade56405fec6dd71b513980b9fe1d709375ab6d..e65f71467f4c78565b25e85007e18b3931a614b5 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_usart.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_usart.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of USART LL module. ****************************************************************************** * @attention @@ -63,14 +63,6 @@ extern "C" { /** @defgroup USART_LL_Private_Constants USART Private Constants * @{ */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define USART_POSITION_CR1_DEDT (uint32_t)POSITION_VAL(USART_CR1_DEDT) -#define USART_POSITION_CR1_DEAT (uint32_t)POSITION_VAL(USART_CR1_DEAT) -#define USART_POSITION_CR2_ADD (uint32_t)POSITION_VAL(USART_CR2_ADD) -#define USART_POSITION_CR3_SCARCNT (uint32_t)POSITION_VAL(USART_CR3_SCARCNT) -#define USART_POSITION_RTOR_BLEN (uint32_t)POSITION_VAL(USART_RTOR_BLEN) -#define USART_POSITION_GTPR_GT (uint32_t)POSITION_VAL(USART_GTPR_GT) /** * @} */ @@ -1358,7 +1350,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) { MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_POSITION_CR2_ADD))); + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); } /** @@ -1373,7 +1365,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_POSITION_CR2_ADD); + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } /** @@ -1680,7 +1672,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) { - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_POSITION_RTOR_BLEN); + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); } /** @@ -1691,7 +1683,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo */ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_POSITION_RTOR_BLEN); + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } /** @@ -1903,7 +1895,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) { - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_POSITION_CR3_SCARCNT); + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); } /** @@ -1916,7 +1908,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_POSITION_CR3_SCARCNT); + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } /** @@ -1960,7 +1952,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); } /** @@ -1974,7 +1966,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 */ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } /** @@ -2121,7 +2113,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_POSITION_CR1_DEDT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); } /** @@ -2134,7 +2126,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_POSITION_CR1_DEDT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } /** @@ -2148,7 +2140,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) { - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_POSITION_CR1_DEAT); + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); } /** @@ -2161,7 +2153,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) { - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_POSITION_CR1_DEAT); + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } /** diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_utils.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_utils.h index 81d3adb8951639930f174233fcbcda4db4938885..68bc7ec9540eb3f9f039b2537f03432334163a16 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_utils.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_utils.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_utils.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of UTILS LL module. @verbatim ============================================================================== @@ -75,7 +75,7 @@ extern "C" { */ /* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY (uint32_t)0xFFFFFFFFU +#define LL_MAX_DELAY 0xFFFFFFFFU /** * @brief Unique device ID register base address @@ -170,12 +170,13 @@ typedef struct /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation * @{ */ -#define LL_UTILS_HSEBYPASS_OFF (uint32_t)0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON (uint32_t)0x00000001U /*!< HSE Bypass is enabled */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ /** * @} */ + /** * @} */ @@ -229,6 +230,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); } + /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_wwdg.h b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_wwdg.h index f7a890fd21abff015ba870b66ef5261fc76d4f65..60ff793476305c1f22efe8f9d2ee6e903842f8da 100644 --- a/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_wwdg.h +++ b/stm32cube/stm32f3xx/drivers/include/stm32f3xx_ll_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_wwdg.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal.c index 9d1602595c1e3e2cd82059953f91b2009d1928ff..e433e04d5e9c3c3d985540655ef3d4ca3d412470 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -70,18 +70,18 @@ * @{ */ /** - * @brief STM32F3xx HAL Driver version number V1.3.0 + * @brief STM32F3xx HAL Driver version number V1.4.0 */ -#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F3xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F3xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\ - |(__STM32F3xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32F3xx_HAL_VERSION_SUB2 << 8 )\ +#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F3xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32F3xx_HAL_VERSION_RC)) -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define IDCODE_DEVID_MASK (0x00000FFFU) /** * @} */ @@ -154,7 +154,7 @@ __IO uint32_t uwTick; HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) +#if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ @@ -237,10 +237,10 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock / 1000); + HAL_SYSTICK_Config(SystemCoreClock / 1000U); /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); /* Return function status */ return HAL_OK; @@ -367,7 +367,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16); + return((DBGMCU->IDCODE) >> 16U); } /** diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc.c index 1da60acdb61fc52f55938add6d51de9323637dc8..2432f1bf1a720e4cb1fbc6f55f9f5e27c7ee4ea7 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc_ex.c index 0d094be2a713d309c79bc195c9b61d5a50abf58f..1bcb34fcf2ff63679c8b5bc9c6f25969ad7e7e8f 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -84,10 +84,10 @@ /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */ /* resolution 12 bits. */ /* Unit: ms */ - #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10) - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) - #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11) + #define ADC_CALIBRATION_TIMEOUT ( 10U) + #define ADC_ENABLE_TIMEOUT ( 2U) + #define ADC_DISABLE_TIMEOUT ( 2U) + #define ADC_STOP_CONVERSION_TIMEOUT ( 11U) /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to worst case, for 1 channel. */ @@ -95,17 +95,17 @@ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */ /* Unit: cycles of CPU clock. */ - #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928) + #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U) /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */ /* Unit: us */ - #define ADC_STAB_DELAY_US ((uint32_t) 10) + #define ADC_STAB_DELAY_US ( 10U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */ /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + #define ADC_TEMPSENSOR_DELAY_US ( 10U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ @@ -117,34 +117,34 @@ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ + /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) + #define ADC_ENABLE_TIMEOUT ( 2U) + #define ADC_DISABLE_TIMEOUT ( 2U) /* Delay for ADC calibration: */ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ - #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2) + #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U) /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ - /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ + /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ - #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10) + #define ADC_CALIBRATION_TIMEOUT ( 10U) /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ - #define ADC_STAB_DELAY_US ((uint32_t) 1) + #define ADC_STAB_DELAY_US ( 1U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + #define ADC_TEMPSENSOR_DELAY_US ( 10U) /* Maximum number of CPU cycles corresponding to 1 ADC cycle */ /* Value fixed to worst case: clock prescalers slowing down ADC clock to */ @@ -152,19 +152,19 @@ /* - AHB prescaler: 16 */ /* - ADC prescaler: 8 */ /* Unit: cycles of CPU clock. */ - #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128) + #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U) /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84) - #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U) + #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U) #endif /* STM32F373xC || STM32F378xx */ /** * @} @@ -254,8 +254,8 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; - uint32_t tmpCFGR = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tmpCFGR = 0U; + __IO uint32_t wait_loop_index = 0U; /* Check ADC handle */ if(hadc == NULL) @@ -304,8 +304,8 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) ADC_CLEAR_ERRORCODE(hadc); /* Initialize HAL ADC API internal variables */ - hadc->InjectionConfig.ChannelCount = 0; - hadc->InjectionConfig.ContextQueue = 0; + hadc->InjectionConfig.ChannelCount = 0U; + hadc->InjectionConfig.ContextQueue = 0U; /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; @@ -339,13 +339,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Set the intermediate state before moving the ADC voltage */ /* regulator to state enable. */ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); - /* Set ADVREGEN bits to 0x01 */ + /* Set ADVREGEN bits to 0x01U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); /* Delay for ADC stabilization time. */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -501,7 +501,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ @@ -512,7 +512,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1 , ADC_SQR1_L , - (hadc->Init.NbrOfConversion - (uint8_t)1) ); + (hadc->Init.NbrOfConversion - (uint8_t)1U) ); } else { @@ -573,9 +573,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_cr1 = 0; - uint32_t tmp_cr2 = 0; - uint32_t tmp_sqr1 = 0; + uint32_t tmp_cr1 = 0U; + uint32_t tmp_cr2 = 0U; + uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if(hadc == NULL) @@ -642,7 +642,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Configuration of ADC: */ /* - data alignment */ /* - external trigger to start conversion */ - /* - external trigger polarity (always set to 1, because needed for all */ + /* - external trigger polarity (always set to 1U, because needed for all */ /* triggers: external trigger of SW start) */ /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ @@ -702,7 +702,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ @@ -864,7 +864,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* 1. Set the intermediate state before moving the ADC voltage regulator */ /* to disable state. */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF); - /* 2. Set ADVREGEN bits to 0x10 */ + /* 2. Set ADVREGEN bits to 0x10U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1); /* Reset register CFGR */ @@ -1519,7 +1519,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti uint32_t tickstart; uint32_t tmp_Flag_EOC; ADC_Common_TypeDef *tmpADC_Common; - uint32_t tmp_cfgr = 0x0; + uint32_t tmp_cfgr = 0x0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1598,7 +1598,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1683,8 +1683,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti uint32_t tickstart; /* Variables for polling in case of scan mode enabled */ - uint32_t Conversion_Timeout_CPU_cycles_max = 0; - uint32_t Conversion_Timeout_CPU_cycles = 0; + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; + uint32_t Conversion_Timeout_CPU_cycles = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1709,10 +1709,10 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* - If single conversion for regular group (Scan mode disabled or enabled */ - /* with NbrOfConversion =1), flag EOC is used to determine the */ + /* with NbrOfConversion =1U), flag EOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for regular group (scan mode enabled and */ - /* NbrOfConversion >=2), flag EOC is set only at the end of the */ + /* NbrOfConversion >=2U), flag EOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ @@ -1729,7 +1729,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1757,7 +1757,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1834,7 +1834,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1853,7 +1853,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */ /* For example: */ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ @@ -1951,7 +1951,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -2819,10 +2819,10 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { - uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */ ADC_Common_TypeDef *tmpADC_Common; - uint32_t tmp_cfgr = 0x0; - uint32_t tmp_cfgr_jqm = 0x0; + uint32_t tmp_cfgr = 0x0U; + uint32_t tmp_cfgr_jqm = 0x0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3044,7 +3044,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - overrun_error = 1; + overrun_error = 1U; } else { @@ -3058,7 +3058,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) { - overrun_error = 1; + overrun_error = 1U; } } else @@ -3066,12 +3066,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) { - overrun_error = 1; + overrun_error = 1U; } } } - if (overrun_error == 1) + if (overrun_error == 1U) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); @@ -3332,7 +3332,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3356,7 +3356,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_BUSY_INTERNAL); /* Wait two ADC clock cycles */ - while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2) + while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U) { wait_loop_index++; } @@ -3873,7 +3873,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u { uint32_t tickstart; uint32_t tmp_Flag_EOC; - uint32_t tmp_cfgr = 0x00000000; + uint32_t tmp_cfgr = 0x00000000U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3910,7 +3910,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -3970,11 +3970,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled */ - uint32_t Conversion_Timeout_CPU_cycles_max =0; - uint32_t Conversion_Timeout_CPU_cycles =0; + uint32_t Conversion_Timeout_CPU_cycles_max =0U; + uint32_t Conversion_Timeout_CPU_cycles =0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -3987,10 +3987,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ - /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ + /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ - /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ + /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ @@ -4006,7 +4006,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -4034,7 +4034,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -4789,7 +4789,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { - uint32_t tmp_jdr = 0; + uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -4855,7 +4855,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { - uint32_t tmp_jdr = 0; + uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -5435,7 +5435,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -5447,7 +5447,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Verification of channel number: Channels 1 to 14 are available in */ - /* differential mode. Channels 15, 16, 17, 18 can be used only in */ + /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */ /* single-ended mode. */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { @@ -5470,28 +5470,28 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Regular sequence configuration */ - /* For Rank 1 to 4 */ - if (sConfig->Rank < 5) + /* For Rank 1 to 4U */ + if (sConfig->Rank < 5U) { MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } - /* For Rank 5 to 9 */ - else if (sConfig->Rank < 10) + /* For Rank 5 to 9U */ + else if (sConfig->Rank < 10U) { MODIFY_REG(hadc->Instance->SQR2, ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } - /* For Rank 10 to 14 */ - else if (sConfig->Rank < 15) + /* For Rank 10 to 14U */ + else if (sConfig->Rank < 15U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } - /* For Rank 15 to 16 */ + /* For Rank 15 to 16U */ else { MODIFY_REG(hadc->Instance->SQR4 , @@ -5508,14 +5508,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { /* Channel sampling time configuration */ - /* For channels 10 to 18 */ + /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } - else /* For channels 1 to 9 */ + else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) , @@ -5526,7 +5526,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */ + /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); @@ -5537,7 +5537,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf switch (sConfig->OffsetNumber) { case ADC_OFFSET_1: - /* Configure offset register 1 */ + /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , @@ -5547,7 +5547,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf break; case ADC_OFFSET_2: - /* Configure offset register 2 */ + /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , @@ -5557,7 +5557,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf break; case ADC_OFFSET_3: - /* Configure offset register 3 */ + /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , @@ -5567,7 +5567,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf break; case ADC_OFFSET_4: - /* Configure offset register 4 */ + /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , @@ -5625,18 +5625,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ - /* For channels 10 to 18 */ + /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2, - ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1) , - ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1) ); + ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) , + ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) ); } - else /* For channels 1 to 9 */ + else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, - ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1) , - ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1) ); + ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) , + ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) ); } } @@ -5681,8 +5681,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -5766,7 +5766,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -5779,21 +5779,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Regular sequence configuration */ - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7) + /* For Rank 1 to 6U */ + if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13) + /* For Rank 7 to 12U */ + else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2 , ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } - /* For Rank 13 to 16 */ + /* For Rank 13 to 16U */ else { MODIFY_REG(hadc->Instance->SQR1 , @@ -5803,14 +5803,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Channel sampling time configuration */ - /* For channels 10 to 18 */ + /* For channels 10 to 18U */ if (sConfig->Channel > ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } - else /* For channels 0 to 9 */ + else /* For channels 0 to 9U */ { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , @@ -5828,8 +5828,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -5901,11 +5901,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Injected context queue feature: temporary JSQR variables defined in */ /* static to be passed over calls of this function */ - uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0; + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -5926,7 +5926,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I } /* Verification of channel number: Channels 1 to 14 are available in */ - /* differential mode. Channels 15, 16, 17, 18 can be used only in */ + /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */ /* single-ended mode. */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { @@ -5946,10 +5946,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* */ /* - if scan mode is disabled: */ /* * Injected channels sequence length is set to 0x00: 1 channel */ - /* converted (channel on injected rank 1) */ + /* converted (channel on injected rank 1U) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* * Injected context register JSQR setting is simple: register is fully */ - /* defined on one call of this function (for injected rank 1) and can */ + /* defined on one call of this function (for injected rank 1U) and can */ /* be entered into queue directly. */ /* - if scan mode is enabled: */ /* * Injected channels sequence length is set to parameter */ @@ -5962,7 +5962,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1) ) + (sConfigInjected->InjectedNbrOfConversion == 1U) ) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -6023,13 +6023,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; /* Initialize value that will be set into register JSQR */ - hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000; + hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ @@ -6043,13 +6043,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) | + SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) | ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) | sConfigInjected->ExternalTrigInjecConvEdge ); } else { - SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) ); + SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) ); } } @@ -6067,7 +6067,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* 3. End of context setting: If last channel set, then write context */ /* into register JSQR and make it enter into queue */ - if (hadc->InjectionConfig.ChannelCount == 0) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Update ADC register JSQR */ MODIFY_REG(hadc->Instance->JSQR , @@ -6160,14 +6160,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Channel sampling time configuration */ - /* For channels 10 to 18 */ + /* For channels 10 to 18U */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) , ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } - else /* For channels 1 to 9 */ + else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) , @@ -6177,7 +6177,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ - /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */ + /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); @@ -6188,7 +6188,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I switch (sConfigInjected->InjectedOffsetNumber) { case ADC_OFFSET_1: - /* Configure offset register 1 */ + /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , @@ -6198,7 +6198,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I break; case ADC_OFFSET_2: - /* Configure offset register 2 */ + /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , @@ -6208,7 +6208,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I break; case ADC_OFFSET_3: - /* Configure offset register 3 */ + /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , @@ -6218,7 +6218,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I break; case ADC_OFFSET_4: - /* Configure offset register 4 */ + /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , @@ -6276,18 +6276,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ - /* For channels 10 to 18 */ + /* For channels 10 to 18U */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2, - ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1), - ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) ); + ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U), + ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) ); } - else /* For channels 1 to 9 */ + else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, - ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1), - ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) ); + ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U), + ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) ); } } @@ -6332,8 +6332,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -6404,7 +6404,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -6426,7 +6426,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ @@ -6446,7 +6446,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_JSQR_JSQ1 , ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, - 0x01) ); + 0x01U) ); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ @@ -6607,8 +6607,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -6692,7 +6692,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* - Set the analog watchdog enable mode: regular and/or injected */ /* groups, one or overall group of channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */ MODIFY_REG(hadc->Instance->CFGR , ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | @@ -6702,7 +6702,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) ); /* Shift the offset in function of the selected ADC resolution: */ - /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */ /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); @@ -6736,7 +6736,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG else { /* Shift the threshold in function of the selected ADC resolution */ - /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ + /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); @@ -6889,7 +6889,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* - Set the analog watchdog enable mode: regular and/or injected groups, */ /* one or all channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ - /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */ MODIFY_REG(hadc->Instance->CR1 , ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | @@ -7071,7 +7071,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F1 devices, in case of sequencer enabled */ + /* Note: On STM32F3 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && @@ -7143,7 +7143,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -7197,7 +7197,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ @@ -7256,9 +7256,9 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) { - uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0; - uint32_t tickstart = 0; - uint32_t Conversion_Timeout_CPU_cycles = 0; + uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U; + uint32_t tickstart = 0U; + uint32_t Conversion_Timeout_CPU_cycles = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -7272,7 +7272,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ - /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ + /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) && (hadc->Init.ContinuousConvMode==ENABLE) && @@ -7284,7 +7284,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) { - if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4)) + if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -7304,7 +7304,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co /* Stop potential conversion on going on regular group */ if (ConversionGroup != ADC_INJECTED_GROUP) { - /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { @@ -7316,7 +7316,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co /* Stop potential conversion on going on injected group */ if (ConversionGroup != ADC_REGULAR_GROUP) { - /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ + /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { @@ -7377,8 +7377,8 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tickstart = 0U; + __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -7391,8 +7391,8 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -7430,7 +7430,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) */ static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ if (ADC_IS_ENABLE(hadc) != RESET) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_can.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_can.c index a8a170873e6cb12c544eceacd29f2f7e93d2797b..31f38ab33aef7b6f14f0ade0866c02beb3907f27 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_can.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_can.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -170,7 +170,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check CAN handle */ if(hcan == NULL) @@ -292,7 +292,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) ((uint32_t)hcan->Init.SJW) | \ ((uint32_t)hcan->Init.BS1) | \ ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); + ((uint32_t)hcan->Init.Prescaler - 1U); /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; @@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { - uint32_t filternbrbitpos = 0; + uint32_t filternbrbitpos = 0U; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); @@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + filternbrbitpos = (1U) << sFilterConfig->FilterNumber; /* Initialisation mode for the filter */ hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; @@ -377,14 +377,14 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) @@ -393,12 +393,12 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy hcan->Instance->FS1R |= filternbrbitpos; /* 32-bit identifier or First 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ @@ -535,75 +535,78 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } + /* Process locked */ + __HAL_LOCK(hcan); - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + { + transmitmailbox = 0U; + } + else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + { + transmitmailbox = 1U; + } + else + { + transmitmailbox = 2U; + } - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ hcan->pTxMsg->IDE | \ hcan->pTxMsg->RTR); } /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0] ) ); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4] ) ); + /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); /* Get tick */ tickstart = HAL_GetTick(); @@ -614,9 +617,13 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Cancel transmission */ + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; @@ -645,9 +652,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_ERROR; } @@ -668,100 +672,99 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { /* Process Locked */ __HAL_LOCK(hcan); /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0; + transmitmailbox = 0U; } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1; + transmitmailbox = 1U; } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + else { - transmitmailbox = 2; + transmitmailbox = 2U; } - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable Error warning Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG); + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } - /* Enable Error passive Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV); + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - /* Enable Bus-off Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF); + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0] ) ); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4] ) ); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } - /* Enable Last error code Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC); + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR); + /* Process Unlocked */ + __HAL_UNLOCK(hcan); - /* Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME); + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - } + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { - return HAL_BUSY; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; } return HAL_OK; @@ -778,7 +781,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); @@ -801,12 +804,12 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u tickstart = HAL_GetTick(); /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -817,30 +820,30 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u } /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; if (hcan->pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) @@ -951,7 +954,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber */ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process locked */ __HAL_LOCK(hcan); @@ -1006,7 +1009,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process locked */ __HAL_LOCK(hcan); @@ -1072,7 +1075,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Check End of reception flag for FIFO0 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); @@ -1080,7 +1083,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Check End of reception flag for FIFO1 */ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U)) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); @@ -1329,30 +1332,30 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; if (hcan->pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cec.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cec.c index 5dbd1aa6e3ac45b1e09e98c67d42f1d39abe55b7..777c424ca25e5a71cd3087e137e1bebfa912bc14 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cec.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cec.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -12,36 +12,37 @@ * + IO operation functions * + Peripheral Control functions * + * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] - The CEC HAL driver can be used as follows: + The CEC HAL driver can be used as follow: (#) Declare a CEC_HandleTypeDef handle structure. (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: - (++) Enable the CEC interface clock. - (++) CEC pins configuration: - (+++) Enable the clock for the CEC GPIOs. - (+++) Configure these CEC pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() + (##) Enable the CEC interface clock. + (##) CEC pins configuration: + (+) Enable the clock for the CEC GPIOs. + (+) Configure these CEC pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() and HAL_CEC_Receive_IT() APIs): - (+++) Configure the CEC interrupt priority. - (+++) Enable the NVIC CEC IRQ handle. + (+) Configure the CEC interrupt priority. + (+) Enable the NVIC CEC IRQ handle. + (@) The specific CEC interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit + and receive process. (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in in case of Bit Rising Error, Error-Bit generation conditions, device logical address and Listen mode in the hcec Init structure. (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_CEC_MspInit() API. - -@@- The specific CEC interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit - and receive process. + (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_CEC_MspInit() API. @endverbatim ****************************************************************************** @@ -94,23 +95,20 @@ /** @defgroup CEC_Private_Constants CEC Private Constants * @{ */ -#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \ - | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \ - | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN) /** - * @} - */ + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup CEC_Private_Functions CEC Private Functions * @{ */ -static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); -static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); /** * @} */ + /* Exported functions ---------------------------------------------------------*/ /** @defgroup CEC_Exported_Functions CEC Exported Functions @@ -142,17 +140,15 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); */ /** - * @brief Initialize the CEC mode according to the specified - * parameters in the CEC_InitTypeDef and creates the associated handle. - * @param hcec: CEC handle. + * @brief Initializes the CEC mode according to the specified + * parameters in the CEC_InitTypeDef and creates the associated handle . + * @param hcec: CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) { - uint32_t tmpreg = 0x0; - /* Check the CEC handle allocation */ - if(hcec == NULL) + if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL)) { return HAL_ERROR; } @@ -166,51 +162,57 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); - assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); - assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); + assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); - - if(hcec->State == HAL_CEC_STATE_RESET) + if(hcec->gState == HAL_CEC_STATE_RESET) { /* Allocate lock resource and initialize it */ hcec->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK */ HAL_CEC_MspInit(hcec); } - - hcec->State = HAL_CEC_STATE_BUSY; + hcec->gState = HAL_CEC_STATE_BUSY; /* Disable the Peripheral */ __HAL_CEC_DISABLE(hcec); - tmpreg = hcec->Init.SignalFreeTime; - tmpreg |= hcec->Init.Tolerance; - tmpreg |= hcec->Init.BRERxStop; - tmpreg |= hcec->Init.BREErrorBitGen; - tmpreg |= hcec->Init.LBPEErrorBitGen; - tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen; - tmpreg |= hcec->Init.SignalFreeTimeOption; - tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS); - tmpreg |= hcec->Init.ListenMode; - /* Write to CEC Control Register */ - MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg); - - /* Enable the Peripheral */ + hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\ + hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\ + hcec->Init.ListenMode; + + /* Enable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); + + /* Enable the CEC Peripheral */ __HAL_CEC_ENABLE(hcec); - hcec->State = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->gState = HAL_CEC_STATE_READY; + hcec->RxState = HAL_CEC_STATE_READY; return HAL_OK; } - - /** - * @brief DeInitialize the CEC peripheral. - * @param hcec: CEC handle. + * @brief DeInitializes the CEC peripheral + * @param hcec: CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -224,15 +226,36 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /* Check the parameters */ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - hcec->State = HAL_CEC_STATE_BUSY; + hcec->gState = HAL_CEC_STATE_BUSY; /* DeInit the low level hardware */ HAL_CEC_MspDeInit(hcec); /* Disable the Peripheral */ __HAL_CEC_DISABLE(hcec); + /* Clear Flags */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR); + + /* Disable the following CEC Transmission/Reception interrupts as + * well as the following CEC Transmission/Reception Errors interrupts + * Rx Byte Received IT + * End of Reception IT + * Rx overrun + * Rx bit rising error + * Rx short bit period error + * Rx long bit period error + * Rx missing acknowledge + * Tx Byte Request IT + * End of Transmission IT + * Tx Missing Acknowledge IT + * Tx-Error IT + * Tx-Buffer Underrun IT + * Tx arbitration lost */ + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->State = HAL_CEC_STATE_RESET; + hcec->gState = HAL_CEC_STATE_RESET; + hcec->RxState = HAL_CEC_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hcec); @@ -241,31 +264,76 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) } /** - * @brief CEC MSP Init. - * @param hcec: CEC handle. + * @brief Initializes the Own Address of the CEC device + * @param hcec: CEC handle + * @param CEC_OwnAddress: The CEC own address. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); + + if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcec); + + hcec->gState = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) + { + hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U); + } + else + { + hcec->Instance->CFGR &= ~(CEC_CFGR_OAR); + } + + hcec->gState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief CEC MSP Init + * @param hcec: CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); - - /* NOTE : This function should not be modified; when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_CEC_MspInit can be implemented in the user file */ } /** - * @brief CEC MSP DeInit. - * @param hcec: CEC handle. + * @brief CEC MSP DeInit + * @param hcec: CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); - - /* NOTE : This function should not be modified; when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_CEC_MspDeInit can be implemented in the user file */ } @@ -279,19 +347,14 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) * @verbatim =============================================================================== - ##### IO operation function ##### + ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the CEC data transfers. - (+) The CEC handle must contain the initiator (TX side) and the destination (RX side) - logical addresses (4-bit long addresses, 0xF for broadcast messages destination) + (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) + logical addresses (4-bit long addresses, 0x0F for broadcast messages destination) - (+) There are two mode of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non Blocking mode: The communication is performed using Interrupts. + (#) The communication is performed using Interrupts. These API's return the HAL status. The end of the data processing will be indicated through the dedicated CEC IRQ when using Interrupt mode. @@ -300,462 +363,72 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) The HAL_CEC_ErrorCallback()user callback will be executed when a communication error is detected - (+) Blocking mode API's are : - (++) HAL_CEC_Transmit() - (++) HAL_CEC_Receive() + (#) API's with Interrupt are : + (+) HAL_CEC_Transmit_IT() + (+) HAL_CEC_IRQHandler() - (+) Non-Blocking mode API's with Interrupt are : - (++) HAL_CEC_Transmit_IT() - (++) HAL_CEC_Receive_IT() - (++) HAL_CEC_IRQHandler() - - (+) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (++) HAL_CEC_TxCpltCallback() - (++) HAL_CEC_RxCpltCallback() - (++) HAL_CEC_ErrorCallback() + (#) A set of User Callbacks are provided: + (+) HAL_CEC_TxCpltCallback() + (+) HAL_CEC_RxCpltCallback() + (+) HAL_CEC_ErrorCallback() @endverbatim * @{ */ /** - * @brief Send data in blocking mode. - * @param hcec: CEC handle. - * @param DestinationAddress: destination logical address. - * @param pData: pointer to input byte data buffer. - * @param Size: amount of data to be sent in bytes (without counting the header). - * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) -{ - uint8_t temp = 0; - uint32_t tempisr = 0; - uint32_t tickstart = 0; - - if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) - { - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - if((pData == NULL) && (Size > 0)) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - assert_param(IS_CEC_ADDRESS(DestinationAddress)); - assert_param(IS_CEC_MSGSIZE(Size)); - - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->State = HAL_CEC_STATE_BUSY_TX; - - hcec->TxXferCount = Size; - - /* case no data to be sent, sender is only pinging the system */ - if (Size == 0) - { - /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - - /* send header block */ - temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXDR = temp; - /* Set TX Start of Message (TXSOM) bit */ - __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - - while (hcec->TxXferCount > 0) - { - hcec->TxXferCount--; - - tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - - /* check whether error occured while waiting for TXBR to be set: - * has Tx underrun occurred ? - * has Tx error occurred ? - * has Tx Missing Acknowledge error occurred ? - * has Arbitration Loss error occurred ? */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } - /* TXBR to clear BEFORE writing TXDR register */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); - if (hcec->TxXferCount == 0) - { - /* if last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - hcec->Instance->TXDR = *pData++; - - /* error check after TX byte write up */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } /* end while (while (hcec->TxXferCount > 0)) */ - - - /* if no error up to this point, check that transmission is - * complete, that is wait until TXEOM is reset */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - } - - /* Final error check once all bytes have been transmitted */ - tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = tempisr; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive data in blocking mode. Must be invoked when RXBR has been set. + * @brief Send data in interrupt mode * @param hcec: CEC handle - * @param pData: pointer to received data buffer. - * @param Timeout: Timeout duration. - * @note The received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0; - - if (hcec->State == HAL_CEC_STATE_READY) - { - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - if (pData == NULL) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - hcec->RxXferSize = 0; - /* Process Locked */ - __HAL_LOCK(hcec); - - - /* Rx loop until CEC_FLAG_RXEND is set */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) - { - tickstart = HAL_GetTick(); - /* Wait for next byte to be received */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - /* any error so far ? - * has Rx Missing Acknowledge occurred ? - * has Rx Long Bit Period error occurred ? - * has Rx Short Bit Period error occurred ? - * has Rx Bit Rising error occurred ? - * has Rx Overrun error occurred ? */ - temp = (uint32_t) (hcec->Instance->ISR); - if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0) - { - /* copy ISR for error handling purposes */ - hcec->ErrorCode = temp; - /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)); - hcec->State = HAL_CEC_STATE_ERROR; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */ - - - /* read received data */ - *pData++ = hcec->Instance->RXDR; - temp = (uint32_t) (hcec->Instance->ISR); - /* end of message ? */ - if ((temp & CEC_FLAG_RXEND) != 0) - { - assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_OK; - } - - /* clear Rx-Byte Received flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); - /* increment payload byte counter */ - hcec->RxXferSize++; - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */ - - /* if the instructions below are executed, it means RXEND was set when RXBR was - * set for the first time: - * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))" - * loop has not been executed and this means a single byte has been sent */ - *pData++ = hcec->Instance->RXDR; - /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ - hcec->RxXferSize = 0; - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Send data in interrupt mode. - * @param hcec: CEC handle. - * @param DestinationAddress: destination logical address. - * @param pData: pointer to input byte data buffer. + * @param InitiatorAddress: Initiator address + * @param DestinationAddress: destination logical address + * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) { - uint8_t temp = 0; /* if the IP isn't already busy and if there is no previous transmission already pending due to arbitration lost */ - if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) - && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) + if (hcec->gState == HAL_CEC_STATE_READY) { - if((pData == NULL) && (Size > 0)) + if((pData == NULL ) && (Size > 0U)) { - hcec->State = HAL_CEC_STATE_ERROR; return HAL_ERROR; } assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_ADDRESS(InitiatorAddress)); assert_param(IS_CEC_MSGSIZE(Size)); /* Process Locked */ __HAL_LOCK(hcec); hcec->pTxBuffPtr = pData; - hcec->State = HAL_CEC_STATE_BUSY_TX; + hcec->gState = HAL_CEC_STATE_BUSY_TX; hcec->ErrorCode = HAL_CEC_ERROR_NONE; - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Enable the following two CEC Transmission interrupts as - * well as the following CEC Transmission Errors interrupts: - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - /* initialize the number of bytes to send, * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = Size; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - /* in case of no payload (Size = 0), sender is only pinging the system; - * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ - if (Size == 0) + /* in case of no payload (Size = 0U), sender is only pinging the system; + Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ + if (Size == 0U) { __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* send header block */ - temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXDR = temp; + hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress); /* Set TX Start of Message (TXSOM) bit */ __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - return HAL_OK; - } - /* if the IP is already busy or if there is a previous transmission - already pending due to arbitration loss */ - else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) - { - __HAL_LOCK(hcec); - /* set state to BUSY TX, in case it wasn't set already (case - * of transmission new attempt after arbitration loss) */ - if (hcec->State != HAL_CEC_STATE_BUSY_TX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - - /* if all data have been sent */ - if(hcec->TxXferCount == 0) - { - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); - /* Disable the CEC Transmission Error Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); - - hcec->State = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the possibility to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hcec); - - HAL_CEC_TxCpltCallback(hcec); - - return HAL_OK; - } - else - { - if (hcec->TxXferCount == 1) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - hcec->TxXferCount--; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Receive data in interrupt mode. - * @param hcec: CEC handle. - * @param pData: pointer to received data buffer. - * @note The received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) -{ - if(hcec->State == HAL_CEC_STATE_READY) - { - if(pData == NULL) - { - hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hcec); - hcec->RxXferSize = 0; - hcec->pRxBuffPtr = pData; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - /* the IP is moving to a ready to receive state */ - hcec->State = HAL_CEC_STATE_STANDBY_RX; - - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Enable the following CEC Reception Error Interrupts: - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR); - /* Process Unlocked */ __HAL_UNLOCK(hcec); - /* Enable the following two CEC Reception interrupts: - * Rx Byte Received IT - * End of Reception IT */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND); - - __HAL_CEC_ENABLE(hcec); - return HAL_OK; + } else { @@ -763,128 +436,133 @@ HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) } } - - /** * @brief Get size of the received frame. - * @param hcec: CEC handle. + * @param hcec: CEC handle * @retval Frame size */ -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) { return hcec->RxXferSize; } +/** + * @brief Change Rx Buffer. + * @param hcec: CEC handle + * @param Rxbuffer: Rx Buffer + * @note This function can be called only inside the HAL_CEC_RxCpltCallback() + * @retval Frame size + */ +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) +{ + hcec->Init.RxBuffer = Rxbuffer; +} /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle. + * @param hcec: CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { - /* save interrupts register for further error or interrupts handling purposes */ - hcec->ErrorCode = hcec->Instance->ISR; - /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE); - hcec->State = HAL_CEC_STATE_ERROR; - } - /* CEC transmit error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR); - hcec->State = HAL_CEC_STATE_ERROR; - } + /* save interrupts register for further error or interrupts handling purposes */ + uint32_t reg = 0U; + reg = hcec->Instance->ISR; - /* CEC TX underrun error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR); - hcec->State = HAL_CEC_STATE_ERROR; - } - /* CEC TX arbitration error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET)) + /* ----------------------------Arbitration Lost Management----------------------------------*/ + /* CEC TX arbitration error interrupt occurred --------------------------------------*/ + if((reg & CEC_FLAG_ARBLST) != RESET) { + hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); - hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX overrun error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR); - hcec->State = HAL_CEC_STATE_ERROR; - } - - /* CEC RX bit rising error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) + /* ----------------------------Rx Management----------------------------------*/ + /* CEC RX byte received interrupt ---------------------------------------------------*/ + if((reg & CEC_FLAG_RXBR) != RESET) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); - hcec->State = HAL_CEC_STATE_ERROR; + /* reception is starting */ + hcec->RxState = HAL_CEC_STATE_BUSY_RX; + hcec->RxXferSize++; + /* read received byte */ + *hcec->Init.RxBuffer++ = hcec->Instance->RXDR; + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); } - /* CEC RX short bit period error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) + /* CEC RX end received interrupt ---------------------------------------------------*/ + if((reg & CEC_FLAG_RXEND) != RESET) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); - hcec->State = HAL_CEC_STATE_ERROR; - } + /* clear IT */ + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); - /* CEC RX long bit period error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); - hcec->State = HAL_CEC_STATE_ERROR; + /* Rx process is completed, restore hcec->RxState to Ready */ + hcec->RxState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->Init.RxBuffer -= hcec->RxXferSize; + HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); + hcec->RxXferSize = 0U; } - /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) + /* ----------------------------Tx Management----------------------------------*/ + /* CEC TX byte request interrupt ------------------------------------------------*/ + if((reg & CEC_FLAG_TXBR) != RESET) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); - hcec->State = HAL_CEC_STATE_ERROR; + if (hcec->TxXferCount == 0U) + { + /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ + __HAL_CEC_LAST_BYTE_TX_SET(hcec); + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + } + else + { + hcec->Instance->TXDR = *hcec->pTxBuffPtr++; + hcec->TxXferCount--; + } + /* clear Tx-Byte request flag */ + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); } - if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0) + /* CEC TX end interrupt ------------------------------------------------*/ + if((reg & CEC_FLAG_TXEND) != RESET) { - HAL_CEC_ErrorCallback(hcec); - } + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); - /* CEC RX byte received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET)) - { - /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Receive_IT(hcec); + /* Tx process is ended, restore hcec->gState to Ready */ + hcec->gState = HAL_CEC_STATE_READY; + /* Call the Process Unlocked before calling the Tx call back API to give the possibility to + start again the Transmission under the Tx call back API */ + __HAL_UNLOCK(hcec); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + HAL_CEC_TxCpltCallback(hcec); } - /* CEC RX end received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET)) + /* ----------------------------Rx/Tx Error Management----------------------------------*/ + if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U) { - /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Receive_IT(hcec); - } + hcec->ErrorCode = reg; + __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE); - /* CEC TX byte request interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET)) - { - /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Transmit_IT(hcec); - } + if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET) + { + hcec->Init.RxBuffer-=hcec->RxXferSize; + hcec->RxXferSize = 0U; + hcec->RxState = HAL_CEC_STATE_READY; + } + else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET)) + { + /* Set the CEC state ready to be able to start again the process */ + hcec->gState = HAL_CEC_STATE_READY; + } - /* CEC TX end interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET)) - { - /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ - CEC_Transmit_IT(hcec); + /* Error Call Back */ + HAL_CEC_ErrorCallback(hcec); } } - /** * @brief Tx Transfer completed callback * @param hcec: CEC handle @@ -894,7 +572,6 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, the HAL_CEC_TxCpltCallback can be implemented in the user file */ @@ -903,68 +580,71 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback * @param hcec: CEC handle + * @param RxFrameSize: Size of frame * @retval None */ -__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) +__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CEC_TxCpltCallback can be implemented in the user file. + UNUSED(RxFrameSize); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_RxCpltCallback can be implemented in the user file */ } /** - * @brief CEC error callback. - * @param hcec: CEC handle. + * @brief CEC error callbacks + * @param hcec: CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_CEC_ErrorCallback can be implemented in the user file. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CEC_ErrorCallback can be implemented in the user file */ } - /** * @} */ -/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions +/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function * @brief CEC control functions * @verbatim =============================================================================== - ##### Peripheral Control functions ##### + ##### Peripheral Control function ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the CEC. (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. - (+) HAL_CEC_GetError() API report the CEC handle error code. + (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. @endverbatim * @{ */ - /** - * @brief Return the CEC state. - * @param hcec: CEC handle. + * @brief return the CEC state + * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC module. * @retval HAL state */ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) { - return hcec->State; + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = hcec->gState; + temp2 = hcec->RxState; + + return (HAL_CEC_StateTypeDef)(temp1 | temp2); } /** -* @brief Return the CEC error code. -* @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * @brief Return the CEC error code + * @param hcec : pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. -* @retval CEC Error Code -*/ + * @retval CEC Error Code + */ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; @@ -978,165 +658,14 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) * @} */ -/** @defgroup CEC_Private_Functions CEC Private Functions - * @{ - */ - - /** - * @brief Send data in interrupt mode. - * @param hcec: CEC handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_CEC_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) -{ - /* if the IP is already busy or if there is a previous transmission - already pending due to arbitration loss */ - if ((hcec->State == HAL_CEC_STATE_BUSY_TX) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) - { - - /* set state to BUSY TX, in case it wasn't set already (case - * of transmission new attempt after arbitration loss) */ - if (hcec->State != HAL_CEC_STATE_BUSY_TX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - - /* if all data have been sent */ - if(hcec->TxXferCount == 0) - { - /* Disable Peripheral to write CEC_IER register */ - __HAL_CEC_DISABLE(hcec); - - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); - /* Disable the CEC Transmission Error Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); - - /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */ - if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET) - { - hcec->State = HAL_CEC_STATE_STANDBY_RX; - } - else - { - hcec->State = HAL_CEC_STATE_READY; - } - HAL_CEC_TxCpltCallback(hcec); - - return HAL_OK; - } - else - { - if (hcec->TxXferCount == 1) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); - hcec->Instance->TXDR = *hcec->pTxBuffPtr++; - hcec->TxXferCount--; - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Receive data in interrupt mode. - * @param hcec: CEC handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_CEC_Receive_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) -{ - uint32_t tempisr; - - /* Three different conditions are tested to carry out the RX IT processing: - * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and - * the reception of the first byte is starting - * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX) - * and a new byte is being received - * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX) - * but has been interrupted by a new message reception or discarded due to - * arbitration loss: the reception of the first or higher priority message - * (the arbitration winner) is starting */ - if ((hcec->State == HAL_CEC_STATE_STANDBY_RX) - || (hcec->State == HAL_CEC_STATE_BUSY_RX) - || (hcec->State == HAL_CEC_STATE_BUSY_TX)) - { - /* reception is starting */ - hcec->State = HAL_CEC_STATE_BUSY_RX; - tempisr = (uint32_t) (hcec->Instance->ISR); - if ((tempisr & CEC_FLAG_RXBR) != 0) - { - /* read received byte */ - *hcec->pRxBuffPtr++ = hcec->Instance->RXDR; - /* if last byte has been received */ - if ((tempisr & CEC_FLAG_RXEND) != 0) - { - /* clear IT */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND); - /* RX interrupts are not disabled at this point. - * Indeed, to disable the IT, the IP must be disabled first - * which resets the TXSOM flag. In case of arbitration loss, - * this leads to a transmission abort. - * Therefore, RX interruptions disabling if so required, - * is done in HAL_CEC_RxCpltCallback */ - - /* IP state is moved to READY. - * If the IP must remain in standby mode to listen - * any new message, it is up to HAL_CEC_RxCpltCallback - * to move it again to HAL_CEC_STATE_STANDBY_RX */ - hcec->State = HAL_CEC_STATE_READY; - - HAL_CEC_RxCpltCallback(hcec); - - return HAL_OK; - } - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); - - hcec->RxXferSize++; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ +#endif /* defined(STM32F373xC) || defined(STM32F378xx) */ +#endif /* HAL_CEC_MODULE_ENABLED */ /** * @} */ -#endif /* defined(STM32F373xC) || defined(STM32F378xx) */ - -#endif /* HAL_CEC_MODULE_ENABLED */ /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_comp.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_comp.c index 9ef54d34fdd29ac1b1053c3118c9931e17ff5f9a..e10142cff25f93fbea3561e66364d31f10d0627d 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_comp.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_comp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_comp.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -132,27 +132,27 @@ +------------------------------------------------------------------------------------------+ | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |-----------------|----------------|---------------|---------------------------------------| - | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | - | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK | - | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | + | | 1U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | + | | 1U/2 VREFINT | OK | OK | OK | OK | OK | OK | OK | + | | 3U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK | | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK | | | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK | | | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK | - | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 | - | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- | + | | IO1 | PA0 | PA2 | PD15U | PE8 | PD13U | PD10U | PC0 | + | | IO2 | --- | --- | PB12U | PB2 | PB10U | PB15U | --- | |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------| - | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 | - | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 | + | Non Inverting | IO1 | PA1 | PA7 | PB14U | PB0 | PD12U | PD11U | PA0 | + | Input | IO2 | --- | PA3 | PD14U | PE7 | PB13U | PB11U | PC1 | +------------------------------------------------------------------------------------------+ Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices +-------------------------------------------------------+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |-------|-------|-------|-------|-------|-------|-------| - | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 | + | PA0 | PA2 | PB1 | PC8 | PC7 | PA10U | PC2 | | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- | - | PA6 | PA12 | --- | --- | --- | --- | --- | - | PA11 | PB9 | --- | --- | --- | --- | --- | + | PA6 | PA12U | --- | --- | --- | --- | --- | + | PA11U | PB9 | --- | --- | --- | --- | --- | | PB8 | --- | --- | --- | --- | --- | --- | +-------------------------------------------------------+ @@ -189,11 +189,11 @@ +----------------------------------------------------------------------------------------------------------------------+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 | |----------------|----------------|----------------|----------------|----------------|----------------|----------------| - | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) | + | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) | | | | | | | | | | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | | | | | | | | | - | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) | + | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) | | | | | | | | | | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | | | | | | | | | @@ -213,7 +213,7 @@ | | | | | | | | | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN | | | | | | | | | - | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)| + | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)| | | | | | | | | | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | | | | | | | | | @@ -224,8 +224,8 @@ | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | | | | | | | | | +----------------------------------------------------------------------------------------------------------------------+ - (1): This connection consists of connecting both GPIO and COMP output to TIM1/8/20 BRK input through an OR gate, instead - of connecting the GPIO to the TIM1/8/20 BRK input and the COMP output to the TIM1/8/20 BRK_ACTH input. The aim is to + (1U): This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead + of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to add a digital filter (3 bits) on the COMP output. Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices @@ -261,7 +261,7 @@ /** @defgroup COMP_Private_Constants COMP Private Constants * @{ */ -#define COMP_LOCK_DISABLE ((uint32_t)0x00000000) +#define COMP_LOCK_DISABLE (0x00000000U) #define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK /** * @} @@ -456,7 +456,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - uint32_t extiline = 0; + uint32_t extiline = 0U; /* Check the COMP handle allocation and lock status */ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) @@ -563,7 +563,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - uint32_t extiline = 0; + uint32_t extiline = 0U; /* Check the COMP handle allocation and lock status */ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) @@ -763,14 +763,14 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { - uint32_t level=0; + uint32_t level=0U; /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT); - if(level != 0) + if(level != 0U) { return(COMP_OUTPUTLEVEL_HIGH); } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cortex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cortex.c index 890c87f969393782f6241469c74084a333c8f4b7..8ae20cbd10ec0eae93aaa35f83edeb8b09a52b5d 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cortex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_cortex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -46,7 +46,7 @@ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Configures the SysTick IRQ priority to the lowest value (0x0FU). (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. @@ -105,19 +105,19 @@ ========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority + NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority | | | 0 bits for subpriority ========================================================================================================================== @@ -208,7 +208,7 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t prioritygroup = 0x00; + uint32_t prioritygroup = 0x00U; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); @@ -294,8 +294,42 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) * @{ */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) + +/** + * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation) + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL = 0U; +} + /** + * @brief Enables the MPU + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +} + + /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. @@ -335,8 +369,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) } else { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ @@ -404,7 +438,7 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { - /* Return 1 if pending else 0 */ + /* Return 1 if pending else 0U */ return NVIC_GetPendingIRQ(IRQn); } @@ -431,7 +465,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { - /* Return 1 if active else 0 */ + /* Return 1 if active else 0U */ return NVIC_GetActive(IRQn); } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc.c index 91efea528df3aa848039a2cedd169b3264db5c17..a77a3e806e2b12a0bfb44ba16036642324663f2c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -276,12 +276,12 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer using the combination of the previous CRC value and the new one [..] or - (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer independently of the previous CRC value. @endverbatim @@ -305,8 +305,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index = 0U; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -318,7 +318,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -365,8 +365,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; /* CRC input data buffer index */ - uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ + uint32_t index = 0U; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ /* Process locked */ __HAL_LOCK(hcrc); @@ -382,7 +382,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t { case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -464,27 +464,27 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ - for(i = 0; i < (BufferLength/4); i++) + for(i = 0U; i < (BufferLength/4U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3]; } /* last bytes specific handling */ - if ((BufferLength%4) != 0) + if ((BufferLength%4U) != 0U) { - if (BufferLength%4 == 1) + if (BufferLength%4U == 1U) { *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; } - if (BufferLength%4 == 2) + if (BufferLength%4U == 2U) { *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; } - if (BufferLength%4 == 3) + if (BufferLength%4U == 3U) { *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; @@ -507,16 +507,16 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i = 0; /* input data buffer index */ + uint32_t i = 0U; /* input data buffer index */ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ - for(i = 0; i < (BufferLength/2); i++) + for(i = 0U; i < (BufferLength/2U); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1]; } - if ((BufferLength%2) != 0) + if ((BufferLength%2U) != 0U) { *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc_ex.c index 42bb9a792af744b2cc37a0b4b8288e220c40d1d0..865a8ab732a5b5580c345e4c481a6dccd6c3345e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. @@ -106,7 +106,7 @@ */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { - uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); @@ -118,7 +118,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & (1U << msb)) == 0) && (msb-- > 0)){} + while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U)){} switch (PolyLength) { diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac.c index 4594d4d5e9bea14471470e8929c6e4ec57feadb9..417c25668379aad53a94c856900632a3432e2f7e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -105,7 +105,7 @@ VEF+ is the input voltage reference (refer to the device datasheet) [..] e.g. To set DAC_OUT1 to 0.7V, use - (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V *** DMA requests *** ===================== @@ -490,8 +490,8 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) - /* For all products including channel 2 */ - /* DAC channel 2 is available on top of DAC channel 1 */ + /* For all products including channel 2U */ + /* DAC channel 2 is available on top of DAC channel 1U */ else /* Channel2 is used for */ { /* Disable the DMA channel */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac_ex.c index b2d6d16a7dde876787ba78a02e7c82b81b4f68c5..b854ef81274b63d351d74eb04b9436c11264158d 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief DACEx HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. @@ -81,7 +81,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is available on top of DAC channel 1 */ +/* DAC channel 2 is available on top of DAC channel 1U */ static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); @@ -108,7 +108,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); [..] This section provides functions allowing to: (+) Set the specified data holding register value for DAC channel. (+) Set the specified data holding register value for dual DAC channel - (when DAC channel 2 is present in DAC 1) + (when DAC channel 2 is present in DAC 1U) @endverbatim * @{ @@ -129,7 +129,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -139,7 +139,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui tmp = (uint32_t) (hdac->Instance); /* DAC 1 has 1 or 2 channels - no DAC2 */ -/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */ +/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */ if(Channel == DAC_CHANNEL_1) { @@ -169,7 +169,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is present in DAC 1 */ +/* DAC channel 2 is present in DAC 1U */ /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -187,7 +187,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { - uint32_t data = 0, tmp = 0; + uint32_t data = 0U, tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); @@ -197,11 +197,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t) (hdac->Instance); @@ -246,7 +246,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */ +/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -307,7 +307,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -/* DAC 1 has 1 channels 1 */ +/* DAC 1 has 1 channels 1U */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -352,12 +352,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /* STM32F302xC || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ -/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */ +/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC 1 has 2 channels 1 & 2 */ +/* DAC 1 has 2 channels 1U & 2U */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -377,7 +377,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel)); @@ -403,7 +403,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - /* Case of use of channel 1 */ + /* Case of use of channel 1U */ switch(Alignment) { case DAC_ALIGN_12B_R: @@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - /* Case of use of channel 2 */ + /* Case of use of channel 2U */ switch(Alignment) { case DAC_ALIGN_12B_R: @@ -491,7 +491,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -/* DAC 1 has 1 channel (channel 1) */ +/* DAC 1 has 1 channel (channel 1U) */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -510,7 +510,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel)); @@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - /* Case of use of channel 1 */ + /* Case of use of channel 1U */ switch(Alignment) { case DAC_ALIGN_12B_R: @@ -573,12 +573,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* STM32F302xC || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ -/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */ +/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC 1 has 2 channels 1 & 2 */ +/* DAC 1 has 2 channels 1U & 2U */ /** * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -612,7 +612,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -/* DAC 1 has 1 channel (channel 1) */ +/* DAC 1 has 1 channel (channel 1U) */ /** * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -642,7 +642,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp |= hdac->Instance->DOR1; @@ -650,8 +650,8 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is present in DAC 1 */ - tmp |= hdac->Instance->DOR2 << 16; +/* DAC channel 2 is present in DAC 1U */ + tmp |= hdac->Instance->DOR2 << 16U; #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ @@ -665,7 +665,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is available on top of DAC channel 1 */ +/* DAC channel 2 is available on top of DAC channel 1U */ /** * @brief Handles DAC interrupt request * This function uses the interruption of DMA @@ -678,7 +678,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac) { if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) { - /* Check underrun flag of DAC channel 1 */ + /* Check underrun flag of DAC channel 1U */ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) { /* Change DAC state to error state */ @@ -700,7 +700,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { - /* Check underrun flag of DAC channel 1 */ + /* Check underrun flag of DAC channel 1U */ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) { /* Change DAC state to error state */ @@ -741,7 +741,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac) { if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) { - /* Check underrun flag of DAC channel 1 */ + /* Check underrun flag of DAC channel 1U */ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) { /* Change DAC state to error state */ @@ -780,7 +780,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac) HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; + uint32_t tmpreg1 = 0U, tmpreg2 = 0U; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Output Buffer (BOFF1) control */ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); } - else /* DAC1 channel 2 & DAC2 channel 1 */ + else /* DAC1 channel 2U & DAC2 channel 1U */ { /* Output Switch (OUTEN) control */ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch)); @@ -823,7 +823,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); } - else /* DAC1 channel 2 & DAC2 channel 1 */ + else /* DAC1 channel 2U & DAC2 channel 1U */ { /* Output Switch (OUTEN) control */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel); @@ -955,7 +955,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is available on top of DAC channel 1 */ +/* DAC channel 2 is available on top of DAC channel 1U */ /** * @brief Conversion complete callback in non blocking mode for Channel2 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -1086,7 +1086,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) -/* DAC channel 2 is available on top of DAC channel 1 */ +/* DAC channel 2 is available on top of DAC channel 1U */ /** * @brief DMA conversion complete callback. * @param hdma: pointer to DMA handle. diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dma.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dma.c index 63e51a4de6ff9631fe181eb506134957b665b044..1cffb4804dd87cf9f35bcb7131746d58f3443fa9 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dma.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -18,7 +18,7 @@ [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals + necessary). Please refer to Reference manual for connection between peripherals and DMA requests . (#) For a given Channel, program the required configuration through the following parameters: @@ -48,7 +48,7 @@ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured - (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e a member of DMA handle structure). @@ -58,14 +58,6 @@ [..] Below the list of most used macros in DMA HAL driver. - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. - [..] (@) You can refer to the DMA HAL driver header file for more useful macros @@ -116,14 +108,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @{ - */ -#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ -/** - * @} - */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -131,6 +115,7 @@ * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); /** * @} */ @@ -161,18 +146,18 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** - * @brief Initializes the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the DMA handle allocation */ - if(hdma == NULL) + if(NULL == hdma) { return HAL_ERROR; } @@ -187,12 +172,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - if(hdma->State == HAL_DMA_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - } - /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -213,17 +192,30 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; + /* Initialize DmaBaseAddress and ChannelIndex parameters used + by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** - * @brief DeInitializes the DMA peripheral + * @brief DeInitialize the DMA peripheral * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status @@ -231,7 +223,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ - if(hdma == NULL) + if(NULL == hdma) { return HAL_ERROR; } @@ -240,24 +232,25 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); + hdma->Instance->CCR &= ~DMA_CCR_EN; /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; + hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0; + hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0; + hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0; + hdma->Instance->CMAR = 0U; + + /* Get DMA Base Address */ + DMA_CalcBaseAndBitshift(hdma); /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -295,8 +288,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ /** - * @brief Starts the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief Start the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address @@ -305,25 +298,40 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + /* Process locked */ __HAL_LOCK(hdma); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - return HAL_OK; + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; } /** @@ -337,87 +345,82 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - /* Process locked */ - __HAL_LOCK(hdma); + HAL_StatusTypeDef status = HAL_OK; - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); + /* Process locked */ + __HAL_LOCK(hdma); - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + /* Enable the transfer complete, & transfer error interrupts */ + /* Half transfer interrupt is optional: enable it only if associated callback is available */ + if(NULL != hdma->XferHalfCpltCallback ) + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + } + else + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - return HAL_OK; + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; } /** - * @brief Aborts the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * - * @note After disabling a DMA Channel, a check for wait until the DMA Channel is - * effectively disabled is added. If a Channel is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. + * @brief Abort the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t tickstart = 0x00; + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); - /* Check if the DMA Channel is effectively disabled */ - while((hdma->Instance->CCR & DMA_CCR_EN) != 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - return HAL_TIMEOUT; - } - } - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; + return HAL_OK; } /** - * @brief Aborts the DMA Transfer in Interrupt mode. + * @brief Abort the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status @@ -435,14 +438,15 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) } else { + /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); + hdma->Instance->CCR &= ~DMA_CCR_EN; /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; @@ -470,35 +474,52 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; - uint32_t tickstart = 0x00; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ - temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + temp = DMA_FLAG_TC1 << hdma->ChannelIndex; } else { /* Half Transfer Complete flag */ - temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + temp = DMA_FLAG_HT1 << hdma->ChannelIndex; } /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) { - if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) + if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) { - /* Clear the transfer error flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; + hdma->State= HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); @@ -508,40 +529,35 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; + hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); - return HAL_TIMEOUT; + return HAL_ERROR; } } } - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; - } else { /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers of half buffer are complete) */ - hdma->State = HAL_DMA_STATE_READY_HALF; + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; } /* Process unlocked */ @@ -551,95 +567,202 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } /** - * @brief Handles DMA interrupt request. + * @brief Handle DMA interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + + /* DMA peripheral state is not updated in Half Transfer */ + /* State is updated only in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete & transfer error interrupts */ + /* if the DMA mode is not CIRCULAR */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { - /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Then, disable all DMA interrupts */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); + /* Process Unlocked */ + __HAL_UNLOCK(hdma); - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); } } +} - /* Half Transfer Complete Interrupt management ******************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + switch (CallbackID) { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF; + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; } } - - /* Transfer Complete Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + else { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); - } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + status = HAL_ERROR; + } - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); + /* Release Lock */ + __HAL_UNLOCK(hdma); - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; + return status; +} - /* Process Unlocked */ - __HAL_UNLOCK(hdma); +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; } } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; } /** @@ -675,8 +798,8 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) @@ -692,12 +815,12 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ -/** @addtogroup DMA_Private_Functions DMA Private Functions +/** @addtogroup DMA_Private_Functions * @{ */ /** - * @brief Sets the DMA Transfer parameter. + * @brief Set the DMA Transfer parameters. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address @@ -707,6 +830,9 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; @@ -730,17 +856,51 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t } } +/** + * @brief Set the DMA base address and channel index depending on DMA instance + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif +} + /** * @} */ -#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ + /** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash.c index 784c24a4bf47b8fbb3678a133d05a674fe088a97..64dd9d2ce25b44e6c7df983538df58061bb2dbed 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -176,18 +176,18 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: Specifies the address to be programmed. - * @param Data: Specifies the data to be programmed + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_ERROR; - uint8_t index = 0; - uint8_t nbiterations = 0; + uint8_t index = 0U; + uint8_t nbiterations = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -204,22 +204,22 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ - nbiterations = 1; + nbiterations = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ - nbiterations = 2; + nbiterations = 2U; } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ - nbiterations = 4; + nbiterations = 4U; } - for (index = 0; index < nbiterations; index++) + for (index = 0U; index < nbiterations; index++) { - FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index))); + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -248,10 +248,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: Specifies the address to be programmed. - * @param Data: Specifies the data to be programmed + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -276,19 +276,19 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; /* Program halfword (16-bit) at a specified address. */ - pFlash.DataRemaining = 1; + pFlash.DataRemaining = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; /* Program word (32-bit : 2*16-bit) at a specified address. */ - pFlash.DataRemaining = 2; + pFlash.DataRemaining = 2U; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; /* Program double word (64-bit : 4*16-bit) at a specified address. */ - pFlash.DataRemaining = 4; + pFlash.DataRemaining = 4U; } /* Program halfword (16-bit) at a specified address. */ @@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u */ void HAL_FLASH_IRQHandler(void) { - uint32_t addresstmp = 0; + uint32_t addresstmp = 0U; /* Check FLASH operation error flags */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) @@ -338,7 +338,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.DataRemaining--; /* Check if there are still pages to erase */ - if(pFlash.DataRemaining != 0) + if(pFlash.DataRemaining != 0U) { addresstmp = pFlash.Address; /*Indicate user which sector has been erased */ @@ -370,7 +370,7 @@ void HAL_FLASH_IRQHandler(void) /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); + HAL_FLASH_EndOfOperationCallback(0U); /* Stop Mass Erase procedure*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -381,14 +381,14 @@ void HAL_FLASH_IRQHandler(void) pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0) + if(pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ - pFlash.Address += 2; + pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16); + pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -406,11 +406,11 @@ void HAL_FLASH_IRQHandler(void) } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2); + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure */ @@ -644,7 +644,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { return HAL_TIMEOUT; } @@ -677,7 +677,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) */ static void FLASH_SetErrorCode(void) { - uint32_t flags = 0; + uint32_t flags = 0U; if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) { diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash_ex.c index 36041364dfb4e47c13ae8f0ab4291e43018e2e50..67fce8357d2cf9855e0b896ea4b1c726540b47ef 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following @@ -177,7 +177,7 @@ static uint8_t FLASH_OB_GetUser(void); HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; - uint32_t address = 0; + uint32_t address = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -482,7 +482,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) */ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { - uint32_t value = 0; + uint32_t value = 0U; if (DATAAdress == OB_DATA_ADDRESS_DATA0) { @@ -539,15 +539,15 @@ static void FLASH_MassErase(void) static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFF; + uint16_t WRP0_Data = 0xFFFFU; #if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFF; + uint16_t WRP1_Data = 0xFFFFU; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFF; + uint16_t WRP2_Data = 0xFFFFU; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFF; + uint16_t WRP3_Data = 0xFFFFU; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ @@ -561,17 +561,17 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #endif /* OB_WRP_PAGES48TO63MASK */ /* Wait for last operation to be completed */ @@ -590,7 +590,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFF) + if(WRP0_Data != 0xFFU) { OB->WRP0 &= WRP0_Data; @@ -600,7 +600,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP0_WRP0 */ #if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 &= WRP1_Data; @@ -610,7 +610,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 &= WRP2_Data; @@ -620,7 +620,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFF)) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 &= WRP3_Data; @@ -651,15 +651,15 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; - uint16_t WRP0_Data = 0xFFFF; + uint16_t WRP0_Data = 0xFFFFU; #if defined(OB_WRP1_WRP1) - uint16_t WRP1_Data = 0xFFFF; + uint16_t WRP1_Data = 0xFFFFU; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - uint16_t WRP2_Data = 0xFFFF; + uint16_t WRP2_Data = 0xFFFFU; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - uint16_t WRP3_Data = 0xFFFF; + uint16_t WRP3_Data = 0xFFFFU; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ @@ -673,17 +673,17 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #endif /* OB_WRP_PAGES48TO63MASK */ @@ -702,7 +702,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(OB_WRP0_WRP0) - if(WRP0_Data != 0xFF) + if(WRP0_Data != 0xFFU) { OB->WRP0 |= WRP0_Data; @@ -712,7 +712,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP0_WRP0 */ #if defined(OB_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 |= WRP1_Data; @@ -722,7 +722,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 |= WRP2_Data; @@ -732,7 +732,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFF)) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 |= WRP3_Data; @@ -836,9 +836,9 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) - OB->USER = (UserConfig | 0x08); + OB->USER = (UserConfig | 0x08U); #else - OB->USER = (UserConfig | 0x88); + OB->USER = (UserConfig | 0x88U); #endif /* Wait for last operation to be completed */ @@ -913,7 +913,7 @@ static uint32_t FLASH_OB_GetWRP(void) static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; - uint32_t tmp_reg = 0; + uint32_t tmp_reg = 0U; /* Read RDP level bits */ #if defined(FLASH_OBR_RDPRT) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_gpio.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_gpio.c index 95c4a7723ff22864338be14d3aa73f816825e218..97de09a568065dab3bf867588d6441bd491f70c8 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_gpio.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_gpio.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -82,7 +82,7 @@ pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as @@ -139,15 +139,15 @@ /** @defgroup GPIO_Private_Defines GPIO Private Defines * @{ */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) - -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) + +#define GPIO_NUMBER (16U) /** * @} */ @@ -189,9 +189,9 @@ */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -217,15 +217,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); GPIOx->AFR[position >> 3] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ @@ -236,21 +236,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); GPIOx->OTYPER = temp; } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ @@ -261,8 +261,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); + temp &= ~((0x0FU) << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2] = temp; /* Clear EXTI line configuration */ @@ -314,9 +314,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -332,29 +332,29 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floting Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + tmp &= ((0x0FU) << (4U * (position & 0x03U))); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + tmp = (0x0FU) << (4U * (position & 0x03U)); SYSCFG->EXTICR[position >> 2] &= ~tmp; /* Clear EXTI line configuration */ @@ -464,7 +464,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32L4 family + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family * @param GPIO_Pin: specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None @@ -479,11 +479,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Apply lock key write sequence */ tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */ GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ GPIOx->LCKR = tmp; /* Read LCKK bit*/ tmp = GPIOx->LCKR; diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_hrtim.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_hrtim.c index 60677a2b33894e0596ac4a05fc2c7c8e48ae3bed..51d9b56e829b7930d3f2d474d8978c050a72485e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_hrtim.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_hrtim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_hrtim.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Resolution Timer (HRTIM) peripheral: @@ -565,8 +565,8 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim) hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE; hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE; hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE; - hhrtim->TimerParam[timer_idx].DMASrcAddress = 0; - hhrtim->TimerParam[timer_idx].DMASize = 0; + hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U; + hhrtim->TimerParam[timer_idx].DMASize = 0U; } return HAL_OK; @@ -746,7 +746,7 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, uint32_t Timeout) { - uint32_t tickstart=0; + uint32_t tickstart=0U; tickstart = HAL_GetTick(); @@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim, { if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hhrtim->State = HAL_HRTIM_STATE_ERROR; return HAL_TIMEOUT; @@ -1046,7 +1046,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim, } if((hhrtim->State == HAL_HRTIM_STATE_READY)) { - if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0)) + if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -1264,7 +1264,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse; CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; + CompareCfg.AutoDelayedTimeout = 0U; HRTIM_CompareUnitConfig(hhrtim, TimerIdx, @@ -1609,7 +1609,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, } if((hhrtim->State == HAL_HRTIM_STATE_READY)) { - if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0)) + if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -1832,7 +1832,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse; CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; + CompareCfg.AutoDelayedTimeout = 0U; HRTIM_CompareUnitConfig(hhrtim, TimerIdx, @@ -2174,7 +2174,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, } if((hhrtim->State == HAL_HRTIM_STATE_READY)) { - if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0)) + if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -2956,7 +2956,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse; CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; - CompareCfg.AutoDelayedTimeout = 0; + CompareCfg.AutoDelayedTimeout = 0U; HRTIM_CompareUnitConfig(hhrtim, TimerIdx, @@ -3508,28 +3508,28 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_2: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); - hrtim_fltinr1 |= (pFaultCfg->Polarity << 8); - hrtim_fltinr1 |= (pFaultCfg->Source << 8); - hrtim_fltinr1 |= (pFaultCfg->Filter << 8); - hrtim_fltinr1 |= (pFaultCfg->Lock << 8); + hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U); + hrtim_fltinr1 |= (pFaultCfg->Source << 8U); + hrtim_fltinr1 |= (pFaultCfg->Filter << 8U); + hrtim_fltinr1 |= (pFaultCfg->Lock << 8U); } break; case HRTIM_FAULT_3: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); - hrtim_fltinr1 |= (pFaultCfg->Polarity << 16); - hrtim_fltinr1 |= (pFaultCfg->Source << 16); - hrtim_fltinr1 |= (pFaultCfg->Filter << 16); - hrtim_fltinr1 |= (pFaultCfg->Lock << 16); + hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U); + hrtim_fltinr1 |= (pFaultCfg->Source << 16U); + hrtim_fltinr1 |= (pFaultCfg->Filter << 16U); + hrtim_fltinr1 |= (pFaultCfg->Lock << 16U); } break; case HRTIM_FAULT_4: { hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); - hrtim_fltinr1 |= (pFaultCfg->Polarity << 24); - hrtim_fltinr1 |= (pFaultCfg->Source << 24); - hrtim_fltinr1 |= (pFaultCfg->Filter << 24); - hrtim_fltinr1 |= (pFaultCfg->Lock << 24); + hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U); + hrtim_fltinr1 |= (pFaultCfg->Source << 24U); + hrtim_fltinr1 |= (pFaultCfg->Filter << 24U); + hrtim_fltinr1 |= (pFaultCfg->Lock << 24U); } break; case HRTIM_FAULT_5: @@ -3643,17 +3643,17 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, if ((Faults & HRTIM_FAULT_2) != RESET) { hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E; - hrtim_fltinr1 |= (Enable << 8); + hrtim_fltinr1 |= (Enable << 8U); } if ((Faults & HRTIM_FAULT_3) != RESET) { hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E; - hrtim_fltinr1 |= (Enable << 16); + hrtim_fltinr1 |= (Enable << 16U); } if ((Faults & HRTIM_FAULT_4) != RESET) { hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E; - hrtim_fltinr1 |= (Enable << 24); + hrtim_fltinr1 |= (Enable << 24U); } if ((Faults & HRTIM_FAULT_5) != RESET) { @@ -3717,7 +3717,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_ADCTRIGGER_2: { hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC); - hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC); + hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC); /* Set the ADC trigger 2 source */ hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger; @@ -3726,7 +3726,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_ADCTRIGGER_3: { hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC); - hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC); + hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC); /* Set the ADC trigger 3 source */ hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger; @@ -3735,7 +3735,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_ADCTRIGGER_4: { hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC); - hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC); + hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC); /* Set the ADC trigger 4 source */ hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger; @@ -3945,8 +3945,8 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { case HRTIM_EVENT_NONE: { - hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0; - hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0; + hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U; + hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U; } break; case HRTIM_EVENT_1: @@ -3961,7 +3961,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1; hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr; } break; @@ -3969,7 +3969,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1; hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr; } break; @@ -3977,7 +3977,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1; hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr; } break; @@ -3985,7 +3985,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1; hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr; } break; @@ -4001,7 +4001,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2; hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr; } break; @@ -4009,7 +4009,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2; hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr; } break; @@ -4017,7 +4017,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2; hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr; } break; @@ -4025,7 +4025,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt { hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2; hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH); - hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); + hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U); hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr; } break; @@ -4094,7 +4094,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_dtr |= pDeadTimeCfg->RisingSign; hrtim_dtr |= pDeadTimeCfg->RisingSignLock; hrtim_dtr |= pDeadTimeCfg->RisingLock; - hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16); + hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U); hrtim_dtr |= pDeadTimeCfg->FallingSign; hrtim_dtr |= pDeadTimeCfg->FallingSignLock; hrtim_dtr |= pDeadTimeCfg->FallingLock; @@ -4398,7 +4398,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, /* DELCMP4 bitfield must be reset when reprogrammed from one value */ /* to the other to reinitialize properly the auto-delayed mechanism */ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4; - hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2); + hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U); /* Set the compare value for timeout compare unit (if any) */ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) @@ -4772,12 +4772,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim: pointer to HAL HRTIM handle * @param Timers: Timer counter(s) to stop * This parameter can be any combination of the following values: - * @arg HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E + * @arg HRTIM_TIMERID_MASTER + * @arg HRTIM_TIMERID_A + * @arg HRTIM_TIMERID_B + * @arg HRTIM_TIMERID_C + * @arg HRTIM_TIMERID_D + * @arg HRTIM_TIMERID_E * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ @@ -4873,12 +4873,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim * @param hhrtim: pointer to HAL HRTIM handle * @param Timers: Timer counter(s) to stop * This parameter can be any combination of the following values: - * @arg HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E + * @arg HRTIM_TIMERID_MASTER + * @arg HRTIM_TIMERID_A + * @arg HRTIM_TIMERID_B + * @arg HRTIM_TIMERID_C + * @arg HRTIM_TIMERID_D + * @arg HRTIM_TIMERID_E * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. @@ -4887,7 +4887,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim, uint32_t Timers) { /* ++ WA */ - __IO uint32_t delai = (uint32_t)(0x17F); + __IO uint32_t delai = (uint32_t)(0x17FU); /* -- WA */ uint8_t timer_idx; @@ -4922,7 +4922,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim, } /* ++ WA */ - do { delai--; } while (delai != 0); + do { delai--; } while (delai != 0U); /* -- WA */ /* Disable timer(s) counter */ @@ -4942,12 +4942,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim: pointer to HAL HRTIM handle * @param Timers: Timer counter(s) to start * This parameter can be any combination of the following values: - * HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E + * HRTIM_TIMERID_MASTER + * @arg HRTIM_TIMERID_A + * @arg HRTIM_TIMERID_B + * @arg HRTIM_TIMERID_C + * @arg HRTIM_TIMERID_D + * @arg HRTIM_TIMERID_E * @retval HAL status * @note This function enables the dma request(s) mentionned in the timer * configuration data structure for every timers to start. @@ -4975,7 +4975,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti __HAL_LOCK(hhrtim); if (((Timers & HRTIM_TIMERID_MASTER) != RESET) && - (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0)) + (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { /* Set the DMA error callback */ hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ; @@ -4999,7 +4999,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5040,12 +5040,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti * @param hhrtim: pointer to HAL HRTIM handle * @param Timers: Timer counter(s) to stop * This parameter can be any combination of the following values: - * @arg HRTIM_TIMER_MASTER - * @arg HRTIM_TIMER_A - * @arg HRTIM_TIMER_B - * @arg HRTIM_TIMER_C - * @arg HRTIM_TIMER_D - * @arg HRTIM_TIMER_E + * @arg HRTIM_TIMERID_MASTER + * @arg HRTIM_TIMERID_A + * @arg HRTIM_TIMERID_B + * @arg HRTIM_TIMERID_C + * @arg HRTIM_TIMERID_D + * @arg HRTIM_TIMERID_E * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related DMA requests are disabled. @@ -5062,7 +5062,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim hhrtim->State = HAL_HRTIM_STATE_BUSY; if (((Timers & HRTIM_TIMERID_MASTER) != RESET) && - (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0)) + (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U)) { /* Disable the DMA */ HAL_DMA_Abort(hhrtim->hdmaMaster); @@ -5077,7 +5077,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim timer_idx++) { if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) && - (hhrtim->TimerParam[timer_idx].DMARequests != 0)) + (hhrtim->TimerParam[timer_idx].DMARequests != 0U)) { /* Get the timer DMA handler */ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx); @@ -5357,7 +5357,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, } if((hhrtim->State == HAL_HRTIM_STATE_READY)) { - if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0)) + if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) { return HAL_ERROR; } @@ -5521,7 +5521,7 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { - uint32_t captured_value = 0; + uint32_t captured_value = 0U; /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -5652,7 +5652,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t output_bit = 0; + uint32_t output_bit = 0U; uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE; /* Check parameters */ @@ -6608,7 +6608,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, /* Master timer registers update handling */ hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA); - hrtim_mcr |= (pTimerCfg->UpdateGating << 2); + hrtim_mcr |= (pTimerCfg->UpdateGating << 2U); /* Enable/Disable registers update on repetition */ hrtim_mcr &= ~(HRTIM_MCR_MREPU); @@ -6731,31 +6731,31 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, case HRTIM_TIMERINDEX_TIMER_A: { hrtim_bmcr &= ~(HRTIM_BMCR_TABM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 1); + hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U); } break; case HRTIM_TIMERINDEX_TIMER_B: { hrtim_bmcr &= ~(HRTIM_BMCR_TBBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 2); + hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U); } break; case HRTIM_TIMERINDEX_TIMER_C: { hrtim_bmcr &= ~(HRTIM_BMCR_TCBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 3); + hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U); } break; case HRTIM_TIMERINDEX_TIMER_D: { hrtim_bmcr &= ~(HRTIM_BMCR_TDBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 4); + hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U); } break; case HRTIM_TIMERINDEX_TIMER_E: { hrtim_bmcr &= ~(HRTIM_BMCR_TEBM); - hrtim_bmcr |= ( pTimerCfg->BurstMode << 5); + hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U); } break; default: @@ -6964,7 +6964,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource; hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource; - shift = 0; + shift = 0U; } break; case HRTIM_OUTPUT_TA2: @@ -6977,7 +6977,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource; hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource; - shift = 16; + shift = 16U; } break; default: @@ -7010,8 +7010,8 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, /* Set the burst mode entry mode : deadtime insertion when entering the idle state during a burst mode operation is allowed only under the following conditions: - - the outputs is active during the burst mode (IDLES=1) - - positive deadtimes (SDTR/SDTF set to 0) + - the outputs is active during the burst mode (IDLES=1U) + - positive deadtimes (SDTR/SDTF set to 0U) */ if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) && ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) && @@ -7062,52 +7062,52 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_EVENT_2: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); - hrtim_eecr1 |= (pEventCfg->Source << 6); - hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL)); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 6); + hrtim_eecr1 |= (pEventCfg->Source << 6U); + hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL)); + hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U); /* Update the HRTIM registers (all bitfields but EE2FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; /* Update the HRTIM registers (EE2FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 6); + hrtim_eecr1 |= (pEventCfg->FastMode << 6U); hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; } break; case HRTIM_EVENT_3: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); - hrtim_eecr1 |= (pEventCfg->Source << 12); - hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL)); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 12); + hrtim_eecr1 |= (pEventCfg->Source << 12U); + hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL)); + hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U); /* Update the HRTIM registers (all bitfields but EE3FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; /* Update the HRTIM registers (EE3FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 12); + hrtim_eecr1 |= (pEventCfg->FastMode << 12U); hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; } break; case HRTIM_EVENT_4: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); - hrtim_eecr1 |= (pEventCfg->Source << 18); - hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL)); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 18); + hrtim_eecr1 |= (pEventCfg->Source << 18U); + hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL)); + hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U); /* Update the HRTIM registers (all bitfields but EE4FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; /* Update the HRTIM registers (EE4FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 18); + hrtim_eecr1 |= (pEventCfg->FastMode << 18U); hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; } break; case HRTIM_EVENT_5: { hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); - hrtim_eecr1 |= (pEventCfg->Source << 24); - hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL)); - hrtim_eecr1 |= (pEventCfg->Sensitivity << 24); + hrtim_eecr1 |= (pEventCfg->Source << 24U); + hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL)); + hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U); /* Update the HRTIM registers (all bitfields but EE5FAST bit) */ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; /* Update the HRTIM registers (EE5FAST bit) */ - hrtim_eecr1 |= (pEventCfg->FastMode << 24); + hrtim_eecr1 |= (pEventCfg->FastMode << 24U); hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1; } break; @@ -7127,11 +7127,11 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_EVENT_7: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); - hrtim_eecr2 |= (pEventCfg->Source << 6); - hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL)); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 6); + hrtim_eecr2 |= (pEventCfg->Source << 6U); + hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL)); + hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U); hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F); - hrtim_eecr3 |= (pEventCfg->Filter << 6); + hrtim_eecr3 |= (pEventCfg->Filter << 6U); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; @@ -7140,11 +7140,11 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_EVENT_8: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); - hrtim_eecr2 |= (pEventCfg->Source << 12); - hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL)); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 12); + hrtim_eecr2 |= (pEventCfg->Source << 12U); + hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL)); + hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U); hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); - hrtim_eecr3 |= (pEventCfg->Filter << 12); + hrtim_eecr3 |= (pEventCfg->Filter << 12U); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; @@ -7153,11 +7153,11 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_EVENT_9: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); - hrtim_eecr2 |= (pEventCfg->Source << 18); - hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL)); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 18); + hrtim_eecr2 |= (pEventCfg->Source << 18U); + hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL)); + hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U); hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F); - hrtim_eecr3 |= (pEventCfg->Filter << 18); + hrtim_eecr3 |= (pEventCfg->Filter << 18U); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; @@ -7166,11 +7166,11 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_EVENT_10: { hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); - hrtim_eecr2 |= (pEventCfg->Source << 24); - hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL)); - hrtim_eecr2 |= (pEventCfg->Sensitivity << 24); + hrtim_eecr2 |= (pEventCfg->Source << 24U); + hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL)); + hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U); hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F); - hrtim_eecr3 |= (pEventCfg->Filter << 24); + hrtim_eecr3 |= (pEventCfg->Filter << 24U); /* Update the HRTIM registers */ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2; hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3; @@ -7274,7 +7274,7 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, { uint32_t hrtim_set; uint32_t hrtim_reset; - uint32_t interrupt = 0; + uint32_t interrupt = 0U; switch (OCChannel) { @@ -7295,12 +7295,12 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, interrupt = HRTIM_TIM_IT_CMP1; } else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && - (hrtim_reset == 0)) + (hrtim_reset == 0U)) { /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET1; } - else if ((hrtim_set == 0) && + else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1)) { /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ @@ -7325,12 +7325,12 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, interrupt = HRTIM_TIM_IT_CMP2; } else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && - (hrtim_reset == 0)) + (hrtim_reset == 0U)) { /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ interrupt = HRTIM_TIM_IT_SET2; } - else if ((hrtim_set == 0) && + else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2)) { /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ @@ -7370,7 +7370,7 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, { uint32_t hrtim_set; uint32_t hrtim_reset; - uint32_t dma_request = 0; + uint32_t dma_request = 0U; switch (OCChannel) { @@ -7391,12 +7391,12 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, dma_request = HRTIM_TIM_DMA_CMP1; } else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) && - (hrtim_reset == 0)) + (hrtim_reset == 0U)) { /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET1; } - else if ((hrtim_set == 0) && + else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1)) { /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ @@ -7421,12 +7421,12 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, dma_request = HRTIM_TIM_DMA_CMP2; } else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) && - (hrtim_reset == 0)) + (hrtim_reset == 0U)) { /* OC mode: HRTIM_BASICOCMODE_ACTIVE */ dma_request = HRTIM_TIM_DMA_SET2; } - else if ((hrtim_set == 0) && + else if ((hrtim_set == 0U) && ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2)) { /* OC mode: HRTIM_BASICOCMODE_INACTIVE */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c.c index f52ec7fac5850f1b7ed750f33e09693da9e427ac..9ec159a18ce2af29e94442ca08a236ccc9746214 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -98,6 +98,9 @@ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases @@ -195,13 +198,13 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -273,7 +276,7 @@ #define SlaveAddr_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ @@ -291,6 +294,9 @@ #define I2C_XFER_ERROR_IT (0x00000011U) #define I2C_XFER_CPLT_IT (0x00000012U) #define I2C_XFER_RELOAD_IT (0x00000012U) + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) /** * @} */ @@ -434,18 +440,17 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Configure I2Cx: Own Address1 and ack own address1 mode */ + /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hi2c->Init.OwnAddress1 != 0U) + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ @@ -458,6 +463,9 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); @@ -518,7 +526,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -534,7 +542,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -635,9 +643,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA return HAL_TIMEOUT; } - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; @@ -718,7 +726,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -759,9 +767,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd return HAL_TIMEOUT; } - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; @@ -843,7 +851,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -881,9 +889,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; @@ -983,7 +991,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1021,9 +1029,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; @@ -1114,7 +1122,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1151,13 +1159,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; @@ -1220,13 +1228,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; @@ -1280,16 +1288,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -1329,16 +1337,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -1387,13 +1395,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; @@ -1495,13 +1503,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; @@ -1597,8 +1605,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ @@ -1663,8 +1671,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Process Locked */ __HAL_LOCK(hi2c); - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ @@ -1848,7 +1856,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2473,8 +2481,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd tickstart = HAL_GetTick(); while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { + if(Timeout != HAL_MAX_DELAY) + { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ @@ -2596,15 +2604,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + xferrequest = I2C_NO_STARTSTOP; + } /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2670,13 +2677,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; + } - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + xferrequest = I2C_NO_STARTSTOP; } /* Send Slave Address and set NBYTES to read */ @@ -2713,7 +2720,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { if((pData == NULL) || (Size == 0U)) { @@ -2726,6 +2733,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + } + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2779,7 +2794,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { if((pData == NULL) || (Size == 0U)) { @@ -2792,6 +2807,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + } + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3007,7 +3030,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -3038,7 +3061,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -3106,7 +3129,7 @@ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -3138,7 +3161,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); @@ -3210,7 +3233,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @retval I2C Error Code +* @retval I2C Error Code */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { @@ -3750,6 +3773,9 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) uint16_t ownadd1code = 0U; uint16_t ownadd2code = 0U; + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + /* In case of Listen state, need to inform upper layer of address match code event */ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { @@ -4321,6 +4347,9 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ @@ -4375,6 +4404,9 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c_ex.c index 616ba82156c9d2bcf7c795fd8a5ac5a11b2a85a4..5d03250bb73db0c63bd90dc3f671888588344479 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: @@ -31,7 +31,7 @@ (++) HAL_I2CEx_DisableWakeUp() (#) Configure the enable or disable of fast mode plus driving capability using the functions : (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisbleFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() @endverbatim ****************************************************************************** * @attention @@ -90,7 +90,7 @@ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -151,7 +151,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t * @brief Configure I2C Digital noise filter. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) @@ -238,7 +238,6 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c) } } - /** * @brief Disable I2C wakeup from stop mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -282,6 +281,15 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) * @brief Enable the I2C fast mode plus driving capability. * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -300,6 +308,15 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) * @brief Disable the I2C fast mode plus driving capability. * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s.c index 26655bb5612374857cfebc325a749ed240ce2097..14690b7e069d016b4546bd223211b5ebe588a682 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -366,8 +366,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -388,7 +388,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin __HAL_I2S_ENABLE(hi2s); } - while(hi2s->TxXferCount > 0) + while(hi2s->TxXferCount > 0U) { hi2s->Instance->DR = (*pData++); hi2s->TxXferCount--; @@ -449,7 +449,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin */ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -459,8 +459,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -489,7 +489,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint } /* Receive data */ - while(hi2s->RxXferCount > 0) + while(hi2s->RxXferCount > 0U) { /* Wait until RXNE flag is set */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) @@ -551,7 +551,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, { if(hi2s->State == HAL_I2S_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -560,8 +560,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -616,7 +616,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u { if(hi2s->State == HAL_I2S_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -625,8 +625,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, { uint32_t *tmp; - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -689,8 +689,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { @@ -756,7 +756,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, { uint32_t *tmp; - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -767,8 +767,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -874,7 +874,7 @@ __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) } /* If the I2S peripheral is still not enabled, enable it */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); @@ -1141,12 +1141,12 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable Tx DMA Request */ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - hi2s->TxXferCount = 0; + hi2s->TxXferCount = 0U; hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_TxCpltCallback(hi2s); @@ -1175,11 +1175,11 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable Rx DMA Request */ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0; + hi2s->RxXferCount = 0U; hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_RxCpltCallback(hi2s); @@ -1210,8 +1210,8 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /* Disable Rx and Tx DMA Request */ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; hi2s->State= HAL_I2S_STATE_READY; @@ -1232,7 +1232,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1253,7 +1253,7 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; hi2s->RxXferCount--; - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1283,7 +1283,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1302,7 +1302,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s_ex.c index a3f09c8d23c7218fcb0c773fd7dff4afdc7b474b..a6c02d15aabfdbd865394b43a99c23712adb8a55 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_i2s_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_i2s_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief I2S Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S Extended peripheral: @@ -19,7 +19,21 @@ called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3). (#) The Extended block is not a full SPI IP, it is used only as I2S slave to implement full duplex mode. The Extended block uses the same clock sources - as its master. + as its master (refer to the following Figure). + + +-----------------------+ + I2Sx_SCK | | + ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) + +--|-->| | + | | +-----------------------+ + | | + I2S_WS | | + ------>| | + | | +-----------------------+ + | +-->| | + | | I2Sx_ext |------------------->I2Sx_extSD(in/out) + +----->| | + +-----------------------+ (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. @@ -101,26 +115,6 @@ ****************************************************************************** */ -/* - Additional Figure: The Extended block uses the same clock sources as its master. - (refer to the following Figure). - - +-----------------------+ - I2Sx_SCK | | - ----------+-->| I2Sx |------------------->I2Sx_SD(in/out) - +--|-->| | - | | +-----------------------+ - | | - I2S_WS | | - ------>| | - | | +-----------------------+ - | +-->| | - | | I2Sx_ext |------------------->I2Sx_extSD(in/out) - +----->| | - +-----------------------+ - -*/ - /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" @@ -148,7 +142,7 @@ */ typedef enum { - I2S_USE_I2S = 0x00, /*!< I2Sx should be used */ + I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */ I2S_USE_I2SEXT = 0x01 /*!< I2Sx_ext should be used */ }I2S_UseTypeDef; /** @@ -223,8 +217,8 @@ static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeD */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) { - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; + uint16_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + uint32_t tmp = 0U, i2sclk = 0U; #if defined(SPI_I2S_FULLDUPLEX_SUPPORT) RCC_PeriphCLKInitTypeDef rccperiphclkinit; #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ @@ -256,7 +250,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); - hi2s->Instance->I2SPR = 0x0002; + hi2s->Instance->I2SPR = 0x0002U; /* Get the I2SCFGR register value */ tmpreg = hi2s->Instance->I2SCFGR; @@ -264,8 +258,8 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; + i2sodd = (uint16_t)0U; + i2sdiv = (uint16_t)2U; } /* If the requested audio frequency is not the default, compute the prescaler */ else @@ -274,12 +268,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) { /* Packet length is 16 bits */ - packetlength = 1; + packetlength = 1U; } else { /* Packet length is 32 bits */ - packetlength = 2; + packetlength = 2U; } /* Get I2S source Clock frequency ****************************************/ @@ -323,33 +317,33 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) { /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); + tmp = (uint16_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U); } else { /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); + tmp = (uint16_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U); } /* Remove the flatting point */ - tmp = tmp / 10; + tmp = tmp / 10U; /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); + i2sodd = (uint16_t) (i2sodd << 8U); } - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if((i2sdiv < 2) || (i2sdiv > 0xFF)) + /* Test if the divider is 1 or 0 or greater than 0xFFU */ + if((i2sdiv < 2U) || (i2sdiv > 0xFFU)) { /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; + i2sdiv = 2U; + i2sodd = 0U; } /* Write to SPIx I2SPR register the computed value */ @@ -370,7 +364,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); - I2SxEXT(hi2s->Instance)->I2SPR = 0x0002; + I2SxEXT(hi2s->Instance)->I2SPR = 0x0002U; /* Get the I2SCFGR register value */ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; @@ -629,7 +623,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN); /* If the I2Sext peripheral is still not enabled, enable it */ - if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) { /* Enable I2Sext peripheral */ __HAL_I2SEXT_ENABLE(hi2s); @@ -638,7 +632,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ /* If the I2S peripheral is still not enabled, enable it */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); @@ -781,7 +775,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -796,10 +790,10 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -838,7 +832,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p __HAL_I2S_ENABLE(hi2s); } - while(hi2s->RxXferCount > 0) + while(hi2s->RxXferCount > 0U) { /* Wait until TXE flag is set */ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK) @@ -849,7 +843,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p return HAL_TIMEOUT; } - if (hi2s->TxXferCount > 0) + if (hi2s->TxXferCount > 0U) { /* Check if an underrun occurs */ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) @@ -925,7 +919,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p __HAL_I2S_CLEAR_OVRFLAG(hi2s); } - while(hi2s->RxXferCount > 0) + while(hi2s->RxXferCount > 0U) { /* Wait until TXE flag is set */ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK) @@ -936,7 +930,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p return HAL_TIMEOUT; } - if (hi2s->TxXferCount > 0) + if (hi2s->TxXferCount > 0U) { /* Check if an underrun occurs */ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) @@ -1020,7 +1014,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t { if(hi2s->State == HAL_I2S_STATE_READY) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -1035,10 +1029,10 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -1069,18 +1063,18 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) { /* Prepare the First Data before enabling the I2S */ - if(hi2s->TxXferCount != 0) + if(hi2s->TxXferCount != 0U) { /* Transmit First data */ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable I2Sext RXNE and ERR interrupt */ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR)); @@ -1111,18 +1105,18 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Prepare the First Data before enabling the I2S */ - if(hi2s->TxXferCount != 0) + if(hi2s->TxXferCount != 0U) { /* Transmit First data */ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable I2Sext TXE and ERR interrupt */ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR)); @@ -1168,7 +1162,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ { uint32_t *tmp; - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -1185,10 +1179,10 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { @@ -1322,9 +1316,9 @@ static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma) hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); } - hi2s->RxXferCount = 0; + hi2s->RxXferCount = 0U; - if (hi2s->TxXferCount == 0) + if (hi2s->TxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; @@ -1344,9 +1338,9 @@ static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma) I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); } - hi2s->TxXferCount = 0; + hi2s->TxXferCount = 0U; - if (hi2s->RxXferCount == 0) + if (hi2s->RxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; @@ -1368,8 +1362,8 @@ static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma) hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; hi2s->State= HAL_I2S_STATE_READY; @@ -1392,12 +1386,12 @@ static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; HAL_I2S_TxRxCpltCallback(hi2s); @@ -1410,12 +1404,12 @@ static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { /* Disable I2Sext TXE and ERR interrupt */ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; HAL_I2S_TxRxCpltCallback(hi2s); @@ -1438,12 +1432,12 @@ static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; hi2s->RxXferCount--; - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; HAL_I2S_TxRxCpltCallback(hi2s); @@ -1456,12 +1450,12 @@ static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed) (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; hi2s->RxXferCount--; - if(hi2s->RxXferCount == 0) + if(hi2s->RxXferCount == 0U) { /* Disable I2Sext RXNE and ERR interrupt */ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - if(hi2s->TxXferCount == 0) + if(hi2s->TxXferCount == 0U) { hi2s->State = HAL_I2S_STATE_READY; HAL_I2S_TxRxCpltCallback(hi2s); @@ -1493,7 +1487,7 @@ static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeD { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1513,7 +1507,7 @@ static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeD { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1536,7 +1530,7 @@ static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeD { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; @@ -1556,7 +1550,7 @@ static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeD { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_irda.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_irda.c index 62cc7ffb88f008ca8a271ce77d20c73a10a9ee68..cc5036225bc3504aabcb02d2aec78545e6e9f265 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_irda.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_irda.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -51,6 +51,10 @@ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_IRDA_MspInit() API. + -@@- The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** @@ -137,8 +141,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" -#ifdef HAL_IRDA_MODULE_ENABLED - /** @addtogroup STM32F3xx_HAL_Driver * @{ */ @@ -148,14 +150,14 @@ * @{ */ +#ifdef HAL_IRDA_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ -#define IRDA_TXDMA_TIMEOUTVALUE 22000 -#define IRDA_TIMEOUT_VALUE 22000 +#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ /** @@ -165,20 +167,27 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup IRDA_Private_Functions IRDA Private Functions +/** @addtogroup IRDA_Private_Functions * @{ */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} */ @@ -253,9 +262,9 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, */ /** - * @brief Initialize the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -293,8 +302,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - SCEN and HDSEL bits in the USART_CR3 register.*/ - hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); - hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); + CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ hirda->Instance->CR3 |= USART_CR3_IREN; @@ -307,8 +316,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -331,8 +340,8 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) __HAL_IRDA_DISABLE(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_RESET; - hirda->RxState = HAL_IRDA_STATE_RESET; + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hirda); @@ -341,12 +350,12 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) } /** - * @brief Initialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Initialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -357,12 +366,12 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) } /** - * @brief DeInitialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DeInitialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); @@ -380,9 +389,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * @brief IRDA Transmit and Receive functions * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== + =============================================================================== + ##### IO operation functions ##### + =============================================================================== [..] This subsection provides a set of functions allowing to manage the IRDA data transfers. @@ -393,11 +402,11 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. - (#) There are two modes of transfer: + (#) There are two mode of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) No-Blocking mode: the communication is performed using Interrupts + (++) Non-Blocking mode: the communication is performed using Interrupts or DMA, these API's return the HAL status. The end of the data processing will be indicated through the dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when @@ -429,27 +438,52 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) (++) HAL_IRDA_RxCpltCallback() (++) HAL_IRDA_ErrorCallback() + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + @endverbatim * @{ */ /** * @brief Send an amount of data in blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Specify timeout value. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; + uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -458,32 +492,34 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + hirda->TxXferSize = Size; hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + while(hirda->TxXferCount > 0U) { hirda->TxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData +=2; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData += 2U; } else { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -504,22 +540,23 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be received. - * @param Timeout: Specify timeout value. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @param Timeout Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; /* Check that a Rx process is not already ongoing */ if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -528,23 +565,25 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + hirda->RxXferSize = Size; hirda->RxXferCount = Size; - /* Computation of the mask to apply to the RDR register + /* Computation of the mask to apply to RDR register of the UART associated to the IRDA */ IRDA_MASK_COMPUTATION(hirda); uhMask = hirda->Mask; /* Check data remaining to be received */ - while(hirda->RxXferCount > 0) + while(hirda->RxXferCount > 0U) { hirda->RxXferCount--; - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -552,7 +591,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { @@ -576,10 +615,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -587,7 +626,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Check that a Tx process is not already ongoing */ if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -600,14 +639,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->TxXferCount = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(hirda); /* Enable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); + SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -619,10 +657,10 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be received. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -630,13 +668,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Check that a Rx process is not already ongoing */ if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ - __HAL_LOCK(hirda); + __HAL_LOCK(hirda); hirda->pRxBuffPtr = pData; hirda->RxXferSize = Size; @@ -647,20 +685,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, IRDA_MASK_COMPUTATION(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Data Register not empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); - - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); return HAL_OK; } @@ -672,23 +706,21 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance)); /* Check that a Tx process is not already ongoing */ if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -701,7 +733,6 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->TxXferCount = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Set the IRDA DMA transfer complete callback */ @@ -713,20 +744,22 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /* Set the DMA error callback */ hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + /* Set the DMA abort callback */ + hirda->hdmatx->XferAbortCallback = NULL; + /* Enable the IRDA transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); + HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size); /* Clear the TC flag in the ICR register */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - hirda->Instance->CR3 |= USART_CR3_DMAT; - /* Process Unlocked */ __HAL_UNLOCK(hirda); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else @@ -737,25 +770,23 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be received. - * @note When the IRDA parity is enabled (PCE = 1) the received data contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be received. + * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance)); /* Check that a Rx process is not already ongoing */ if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -767,7 +798,6 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->RxXferSize = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; /* Set the IRDA DMA transfer complete callback */ @@ -779,16 +809,24 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Set the DMA error callback */ hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + /* Set the DMA abort callback */ + hirda->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); + HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ - hirda->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -800,9 +838,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /** - * @brief Pause the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @brief Pause the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) @@ -810,13 +848,19 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) + if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) { /* Disable the IRDA DMA Tx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Disable the IRDA DMA Rx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } @@ -828,9 +872,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) } /** - * @brief Resume the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * @brief Resume the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) @@ -847,6 +891,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) { /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Enable the IRDA DMA Rx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } @@ -858,9 +907,9 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) } /** - * @brief Stop the DMA Transfer. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * @brief Stop the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) @@ -868,144 +917,644 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) /* The Lock is not implemented on this API to allow the user application to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback(): - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is - generated if the DMA transfer interruption occurs at the middle or at the end of the stream - and the corresponding call back is executed. - */ + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ - /* Disable the IRDA Tx/Rx DMA requests */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Stop IRDA DMA Tx request if ongoing */ + if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - /* Abort the IRDA DMA tx channel */ - if(hirda->hdmatx != NULL) + /* Abort the IRDA DMA Tx channel */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + + IRDA_EndTxTransfer(hirda); + } + + /* Stop IRDA DMA Rx request if ongoing */ + if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) { - HAL_DMA_Abort(hirda->hdmatx); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + + IRDA_EndRxTransfer(hirda); } - /* Abort the IRDA DMA rx channel */ - if(hirda->hdmarx != NULL) + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmatx); + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { - HAL_DMA_Abort(hirda->hdmarx); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmarx); + } } - hirda->gState = HAL_IRDA_STATE_READY; + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; hirda->RxState = HAL_IRDA_STATE_READY; + /* Reset Handle ErrorCode to No Error */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmatx); + } + } + + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + return HAL_OK; } +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmarx); + } + } + + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} /** - * @brief Handle IRDA interrupt request. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) + * @brief Abort ongoing transfers (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { - /* IRDA parity error interrupt occurred -------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(hirda->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; + } + else + { + hirda->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(hirda->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; + } + else + { + hirda->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the IRDA DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - /* Set the IRDA Rx state ready to be able to start again the process */ - hirda->RxState = HAL_IRDA_STATE_READY; + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmatx != NULL) + { + /* IRDA Tx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + hirda->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } } - /* IRDA frame error interrupt occurred --------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - /* Set the IRDA Rx state ready to be able to start again the process */ - hirda->RxState = HAL_IRDA_STATE_READY; + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmarx != NULL) + { + /* IRDA Rx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + hirda->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } } - /* IRDA noise error interrupt occurred --------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - /* Set the IRDA Rx state ready to be able to start again the process */ + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); } - /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - /* Set the IRDA Rx state ready to be able to start again the process */ - hirda->RxState = HAL_IRDA_STATE_READY; + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ + hirda->hdmatx->XferAbortCallback(hirda->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); } - /* Call IRDA Error Call back function if need be --------------------------*/ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); + } + } + else { - HAL_IRDA_ErrorCallback(hirda); + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); } - /* IRDA in mode Receiver ---------------------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET)) + return HAL_OK; +} + +/** + * @brief Handle IRDA interrupt request. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + uint32_t isrflags = READ_REG(hirda->Instance->ISR); + uint32_t cr1its = READ_REG(hirda->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) { - IRDA_Receive_IT(hirda); + /* IRDA in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + return; + } } + /* If some errors occur */ + cr3its = READ_REG(hirda->Instance->CR3); + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + { + /* IRDA parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + /* IRDA frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + /* IRDA noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + + /* Call IRDA Error Call back function if need be --------------------------*/ + if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the IRDA state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + IRDA_EndRxTransfer(hirda); + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_IRDA_ErrorCallback(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ /* IRDA in mode Transmitter ------------------------------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { IRDA_Transmit_IT(hirda); + return; } /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { IRDA_EndTransmit_IT(hirda); + return; } } /** * @brief Tx Transfer completed callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file. */ } /** * @brief Tx Half Transfer completed callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified USART module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. */ } /** * @brief Rx Transfer completed callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) @@ -1013,8 +1562,8 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_RxCpltCallback can be implemented in the user file. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file. */ } @@ -1036,17 +1585,65 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief IRDA error callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Receive Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. */ } @@ -1059,7 +1656,7 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) * @verbatim ============================================================================== - ##### Peripheral State and Errors functions ##### + ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to return the State of IrDA @@ -1075,14 +1672,14 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Return the IRDA handle state. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = hirda->gState; temp2 = hirda->RxState; @@ -1091,8 +1688,8 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) /** * @brief Return the IRDA handle error code. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) @@ -1108,20 +1705,19 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) * @} */ -/** @addtogroup IRDA_Private_Functions IRDA Private Functions +/** @defgroup IRDA_Private_Functions IRDA Private Functions * @{ */ - /** - * @brief Configure the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Configure the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @retval None + * @retval HAL status */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; @@ -1153,19 +1749,19 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_PCLK2: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); + hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate); break; case IRDA_CLOCKSOURCE_UNDEFINED: default: @@ -1177,17 +1773,21 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) } /** - * @brief Check the IRDA Idle State. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief Check the IRDA Idle State. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) { + uint32_t tickstart = 0U; /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* TEACK bits in ISR is checked only when available. Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature. */ @@ -1197,7 +1797,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -1208,7 +1808,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Check if the Receiver is enabled */ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + /* Wait until REACK flag is set */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout Occured */ return HAL_TIMEOUT; @@ -1216,8 +1817,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) } /* Initialize the IRDA state*/ - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1227,111 +1828,114 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /** * @brief Handle IRDA Communication Timeout. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param Flag: specifies the IRDA flag to check. - * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. - * @param Timeout: Timeout duration + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param Flag Specifies the IRDA flag to check. + * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hirda); + /* Process Unlocked */ + __HAL_UNLOCK(hirda); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } - else - { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; +} - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; } + /** * @brief DMA IRDA transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - hirda->TxXferCount = 0; + hirda->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the IRDA CR3 register */ - hirda->Instance->CR3 &= ~(USART_CR3_DMAT); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else { HAL_IRDA_TxCpltCallback(hirda); } + } /** - * @brief DMA IRDA transmit process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA IRDA transmit process half complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); HAL_IRDA_TxHalfCpltCallback(hirda); } @@ -1344,16 +1948,20 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the IRDA CR3 register */ - hirda->Instance->CR3 &= ~(USART_CR3_DMAR); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore hirda->RxState to Ready */ hirda->RxState = HAL_IRDA_STATE_READY; @@ -1370,37 +1978,191 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); HAL_IRDA_RxHalfCpltCallback(hirda); } /** - * @brief DMA IRDA communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA IRDA communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + + /* Stop IRDA DMA Tx request if ongoing */ + if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } + + /* Stop IRDA DMA Rx request if ongoing */ + if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - hirda->gState= HAL_IRDA_STATE_READY; - hirda->RxState= HAL_IRDA_STATE_READY; + HAL_IRDA_ErrorCallback(hirda); +} + +/** + * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; HAL_IRDA_ErrorCallback(hirda); } +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); + + hirda->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hirda->hdmarx != NULL) + { + if(hirda->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +} + + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); + + hirda->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hirda->hdmatx != NULL) + { + if(hirda->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +} + + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); + + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +} + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +} /** - * @brief Send an amount of data in non-blocking mode. + * @brief Send an amount of data in interrupt mode. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_IRDA_Transmit_IT(). - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) @@ -1410,13 +2172,13 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /* Check that a Tx process is ongoing */ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { - if(hirda->TxXferCount == 0) + if(hirda->TxXferCount == 0U) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); return HAL_OK; } @@ -1425,12 +2187,12 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + hirda->pTxBuffPtr += 2U; } else { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU); } hirda->TxXferCount--; @@ -1445,14 +2207,14 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) /** * @brief Wrap up transmission in non-blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore hirda->gState to Ready */ hirda->gState = HAL_IRDA_STATE_READY; @@ -1462,44 +2224,42 @@ static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) return HAL_OK; } - /** - * @brief Receive an amount of data in non-blocking mode. - * Function is called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Receive_IT(). - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @brief Receive an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Receive_IT() + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { uint16_t* tmp; - uint16_t uhMask = hirda->Mask; + uint16_t uhMask = hirda->Mask; + uint16_t uhdata; /* Check that a Rx process is ongoing */ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - + uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) hirda->pRxBuffPtr ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - hirda->pRxBuffPtr +=2; + *tmp = (uint16_t)(uhdata & uhMask); + hirda->pRxBuffPtr +=2U; } else { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); } - if(--hirda->RxXferCount == 0) + if(--hirda->RxXferCount == 0U) { - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore hirda->RxState to Ready */ hirda->RxState = HAL_IRDA_STATE_READY; @@ -1524,6 +2284,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) * @} */ +#endif /* HAL_IRDA_MODULE_ENABLED */ /** * @} */ @@ -1532,6 +2293,4 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) * @} */ -#endif /* HAL_IRDA_MODULE_ENABLED */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_iwdg.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_iwdg.c index 2833e5782d095dbfdc6ee6b480570b65036c88f4..324128812f7e7b02e7a67b7656064301dfeafc9f 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_iwdg.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_iwdg.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -22,8 +22,8 @@ if the main clock fails. (+) Once the IWDG is started, the LSI is forced ON and both can not be - disabled. The counter starts counting down from the reset value (0xFFF). - When it reaches the end of count value (0x000) a reset signal is + disabled. The counter starts counting down from the reset value (0xFFFU). + When it reaches the end of count value (0x000U) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, @@ -41,7 +41,7 @@ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s - The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx + The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx devices provide the capability to measure the LSI frequency (LSI clock connected internally to TIM16 CH1 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. @@ -127,7 +127,7 @@ * @{ */ /* Status register need 5 RC LSI divided by prescaler clock to be updated. With - higher prescaler (256), and according to HSI variation, we need to wait at + higher prescaler (256U), and according to HSI variation, we need to wait at least 6 cycles so 48 ms. */ #define HAL_IWDG_DEFAULT_TIMEOUT 48u /** diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_msp_template.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_msp_template.c index d58771c8c10f2b624578f550ae6278b28c5b5980..1e24277066906532ad6aa28c01d35398ad0b242e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_msp_template.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_msp_template.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_msp_template.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nand.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nand.c index 026502b824c9f5b44dd7261cbd96bd89d08e2c87..d6b733ccdadc2029c022209609aa1a3d50aac57c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nand.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nand.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -340,8 +340,8 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { - __IO uint32_t data = 0; - uint32_t deviceaddress = 0; + __IO uint32_t data = 0U; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -444,10 +444,10 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) { - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; + __IO uint32_t index = 0U; + uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + uint32_t addressoffset = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -477,7 +477,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType nandaddress.Zone = pAddress->Zone; /* Page(s) read loop */ - while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) + while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr >= 1024U) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } @@ -538,11 +538,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType */ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) { - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + uint32_t addressoffset = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -572,7 +572,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp nandaddress.Zone = pAddress->Zone; /* Page(s) write loop */ - while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) + while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); @@ -590,7 +590,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr >= 1024U) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } @@ -645,10 +645,10 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; + __IO uint32_t index = 0U; + uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + uint32_t addressoffset = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -678,7 +678,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres nandaddress.Zone = pAddress->Zone; /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) + while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); @@ -695,7 +695,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr >= 1024U) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } @@ -738,11 +738,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + uint32_t addressoffset = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -772,7 +772,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre nandaddress.Zone = pAddress->Zone; /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) + while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); @@ -790,7 +790,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr >= 1024U) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } @@ -843,8 +843,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t deviceaddress = 0; - uint32_t tickstart = 0; + uint32_t deviceaddress = 0U; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + if(hnand->Info.BlockNbr >= 1024U) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); } @@ -915,8 +915,8 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy */ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { - uint32_t data = 0; - uint32_t deviceaddress = 0; + uint32_t data = 0U; + uint32_t deviceaddress = 0U; /* Identify the device address */ if(hnand->Init.NandBank == FMC_NAND_BANK2) @@ -966,12 +966,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA /* Check NAND address is valid */ if(pAddress->Page == hnand->Info.BlockSize) { - pAddress->Page = 0; + pAddress->Page = 0U; pAddress->Block++; if(pAddress->Block == hnand->Info.ZoneSize) { - pAddress->Block = 0; + pAddress->Block = 0U; pAddress->Zone++; if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) @@ -1145,12 +1145,12 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp if(Address->Page == hnand->Info.BlockSize) { - Address->Page = 0; + Address->Page = 0U; Address->Block++; if(Address->Block == hnand->Info.ZoneSize) { - Address->Block = 0; + Address->Block = 0U; Address->Zone++; if(Address->Zone == hnand->Info.BlockNbr) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nor.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nor.c index e449cc776ecf1aba5d8b5f62d72fbee5e2869a93..7fd7f53585a3a773875628d44eaea37f48bf077b 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nor.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_nor.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -330,7 +330,7 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -390,7 +390,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -440,7 +440,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -499,7 +499,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -560,7 +560,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -598,10 +598,10 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); /* Read buffer */ - while( uwBufferSize > 0) + while( uwBufferSize > 0U) { *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2; + uwAddress += 2U; uwBufferSize--; } @@ -632,7 +632,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr { uint16_t * p_currentaddress = (uint16_t *)NULL; uint16_t * p_endaddress = (uint16_t *)NULL; - uint32_t lastloadedaddress = 0, deviceaddress = 0; + uint32_t lastloadedaddress = 0U, deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -666,7 +666,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Initialize variables */ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); - p_endaddress = p_currentaddress + (uwBufferSize-1); + p_endaddress = p_currentaddress + (uwBufferSize-1U); lastloadedaddress = (uint32_t)(uwAddress); /* Issue unlock command sequence */ @@ -675,7 +675,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Write Buffer Load Command */ NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); + NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U)); /* Load Data into NOR Buffer */ while(p_currentaddress <= p_endaddress) @@ -710,7 +710,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -769,7 +769,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -827,7 +827,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -987,8 +987,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmp_sr1 = 0, tmp_sr2 = 0; - uint32_t tickstart = 0; + uint16_t tmp_sr1 = 0U, tmp_sr2 = 0U; + uint32_t tickstart = 0U; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); @@ -1000,7 +1000,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { status = HAL_NOR_STATUS_TIMEOUT; } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp.c index 276e0b98e78c9038406b9fc3c3dc1ec88f137471..68a2c4569e76ab57b0c40dc1afbc1522223696af 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief OPAMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) @@ -37,7 +37,7 @@ handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll (++) HAL_OPAMP_SelfCalibrate: (++) Runs automatically the calibration in 2 steps. - (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors). + (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors). (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is appropriate and enough in most cases). (++) Enables the user trimming mode @@ -71,7 +71,7 @@ (Resistor feedback output) (++) The OPAMP(s) output(s) can be internally connected to resistor feedback output. - (++) OPAMP gain is either 2, 4, 8 or 16. + (++) OPAMP gain is either 2U, 4U, 8 or 16. ##### How to use this driver ##### @@ -170,14 +170,14 @@ |-----------------|--------|--------|--------|--------|--------| | | No conn| X | X | X | X | | Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 | - | (1) | VM1 | PA3 | PA5 | PB2 | PD8 | + | (1U) | VM1 | PA3 | PA5 | PB2 | PD8 | |-----------------|--------|--------|--------|--------|--------| | | VP0 | PA1 | PA7 | PB0 | PB13 | | Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 | | Input | VP2 | PA3 | PB0 | PA1 | PA4 | | | VP3 | PA5 | PB14 | PA5 | PB11 | +--------------------------------------------------------------+ - (1): NA in follower mode. + (1U): NA in follower mode. Table 2. OPAMPs outputs for the STM32F3 devices: +--------------------------------------------------------------+ @@ -213,7 +213,7 @@ * @{ */ /* CSR register reset value */ -#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000) +#define OPAMP_CSR_RESET_VALUE (0x00000000U) /** * @} */ @@ -570,8 +570,8 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) HAL_StatusTypeDef status = HAL_OK; - uint32_t trimmingvaluen = 0; - uint32_t trimmingvaluep = 0; + uint32_t trimmingvaluen = 0U; + uint32_t trimmingvaluep = 0U; uint32_t delta; /* Check the OPAMP handle allocation */ @@ -600,7 +600,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON); /* 1st calibration - N */ - /* Select 90% VREF */ + /* Select 90U% VREF */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); /* Enable the selected opamp */ @@ -608,10 +608,10 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* Init trimming counter */ /* Medium value */ - trimmingvaluen = 16; - delta = 8; + trimmingvaluen = 16U; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -632,7 +632,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) trimmingvaluen -= delta; } - delta >>= 1; + delta >>= 1U; } /* Still need to check if righ calibration is current value or un step below */ @@ -642,7 +642,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ - HAL_Delay(2); + HAL_Delay(2U); if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -653,15 +653,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) } /* 2nd calibration - P */ - /* Select 10% VREF */ + /* Select 10U% VREF */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); /* Init trimming counter */ /* Medium value */ - trimmingvaluep = 16; - delta = 8; + trimmingvaluep = 16U; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -681,18 +681,18 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) trimmingvaluep -= delta; } - delta >>= 1; + delta >>= 1U; } /* Still need to check if righ calibration is current value or un step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */ /* Set candidate trimming */ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -842,8 +842,8 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset) { - uint32_t oldusertrimming = 0; - OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0, oldtrimmingvaluen = 0, trimmingvalue = 0; + uint32_t oldusertrimming = 0U; + OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0U, oldtrimmingvaluen = 0U, trimmingvalue = 0U; /* Check the OPAMP handle allocation */ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp_ex.c index 5ae6c7889a566b9eae47e00f627b4ed86240e9a5..098954d47f33d363258dd0947ffa2a6871a14cfd 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_opamp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended OPAMP HAL module driver. * * This file provides firmware functions to manage the following @@ -105,10 +105,10 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { HAL_StatusTypeDef status = HAL_OK; - uint32_t trimmingvaluen1 = 0; - uint32_t trimmingvaluep1 = 0; - uint32_t trimmingvaluen2 = 0; - uint32_t trimmingvaluep2 = 0; + uint32_t trimmingvaluen1 = 0U; + uint32_t trimmingvaluep1 = 0U; + uint32_t trimmingvaluen2 = 0U; + uint32_t trimmingvaluep2 = 0U; uint32_t delta; @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON); /* 1st calibration - N */ - /* Select 90% VREF */ + /* Select 90U% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); @@ -151,11 +151,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Init trimming counter */ /* Medium value */ - trimmingvaluen1 = 16; - trimmingvaluen2 = 16; - delta = 8; + trimmingvaluen1 = 16U; + trimmingvaluen2 = 16U; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR & OPAMP_CSR_OUTCAL) { @@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluen2 -= delta; } - delta >>= 1; + delta >>= 1U; } // Still need to check if righ calibration is current value or un step below @@ -199,7 +199,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ - HAL_Delay(2); + HAL_Delay(2U); if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) { @@ -218,17 +218,17 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA } /* 2nd calibration - P */ - /* Select 10% VREF */ + /* Select 10U% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); /* Init trimming counter */ /* Medium value */ - trimmingvaluep1 = 16; - trimmingvaluep2 = 16; - delta = 8; + trimmingvaluep1 = 16U; + trimmingvaluep2 = 16U; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR & OPAMP_CSR_OUTCAL) { @@ -259,7 +259,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluep2 -= delta; } - delta >>= 1; + delta >>= 1U; } // Still need to check if righ calibration is current value or un step below @@ -271,7 +271,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ /* Offset trim time: during calibration, minimum time needed between */ /* two steps to have 1 mV accuracy */ - HAL_Delay(2); + HAL_Delay(2U); if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) { @@ -362,14 +362,14 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { HAL_StatusTypeDef status = HAL_OK; - uint32_t trimmingvaluen1 = 0; - uint32_t trimmingvaluep1 = 0; - uint32_t trimmingvaluen2 = 0; - uint32_t trimmingvaluep2 = 0; - uint32_t trimmingvaluen3 = 0; - uint32_t trimmingvaluep3 = 0; - uint32_t trimmingvaluen4 = 0; - uint32_t trimmingvaluep4 = 0; + uint32_t trimmingvaluen1 = 0U; + uint32_t trimmingvaluep1 = 0U; + uint32_t trimmingvaluen2 = 0U; + uint32_t trimmingvaluep2 = 0U; + uint32_t trimmingvaluen3 = 0U; + uint32_t trimmingvaluep3 = 0U; + uint32_t trimmingvaluen4 = 0U; + uint32_t trimmingvaluep4 = 0U; uint32_t delta; @@ -413,7 +413,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON); /* 1st calibration - N */ - /* Select 90% VREF */ + /* Select 90U% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); @@ -427,13 +427,13 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Init trimming counter */ /* Medium value */ - trimmingvaluen1 = 16; - trimmingvaluen2 = 16; - trimmingvaluen3 = 16; - trimmingvaluen4 = 16; - delta = 8; + trimmingvaluen1 = 16U; + trimmingvaluen2 = 16U; + trimmingvaluen3 = 16U; + trimmingvaluen4 = 16U; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -490,11 +490,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluen4 -= delta; } - delta >>= 1; + delta >>= 1U; } /* Still need to check if righ calibration is current value or un step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -538,7 +538,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA } /* 2nd calibration - P */ - /* Select 10% VREF */ + /* Select 10U% VREF */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); @@ -546,14 +546,14 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Init trimming counter */ /* Medium value */ - trimmingvaluep1 = 16; - trimmingvaluep2 = 16; - trimmingvaluep3 = 16; - trimmingvaluep4 = 16; + trimmingvaluep1 = 16U; + trimmingvaluep2 = 16U; + trimmingvaluep3 = 16U; + trimmingvaluep4 = 16U; - delta = 8; + delta = 8U; - while (delta != 0) + while (delta != 0U) { /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { @@ -606,11 +606,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluep4 -= delta; } - delta >>= 1; + delta >>= 1U; } /* Still need to check if righ calibration is current value or un step below */ - /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */ + /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */ /* Set candidate trimming */ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET) { diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pccard.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pccard.c index 7d9c5fb64583e8a74cca9c83bd091b1188f97853..7acb7f32de4c865a4ded0f2494f2fc23881d3c68 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pccard.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pccard.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. @@ -95,9 +95,9 @@ * @{ */ -#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF -#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF -#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000 +#define PCCARD_TIMEOUT_READ_ID 0x0000FFFF +#define PCCARD_TIMEOUT_SECTOR 0x0000FFFF +#define PCCARD_TIMEOUT_STATUS 0x01000000 #define PCCARD_STATUS_OK (uint8_t)0x58 #define PCCARD_STATUS_WRITE_OK (uint8_t)0x50 @@ -264,8 +264,8 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) */ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -294,14 +294,14 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } else { /* Read CF ID bytes */ - for(index = 0; index < 16; index++) + for(index = 0U; index < 16U; index++) { CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA); } @@ -327,8 +327,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp */ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -352,17 +352,17 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t do { - /* wait till the Status = 0x80 */ + /* wait till the Status = 0x80U */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status == 0x80) && timeout); + }while((status == 0x80U) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - timeout = 0xFFFF; + timeout = 0xFFFFU; do { @@ -371,7 +371,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -403,8 +403,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t */ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -433,7 +433,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -451,7 +451,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ timeout--; }while((status != PCCARD_STATUS_WRITE_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -476,8 +476,8 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ */ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = 0x400; - uint8_t status = 0; + uint32_t timeout = 0x400U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -511,7 +511,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 timeout--; } - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -543,10 +543,10 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) } /* Provide an SW reset and Read and verify the: - - CF Configuration Option Register at address 0x98000200 --> 0x80 - - Card Configuration and Status Register at address 0x98000202 --> 0x00 - - Pin Replacement Register at address 0x98000204 --> 0x0C - - Socket and Copy Register at address 0x98000206 --> 0x00 + - CF Configuration Option Register at address 0x98000200U --> 0x80 + - Card Configuration and Status Register at address 0x98000202U --> 0x00 + - Pin Replacement Register at address 0x98000204U --> 0x0C + - Socket and Copy Register at address 0x98000206U --> 0x00 */ /* Check the PCCARD controller state */ @@ -671,7 +671,7 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) { - uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0; + uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0U; /* Check the PCCARD controller state */ if(hpccard->State == HAL_PCCARD_STATE_BUSY) @@ -687,7 +687,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) timeout--; } - if(timeout == 0) + if(timeout == 0U) { status_cf = PCCARD_TIMEOUT_ERROR; } @@ -707,7 +707,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) { - uint8_t data = 0, status_cf = PCCARD_BUSY; + uint8_t data = 0U, status_cf = PCCARD_BUSY; /* Check the PCCARD controller state */ if(hpccard->State == HAL_PCCARD_STATE_BUSY) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd.c index a1810abcceedf72ebd06ed17fc8f952583933f49..4a37218e52d4e7289d826a0004a324d9619afdb7 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -96,7 +96,7 @@ /** @defgroup PCD_Private_Define PCD Private Define * @{ */ -#define BTABLE_ADDRESS (0x000) +#define BTABLE_ADDRESS (0x000U) /** * @} */ @@ -139,9 +139,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t i = 0; + uint32_t i = 0U; - uint32_t wInterrupt_Mask = 0; + uint32_t wInterrupt_Mask = 0U; /* Check the PCD handle allocation */ if(hpcd == NULL) @@ -164,50 +164,50 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Init endpoints structures */ - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) { /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1; + hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; /* Control until ep is actvated */ hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0; - hpcd->IN_ep[i].xfer_buff = 0; - hpcd->IN_ep[i].xfer_len = 0; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; } - for (i = 0; i < hpcd->Init.dev_endpoints ; i++) + for (i = 0U; i < hpcd->Init.dev_endpoints ; i++) { - hpcd->OUT_ep[i].is_in = 0; + hpcd->OUT_ep[i].is_in = 0U; hpcd->OUT_ep[i].num = i; /* Control until ep is activated */ hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0; - hpcd->OUT_ep[i].xfer_buff = 0; - hpcd->OUT_ep[i].xfer_len = 0; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; } /* Init Device */ - /*CNTR_FRES = 1*/ + /*CNTR_FRES = 1U*/ hpcd->Instance->CNTR = USB_CNTR_FRES; - /*CNTR_FRES = 0*/ - hpcd->Instance->CNTR = 0; + /*CNTR_FRES = 0U*/ + hpcd->Instance->CNTR = 0U; /*Clear pending interrupts*/ - hpcd->Instance->ISTR = 0; + hpcd->Instance->ISTR = 0U; /*Set Btable Adress*/ hpcd->Instance->BTABLE = BTABLE_ADDRESS; /*set wInterrupt_Mask global variable*/ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; + | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; /*Set interrupt mask*/ hpcd->Instance->CNTR = wInterrupt_Mask; - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; hpcd->State= HAL_PCD_STATE_READY; return HAL_OK; @@ -296,7 +296,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { /* DP Pull-Down is external */ - HAL_PCDEx_SetConnectionState (hpcd, 1); + HAL_PCDEx_SetConnectionState (hpcd, 1U); return HAL_OK; } @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR = USB_CNTR_FRES; /* clear interrupt status register */ - hpcd->Instance->ISTR = 0; + hpcd->Instance->ISTR = 0U; /* switch-off device */ hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); @@ -341,28 +341,28 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { PCD_EPTypeDef *ep; - uint16_t count=0; + uint16_t count=0U; uint8_t EPindex; __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0; + __IO uint16_t wEPVal = 0U; /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) { /* extract highest priority endpoint number */ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - if (EPindex == 0) + if (EPindex == 0U) { /* Decode and service control endpoint interrupt */ /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) + if ((wIstr & USB_ISTR_DIR) == 0U) { - /* DIR = 0 */ + /* DIR = 0U */ /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + /* DIR = 0 implies that (EP_CTR_TX = 1U) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; @@ -370,54 +370,54 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff += ep->xfer_count; /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); + HAL_PCD_DataInStageCallback(hpcd, 0U); - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) { hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; } } else { - /* DIR = 1 */ + /* DIR = 1U */ - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + /* DIR = 1U & CTR_RX => SETUP or OUT int */ + /* DIR = 1U & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - if ((wEPVal & USB_EP_SETUP) != 0) + if ((wEPVal & USB_EP_SETUP) != 0U) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ + /* SETUP bit kept frozen while CTR_RX = 1U*/ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Process SETUP Packet*/ HAL_PCD_SetupStageCallback(hpcd); } - else if ((wEPVal & USB_EP_CTR_RX) != 0) + else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); ep->xfer_buff+=ep->xfer_count; } /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); + HAL_PCD_DataOutStageCallback(hpcd, 0U); - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket) + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID) } } } @@ -428,28 +428,28 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) + if ((wEPVal & USB_EP_CTR_RX) != 0U) { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); ep = &hpcd->OUT_ep[EPindex]; /* OUT double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) { /*read from endpoint BUF0Addr buffer*/ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); } @@ -458,18 +458,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT) } /*multi-packet on the NON control OUT endpoint*/ ep->xfer_count+=count; ep->xfer_buff+=count; - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { /* RX COMPLETE */ HAL_PCD_DataOutStageCallback(hpcd, ep->num); @@ -481,7 +481,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } /* if((wEPVal & EP_CTR_RX) */ - if ((wEPVal & USB_EP_CTR_TX) != 0) + if ((wEPVal & USB_EP_CTR_TX) != 0U) { ep = &hpcd->IN_ep[EPindex]; @@ -489,21 +489,21 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); /* IN double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); } } else { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) { /*read from endpoint BUF0Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); } @@ -512,19 +512,19 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) } /*multi-packet on the NON control IN endpoint*/ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_buff+=ep->xfer_count; /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { /* TX COMPLETE */ HAL_PCD_DataInStageCallback(hpcd, ep->num); @@ -557,7 +557,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { - uint32_t wInterrupt_Mask = 0; + uint32_t wInterrupt_Mask = 0U; if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) { @@ -570,7 +570,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); + HAL_PCD_SetAddress(hpcd, 0U); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) @@ -584,7 +584,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) { - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); + hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE)); /*set wInterrupt_Mask global variable*/ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ @@ -606,7 +606,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U) { HAL_PCD_SuspendCallback(hpcd); } @@ -825,7 +825,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - HAL_PCDEx_SetConnectionState(hpcd, 1); + HAL_PCDEx_SetConnectionState(hpcd, 1U); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -841,7 +841,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); /* Disable DP Pull-Down bit*/ - HAL_PCDEx_SetConnectionState(hpcd, 0); + HAL_PCDEx_SetConnectionState(hpcd, 0U); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -857,7 +857,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) { __HAL_LOCK(hpcd); - if(address == 0) + if(address == 0U) { /* set device address and enable function */ hpcd->Instance->DADDR = USB_DADDR_EF; @@ -883,17 +883,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; ep->maxpacket = ep_mps; ep->type = ep_type; @@ -914,29 +914,31 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint case PCD_EP_TYPE_ISOC: PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS); break; + default: + break; } PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num); - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { if (ep->is_in) { /*Set the endpoint Transmit buffer address */ PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) } else { /*Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress); /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket) + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) } } /*Double Buffer*/ @@ -945,29 +947,29 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /*Set the endpoint as double buffered*/ PCD_SET_EP_DBUF(hpcd->Instance, ep->num); /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1); + PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1) - if (ep->is_in==0) + if (ep->is_in==0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) PCD_RX_DTOG(hpcd->Instance, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } @@ -986,7 +988,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; } @@ -994,51 +996,51 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { ep = &hpcd->OUT_ep[ep_addr & 0x7F]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; __HAL_LOCK(hpcd); - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { if (ep->is_in) { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } /*Double Buffer*/ else { - if (ep->is_in==0) + if (ep->is_in==0U) { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) /* Reset value of the data toggle bits for the endpoint out*/ PCD_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) } else { /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) PCD_RX_DTOG(hpcd->Instance, ep->num); /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) } } @@ -1065,9 +1067,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0x7FU; __HAL_LOCK(hpcd); @@ -1080,22 +1082,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u else { len=ep->xfer_len; - ep->xfer_len =0; + ep->xfer_len =0U; } /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len); + PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len) } else { /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) } - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) __HAL_UNLOCK(hpcd); @@ -1123,16 +1125,16 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) { PCD_EPTypeDef *ep; - uint16_t pmabuffer = 0; + uint16_t pmabuffer = 0U; ep = &hpcd->IN_ep[ep_addr & 0x7F]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0x7FU; __HAL_LOCK(hpcd); @@ -1145,11 +1147,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, else { len=ep->xfer_len; - ep->xfer_len =0; + ep->xfer_len =0U; } /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len); PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len); @@ -1157,7 +1159,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, else { /*Write the data to the USB endpoint*/ - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) { pmabuffer = ep->pmaaddr1; } @@ -1166,10 +1168,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, pmabuffer = ep->pmaaddr0; } PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); + PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) } - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) __HAL_UNLOCK(hpcd); @@ -1188,7 +1190,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; } @@ -1197,24 +1199,24 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 1U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); - if (ep->num == 0) + if (ep->num == 0U) { /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); + PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) } else { if (ep->is_in) { - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL) } else { - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL); + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL) } } __HAL_UNLOCK(hpcd); @@ -1232,7 +1234,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep; - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; } @@ -1241,21 +1243,21 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 0U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); __HAL_LOCK(hpcd); if (ep->is_in) { - PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) } else { - PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num); - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID); + PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID) } __HAL_UNLOCK(hpcd); @@ -1291,7 +1293,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { - hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); + hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME); return HAL_OK; } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd_ex.c index 8152717aedc404556532b582b79aab7d2c785640..156748f0e355aeaac4656154e0dd49b3790d277f 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -109,9 +109,9 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep; /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { @@ -122,7 +122,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, if (ep_kind == PCD_SNG_BUF) { /*Single Buffer*/ - ep->doublebuffer = 0; + ep->doublebuffer = 0U; /*Configure the PMA*/ ep->pmaadress = (uint16_t)pmaadress; } @@ -131,8 +131,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, /*Double Buffer Endpoint*/ ep->doublebuffer = 1; /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16; + ep->pmaaddr0 = pmaadress & 0xFFFFU; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; } return HAL_OK; @@ -164,15 +164,17 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */ + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; + uint32_t i, temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U)); + for (i = n; i != 0; i--) { temp1 = (uint16_t) * pbUsrBuf; pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ; *pdwVal++ = temp2; pdwVal++; pbUsrBuf++; @@ -189,13 +191,19 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1;/* /2*/ + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; uint32_t i; uint32_t *pdwVal; - pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400); + + pdwVal = (uint32_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U)); + uint32_t tmp = *pdwVal++; + *pbUsrBuf++ = (uint16_t)((tmp >> 0) & 0xFF); + *pbUsrBuf++ = (uint16_t)((tmp >> 8) & 0xFF); + + for (i = n; i != 0; i--) { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; + *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++; pbUsrBuf++; } } @@ -216,17 +224,16 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui */ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; uint32_t i; uint16_t temp1, temp2; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - - for (i = n; i != 0; i--) + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + for (i = n; i != 0U; i--) { temp1 = (uint16_t) * pbUsrBuf; pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; + temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ; *pdwVal++ = temp2; pbUsrBuf++; } @@ -242,13 +249,13 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u */ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { - uint32_t n = (wNBytes + 1) >> 1; + uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U; uint32_t i; uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) + pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U)); + for (i = n; i != 0U; i--) { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; + *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++; pbUsrBuf++; } } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr.c index d90112ada2c1ea237c9857cf5892db8d13180adc..20b205f746c47333e61ffa9939bd98aa70a85895 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -243,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Comparator auto-wakeup (AWU) from the Stop mode (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: - (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U) to be sensitive to to the selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using the EXTI_Init() function. (+++) Configure the comparator to generate the event. @@ -255,7 +255,7 @@ void HAL_PWR_DisableBkUpAccess(void) * @brief Enables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * This parameter can be value of : - * @ref PWREx_WakeUp_Pins + * @ref PWR_WakeUp_Pins * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) @@ -270,7 +270,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) * @brief Disables the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be values of : - * @ref PWREx_WakeUp_Pins + * @ref PWR_WakeUp_Pins * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) @@ -342,7 +342,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr_ex.c index 4bc7a2658e6dac46f8b3e1d73034a3c026752afc..023f0744f4ff3845dc10af7752c00aba5746ea13 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -59,10 +59,10 @@ /** @defgroup PWREx_Private_Constants PWR Extended Private Constants * @{ */ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) /** * @} */ @@ -109,7 +109,7 @@ In Stop mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain. Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the - microcontroller must be powered from a nominal VDD = 1.8V +/-8% voltage. + microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc.c index d46f407fd61d78961610571f3f43f8b98e6f929b..1fbd9997a163889b85259299a522547ff6fdd070 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -120,10 +120,10 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 16, 16}; -const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, - 9,10, 11, 12, 13, 14, 15, 16}; +const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; +const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; /** * @} */ @@ -752,7 +752,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); } /* Update the SystemCoreClock global variable */ @@ -913,8 +913,8 @@ void HAL_RCC_DisableCSS(void) */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0; - uint32_t sysclockfreq = 0; + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; tmpreg = RCC->CFGR; @@ -939,7 +939,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (HSI_VALUE >> 1) * pllmul; + pllclk = (HSI_VALUE >> 1U) * pllmul; } #else if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) @@ -1118,7 +1118,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc_ex.c index c5a267c25a1428f87f6b9bb67039cfbfdd1b2c31..ece47adccefcff12e88f427ecc6df0a180953c81 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -120,8 +120,8 @@ static uint32_t RCC_GetPLLCLKFreq(void); */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tickstart = 0; - uint32_t temp_reg = 0; + uint32_t tickstart = 0U; + uint32_t temp_reg = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); @@ -959,14 +959,14 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { - uint32_t frequency = 0; - uint32_t srcclk = 0; + uint32_t frequency = 0U; + uint32_t srcclk = 0U; #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) - uint16_t adc_pll_prediv_table[12] = { 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; + uint16_t adc_pll_prediv_table[12] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ -#if defined(RCC_CFGR_SDADCPRE) - uint8_t sdadc_prescaler_table[16] = { 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, 48}; -#endif /* RCC_CFGR_SDADCPRE */ +#if defined(RCC_CFGR_SDPRE) + uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}; +#endif /* RCC_CFGR_SDPRE */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); @@ -991,12 +991,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { - frequency = HSE_VALUE / 32; + frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1035,7 +1035,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1068,7 +1068,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART2*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1102,7 +1102,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for USART3*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1136,7 +1136,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for UART4*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1170,7 +1170,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for UART5*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1193,7 +1193,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1216,7 +1216,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C2*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1240,7 +1240,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2C3*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1265,7 +1265,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for I2S*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1287,13 +1287,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if USB clock selection is divided by 1.5 */ else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */ { - frequency = (RCC_GetPLLCLKFreq() * 3) / 2; + frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U; } } /* Clock not enabled for USB*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1315,18 +1315,18 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */ - frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xF]; + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ + frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU]; } /* Clock not enabled for ADC1*/ else { - frequency = 0; + frequency = 0U; } } #else /* RCC_CFGR_ADCPRE */ - /* ADC1 is set to PLCK2 frequency divided by 2/4/6/8 */ - frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1) * 2); + /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */ + frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U); #endif /* RCC_CFGR2_ADC1PRES */ break; } @@ -1347,13 +1347,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */ + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF]; } /* Clock not enabled for ADC12*/ else { - frequency = 0; + frequency = 0U; } } break; @@ -1375,13 +1375,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { - /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */ + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF]; } /* Clock not enabled for ADC34*/ else { - frequency = 0; + frequency = 0U; } } break; @@ -1406,7 +1406,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM1*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1430,7 +1430,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM2*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1454,7 +1454,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM8*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1478,7 +1478,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM15*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1502,7 +1502,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM16*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1526,7 +1526,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM17*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1550,7 +1550,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM20*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1574,7 +1574,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for TIM34*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1598,21 +1598,21 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for HRTIM1*/ else { - frequency = 0; + frequency = 0U; } break; } #endif /* RCC_CFGR3_HRTIM1SW */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) case RCC_PERIPHCLK_SDADC: { /* Get the current SDADC source */ srcclk = __HAL_RCC_GET_SDADC_SOURCE(); - /* Frequency is the system frequency divided by SDADC prescaler (2/4/6/8/10/12/14/16/20/24/28/32/36/40/44/48) */ - frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDADCPRE)) & 0xF]; + /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */ + frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF]; break; } -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ #if defined(RCC_CFGR3_CECSW) case RCC_PERIPHCLK_CEC: { @@ -1632,7 +1632,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Clock not enabled for CEC*/ else { - frequency = 0; + frequency = 0U; } break; } @@ -1664,25 +1664,25 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ static uint32_t RCC_GetPLLCLKFreq(void) { - uint32_t pllmul = 0, pllsource = 0, prediv = 0, pllclk = 0; + uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U; pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - pllmul = ( pllmul >> 18) + 2; + pllmul = ( pllmul >> 18U) + 2U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if (pllsource != RCC_PLLSOURCE_HSI) { - prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (HSE_VALUE/prediv) * pllmul; } else { - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (HSI_VALUE >> 1) * pllmul; + /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */ + pllclk = (HSI_VALUE >> 1U) * pllmul; } #else - prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc.c index ea7ace97d46765c3aafdf6e86f601ea8804a4fcd..fe9086bb69b49db2b6a7ddc2b8bf7be0401f8cb0 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: @@ -292,7 +292,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); @@ -343,7 +343,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) else { /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; + hrtc->Instance->TR = 0x00000000U; hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); /* Reset All CR bits except CR[2:0] */ hrtc->Instance->CR &= RTC_CR_WUCKSEL; @@ -366,23 +366,23 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) } /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; + hrtc->Instance->CR &= 0x00000000U; hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMASSR = 0x00000000U; + hrtc->Instance->ALRMBSSR = 0x00000000U; /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; + hrtc->Instance->ISR = 0x00000000U; /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAFCR = (uint32_t)0x00000000; + hrtc->Instance->TAFCR = 0x00000000U; - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) @@ -471,7 +471,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -492,16 +492,16 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } else { - sTime->TimeFormat = 0x00; + sTime->TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sTime->Hours)); } assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); + (((uint32_t)sTime->TimeFormat) << 16U)); } else { @@ -513,15 +513,15 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } else { - sTime->TimeFormat = 0x00; + sTime->TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ + tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ + ((uint32_t)(sTime->Minutes) << 8U) | \ ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); + ((uint32_t)(sTime->TimeFormat) << 16U)); } /* Disable the write protection for RTC registers */ @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Exit Initialization mode */ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) @@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -616,10 +616,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -645,7 +645,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -655,9 +655,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); @@ -668,10 +668,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); + ((uint32_t)sDate->WeekDay << 13U)); } else { @@ -681,10 +681,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = RTC_Bcd2ToByte(sDate->Date); assert_param(IS_RTC_DATE(datetmpreg)); - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ + datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ + (((uint32_t)sDate->Month) << 8U) | \ ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); + (((uint32_t)sDate->WeekDay) << 13U)); } /* Disable the write protection for RTC registers */ @@ -712,7 +712,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /* Exit Initialization mode */ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) @@ -753,7 +753,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t datetmpreg = 0; + uint32_t datetmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -762,10 +762,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -807,8 +807,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart = 0U; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -832,7 +832,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -847,11 +847,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -865,7 +865,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -883,11 +883,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -991,8 +991,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tickstart = 0U; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1016,7 +1016,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -1030,11 +1030,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1048,7 +1048,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -1065,11 +1065,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1176,7 +1176,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); @@ -1270,7 +1270,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1293,12 +1293,12 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); @@ -1385,7 +1385,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1437,7 +1437,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; @@ -1508,7 +1508,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check if the Initialization mode is set */ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) @@ -1538,15 +1538,15 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) */ uint8_t RTC_ByteToBcd2(uint8_t Value) { - uint32_t bcdhigh = 0; + uint32_t bcdhigh = 0U; - while(Value >= 10) + while(Value >= 10U) { bcdhigh++; - Value -= 10; + Value -= 10U; } - return ((uint8_t)(bcdhigh << 4) | Value); + return ((uint8_t)(bcdhigh << 4U) | Value); } /** @@ -1556,9 +1556,9 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) */ uint8_t RTC_Bcd2ToByte(uint8_t Value) { - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint32_t tmp = 0U; + tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U; + return (tmp + (Value & (uint8_t)0x0FU)); } /** * @} diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc_ex.c index cdce38d6dc6b675239abe8a5b43b4477afb71e81..ebe3f7af360b10aa1b17868e5793b9a692a82b13 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extended peripheral: @@ -39,7 +39,7 @@ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() function. - (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13). + (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U). *** Tamper configuration *** ============================ @@ -49,7 +49,7 @@ value, sampling frequency, precharge or discharge and Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. - (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13). + (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U). *** Backup Data Registers configuration *** =========================================== @@ -150,7 +150,7 @@ */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -204,7 +204,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); @@ -254,7 +254,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -297,7 +297,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0, tmpdate = 0; + uint32_t tmptime = 0U, tmpdate = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -307,17 +307,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -348,7 +348,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); @@ -366,14 +366,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); } tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE); @@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); @@ -415,14 +415,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Configure the tamper trigger */ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { - sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1); + sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1U); } tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\ + hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ (uint32_t)RTC_TAFCR_TAMPPUDIS); @@ -631,7 +631,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -660,7 +660,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -692,7 +692,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -725,7 +725,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -770,7 +770,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -859,7 +859,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -958,7 +958,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -1067,7 +1067,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1127,13 +1127,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + tmp += (BackupRegister * 4U); /* Write the specified register */ *(__IO uint32_t *)tmp = (uint32_t)Data; @@ -1149,13 +1149,13 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + tmp += (BackupRegister * 4U); /* Read the specified register */ return (*(__IO uint32_t *)tmp); @@ -1182,7 +1182,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) */ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); @@ -1250,7 +1250,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo */ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); @@ -1289,7 +1289,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Configure the Shift settings */ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) @@ -1613,7 +1613,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sdadc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sdadc.c index 0a26612bebd6502949d09f176513e38a29a20689..a2d0e205e6a6e2678bb56ec3c72caf1ed512e0fe 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sdadc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sdadc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sdadc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Sigma-Delta Analog to Digital Converter * (SDADC) peripherals: @@ -286,8 +286,8 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc) /* Initialize SDADC variables with default values */ hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF; hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF; - hsdadc->InjectedChannelsNbr = 1; - hsdadc->InjConvRemaining = 1; + hsdadc->InjectedChannelsNbr = 1U; + hsdadc->InjConvRemaining = 1U; hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER; hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER; hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE; @@ -317,14 +317,14 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc) SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage; /* Wait at least 2ms before setting ADON */ - HAL_Delay(2); + HAL_Delay(2U); } /* Enable SDADC */ hsdadc->Instance->CR2 |= SDADC_CR2_ADON; /* Wait end of stabilization */ - while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0) + while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0U) { } @@ -355,14 +355,14 @@ HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc) hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON); /* Reset all registers */ - hsdadc->Instance->CR1 = 0x00000000; - hsdadc->Instance->CR2 = 0x00000000; - hsdadc->Instance->JCHGR = 0x00000001; - hsdadc->Instance->CONF0R = 0x00000000; - hsdadc->Instance->CONF1R = 0x00000000; - hsdadc->Instance->CONF2R = 0x00000000; - hsdadc->Instance->CONFCHR1 = 0x00000000; - hsdadc->Instance->CONFCHR2 = 0x00000000; + hsdadc->Instance->CR1 = 0x00000000U; + hsdadc->Instance->CR2 = 0x00000000U; + hsdadc->Instance->JCHGR = 0x00000001U; + hsdadc->Instance->CONF0R = 0x00000000U; + hsdadc->Instance->CONF1R = 0x00000000U; + hsdadc->Instance->CONF2R = 0x00000000U; + hsdadc->Instance->CONFCHR1 = 0x00000000U; + hsdadc->Instance->CONFCHR2 = 0x00000000U; /* Call MSP deinit function */ HAL_SDADC_MspDeInit(hsdadc); @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, SDADC_ConfParamTypeDef* ConfParamStruct) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -475,7 +475,7 @@ HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, /* Program configuration register with parameters */ tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \ SDADC_CONFREG_OFFSET + \ - (uint32_t)(ConfIndex << 2)); + (uint32_t)(ConfIndex << 2U)); *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \ ConfParamStruct->Gain | \ ConfParamStruct->CommonMode | \ @@ -505,7 +505,7 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, uint32_t ConfIndex) { HAL_StatusTypeDef status = HAL_OK; - uint32_t channelnum = 0; + uint32_t channelnum = 0U; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -532,11 +532,11 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, if(Channel != SDADC_CHANNEL_8) { /* Get channel number */ - channelnum = (uint32_t)(Channel>>16); + channelnum = (uint32_t)(Channel>>16U); /* Set the channel configuration */ - hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2)); - hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2)); + hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2U)); + hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2U)); } else { @@ -1016,7 +1016,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint3 /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1150,7 +1150,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint3 /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1289,7 +1289,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pDa /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); assert_param(pData != NULL); - assert_param(Length != 0); + assert_param(Length != 0U); /* Check that DMA is not enabled for injected conversion */ if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN) @@ -1300,7 +1300,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pDa else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + (Length != 1U)) { status = HAL_ERROR; } @@ -1465,7 +1465,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad /* Check the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Return timeout status */ return HAL_TIMEOUT; @@ -1484,7 +1484,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad } /* Update remaining injected conversions */ hsdadc->InjConvRemaining--; - if(hsdadc->InjConvRemaining == 0) + if(hsdadc->InjConvRemaining == 0U) { /* end of injected sequence, reset the value */ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr; @@ -1614,7 +1614,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint3 /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); assert_param(pData != NULL); - assert_param(Length != 0); + assert_param(Length != 0U); /* Check that DMA is not enabled for regular conversion */ if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN) @@ -1722,7 +1722,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc) */ uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel) { - uint32_t value = 0; + uint32_t value = 0U; /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1754,7 +1754,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); assert_param(pData != NULL); - assert_param(Length != 0); + assert_param(Length != 0U); /* Check instance is SDADC1 */ if(hsdadc->Instance != SDADC1) @@ -1770,7 +1770,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) + (Length != 1U)) { status = HAL_ERROR; } @@ -1879,7 +1879,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc) */ uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc) { - uint32_t value = 0; + uint32_t value = 0U; /* Check parameters and check instance is SDADC1 */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -1910,7 +1910,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsda /* Check parameters */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); assert_param(pData != NULL); - assert_param(Length != 0); + assert_param(Length != 0U); /* Check instance is SDADC1 */ if(hsdadc->Instance != SDADC1) @@ -1926,7 +1926,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsda else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \ - (Length > (hsdadc->InjectedChannelsNbr << 1))) + (Length > (hsdadc->InjectedChannelsNbr << 1U))) { status = HAL_ERROR; } @@ -2035,7 +2035,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdad */ uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc) { - uint32_t value = 0; + uint32_t value = 0U; /* Check parameters and check instance is SDADC1 */ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance)); @@ -2084,7 +2084,7 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc) /* Update remaining injected conversions */ hsdadc->InjConvRemaining--; - if(hsdadc->InjConvRemaining ==0) + if(hsdadc->InjConvRemaining ==0U) { /* end of injected sequence, reset the value */ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr; @@ -2374,7 +2374,7 @@ uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc) */ static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Set INIT bit on SDADC_CR1 register */ hsdadc->Instance->CR1 |= SDADC_CR1_INIT; @@ -2411,18 +2411,18 @@ static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc) */ static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels) { - uint32_t nbChannels = 0; + uint32_t nbChannels = 0U; uint32_t tmp,i; /* Get the number of channels from bitfield */ tmp = (uint32_t) (Channels & SDADC_LSB_MASK); - for(i = 0 ; i < 9 ; i++) + for(i = 0U ; i < 9U ; i++) { - if((tmp & (uint32_t)0x00000001) != 0) + if((tmp & 0x00000001U) != 0U) { nbChannels++; } - tmp = (uint32_t) (tmp >> 1); + tmp = (uint32_t) (tmp >> 1U); } return nbChannels; } @@ -2492,7 +2492,7 @@ static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc) } /* Wait for the end of regular conversion */ tickstart = HAL_GetTick(); - while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0) + while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0U) { if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT) { @@ -2616,7 +2616,7 @@ static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc) } /* Wait for the end of injected conversion */ tickstart = HAL_GetTick(); - while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0) + while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0U) { if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT) { diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard.c index 21a02b508b9b671613dc7dce9487a19e0a91326f..af0318bcf4dd7ab51d56847669e64eb4878603fa 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State and Errors functions * + Peripheral Control functions + * + Peripheral State and Error functions * @verbatim ============================================================================== @@ -24,20 +24,20 @@ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: (++) Enable the USARTx interface clock. (++) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -92,8 +92,6 @@ [..] Below the list of most used macros in SMARTCARD HAL driver. - (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt @@ -137,8 +135,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" -#ifdef HAL_SMARTCARD_MODULE_ENABLED - /** @addtogroup STM32F3xx_HAL_Driver * @{ */ @@ -148,14 +144,15 @@ * @{ */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000 -#define SMARTCARD_TIMEOUT_VALUE 22000 +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ + #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ #define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ @@ -168,16 +165,23 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @addtogroup SMARTCARD_Private_Functions * @{ */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard); @@ -195,9 +199,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar * @brief Initialization and Configuration functions * @verbatim - =============================================================================== + ============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to initialize the USARTx associated to the SmartCard. @@ -241,12 +245,6 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar Frame Length is fixed to 8 bits plus parity: SMARTCARD frame format is given in the following table: +---------------------------------------------------------------+ - | M bit | PCE bit | SMARTCARD frame | - |---------------------|-----------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ - or - +---------------------------------------------------------------+ | M1M0 bits | PCE bit | SMARTCARD frame | |-----------------------|---------------------------------------| | 01 | 1 | | SB | 8 bit data | PB | STB | | @@ -255,9 +253,9 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcar */ /** - * @brief Initialize the SMARTCARD mode according to the specified - * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Initialize the SMARTCARD mode according to the specified + * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -269,7 +267,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) return HAL_ERROR; } - /* Check the USART associated to the SmartCard */ + /* Check the USART associated to the SMARTCARD handle */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) @@ -283,8 +281,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsmartcard); + /* Disable the Peripheral to set smartcard mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In SmartCard mode, the following bits must be kept cleared: + - LINEN in the USART_CR2 register, + - HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); + + /* set the USART in SMARTCARD mode */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN); /* Set the SMARTCARD Communication parameters */ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) @@ -297,26 +304,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) SMARTCARD_AdvFeatureConfig(hsmartcard); } - /* In SmartCard mode, the following bits must be kept cleared: - - LINEN in the USART_CR2 register, - - HDSEL and IREN bits in the USART_CR3 register.*/ - hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN); - hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); - - /* set the USART in SMARTCARD mode */ - hsmartcard->Instance->CR3 |= USART_CR3_SCEN; - /* Enable the Peripheral */ - __HAL_SMARTCARD_ENABLE(hsmartcard); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */ return (SMARTCARD_CheckIdleState(hsmartcard)); } - /** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -328,26 +325,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) return HAL_ERROR; } - /* Check the parameters */ + /* Check the USART/UART associated to the SMARTCARD handle */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsmartcard); + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - hsmartcard->Instance->CR1 = 0x0; - hsmartcard->Instance->CR2 = 0x0; - hsmartcard->Instance->CR3 = 0x0; - hsmartcard->Instance->RTOR = 0x0; - hsmartcard->Instance->GTPR = 0x0; + WRITE_REG(hsmartcard->Instance->CR1, 0x0U); + WRITE_REG(hsmartcard->Instance->CR2, 0x0U); + WRITE_REG(hsmartcard->Instance->CR3, 0x0U); + WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); + WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); /* DeInit the low level hardware */ HAL_SMARTCARD_MspDeInit(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; - hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; + hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; + hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hsmartcard); @@ -356,12 +353,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -372,12 +369,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmartcard); @@ -409,11 +406,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts + (++) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when @@ -423,67 +420,118 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : + (#) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() (++) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_SMARTCARD_Transmit_IT() (++) HAL_SMARTCARD_Receive_IT() (++) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_SMARTCARD_Transmit_DMA() (++) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SMARTCARD_TxCpltCallback() (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_SMARTCARD_Abort() + (++) HAL_SMARTCARD_AbortTransmit() + (++) HAL_SMARTCARD_AbortReceive() + (++) HAL_SMARTCARD_Abort_IT() + (++) HAL_SMARTCARD_AbortTransmit_IT() + (++) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_SMARTCARD_AbortCpltCallback() + (++) HAL_SMARTCARD_AbortTransmitCpltCallback() + (++) HAL_SMARTCARD_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + @endverbatim * @{ */ /** - * @brief Send an amount of data in blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Send an amount of data in blocking mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. - * @param Timeout : Timeout duration. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hsmartcard); - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Disable Rx, enable Tx */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - while(hsmartcard->TxXferCount > 0) + + while(hsmartcard->TxXferCount > 0U) { hsmartcard->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } + /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ + if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + { + /* Disable the Peripheral first to update modes */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + } /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -500,20 +548,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui } /** - * @brief Receive an amount of data in blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Receive an amount of data in blocking mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout : Timeout duration. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + /* Check that a Rx process is not already ongoing */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -524,13 +574,18 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; + /* Check the remain data to be received */ - while(hsmartcard->RxXferCount > 0) + while(hsmartcard->RxXferCount > 0U) { hsmartcard->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -552,11 +607,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Send an amount of data in interrupt mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Send an amount of data in interrupt mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) @@ -564,7 +619,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -572,21 +627,32 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Process Locked */ __HAL_LOCK(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + /* Disable Rx, enable Tx */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -597,11 +663,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Receive an amount of data in interrupt mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Receive an amount of data in interrupt mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) @@ -609,7 +675,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Check that a Rx process is not already ongoing */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -617,24 +683,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Process Locked */ __HAL_LOCK(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + hsmartcard->pRxBuffPtr = pData; hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE); + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - /* Enable the SMARTCARD Data Register not empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); return HAL_OK; } @@ -645,21 +708,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -667,13 +728,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Process Locked */ __HAL_LOCK(hsmartcard); + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Disable Rx, enable Tx */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -681,20 +752,25 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Set the SMARTCARD error callback */ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + /* Set the DMA abort callback */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + /* Enable the SMARTCARD transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size); + HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size); /* Clear the TC flag in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF); + CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the UART Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the SMARTCARD associated USART CR3 register */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_OK; } else @@ -704,23 +780,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard } /** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), * the received data contain the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check that a Rx process is not already ongoing */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -728,29 +802,37 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, /* Process Locked */ __HAL_LOCK(hsmartcard); - hsmartcard->pRxBuffPtr = pData; - hsmartcard->RxXferSize = Size; - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; /* Set the SMARTCARD DMA error callback */ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + /* Set the DMA abort callback */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size); + HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the SMARTCARD associated USART CR3 register */ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_OK; } else @@ -760,461 +842,838 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, } /** - * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Abort ongoing transfers (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @retval None - */ -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* SMARTCARD parity error interrupt occurred -------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - /* Set the SMARTCARD states ready to be able to start again the process */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - } + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* SMARTCARD frame error interrupt occurred --------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - /* Set the SMARTCARD states ready to be able to start again the process */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - } + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - /* SMARTCARD noise error interrupt occurred --------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - /* Set the SMARTCARD states ready to be able to start again the process */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - } + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; - /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - /* Set the SMARTCARD states ready to be able to start again the process */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + HAL_DMA_Abort(hsmartcard->hdmatx); + } } - /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET)) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; - /* Set the SMARTCARD states ready to be able to start again the process */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - } + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - /* Call SMARTCARD Error Call back function if need be --------------------------*/ - if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) - { - HAL_SMARTCARD_ErrorCallback(hsmartcard); - } + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; - /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET)) - { - SMARTCARD_Receive_IT(hsmartcard); + HAL_DMA_Abort(hsmartcard->hdmarx); + } } - /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET)) - { - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - __HAL_UNLOCK(hsmartcard); - HAL_SMARTCARD_RxCpltCallback(hsmartcard); - /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); - } + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; - /* SMARTCARD in mode Transmitter ------------------------------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET)) - { - SMARTCARD_Transmit_IT(hsmartcard); - } + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) - { - SMARTCARD_EndTransmit_IT(hsmartcard); - } -} + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; -/** - * @brief Tx Transfer completed callback. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); + /* Reset Handle ErrorCode to No Error */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. - */ + return HAL_OK; } /** - * @brief Rx Transfer completed callback. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. - */ + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hsmartcard->hdmatx); + } + } + + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; } /** - * @brief SMARTCARD error callback. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); + /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. - */ -} + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } -/** - * @} - */ + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); -/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of SmartCard - handle and also return Peripheral Errors occurred during communication process - (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state - of the SMARTCARD peripheral. - (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during - communication. + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; -@endverbatim - * @{ - */ + HAL_DMA_Abort(hsmartcard->hdmarx); + } + } + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; -/** - * @brief Return the SMARTCARD handle state. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle state - */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) -{ - uint32_t temp1= 0x00, temp2 = 0x00; - temp1 = hsmartcard->gState; - temp2 = hsmartcard->RxState; + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; } /** - * @brief Return the SMARTCARD handle error code. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle Error Code + * @brief Abort ongoing transfers (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - return hsmartcard->ErrorCode; -} + uint32_t abortcplt = 1U; -/** - * @} - */ - -/** - * @} - */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @{ - */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(hsmartcard->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; + } + else + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(hsmartcard->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; + } + else + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + } + } -/** - * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check that a Tx process is ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - if(hsmartcard->TxXferCount == 0) + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hsmartcard->hdmatx != NULL) { - /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); + /* SMARTCARD Tx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - return HAL_OK; + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } } - else + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hsmartcard->hdmarx != NULL) { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); - hsmartcard->TxXferCount--; + /* SMARTCARD Rx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - return HAL_OK; + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } } } - else + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) { - return HAL_BUSY; + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); } + + return HAL_OK; } /** - * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* Check if a receive process is ongoing or not. If not disable ERR IT */ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - /* Tx process is ended, restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - HAL_SMARTCARD_TxCpltCallback(hsmartcard); + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); + } + } + else + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); + } return HAL_OK; } - /** - * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Check that a Rx process is ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - if(--hsmartcard->RxXferCount == 0) + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hsmartcard->hdmarx != NULL) { - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); } + } + else + { + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_RxCpltCallback(hsmartcard); - - return HAL_OK; + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } - - return HAL_OK; } else { - /* Clear RXNE interrupt flag */ - __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; - return HAL_BUSY; + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); } + + return HAL_OK; } /** - * @brief Handle SMARTCARD Communication Timeout. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param Flag: specifies the SMARTCARD flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration. - * @retval HAL status + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tickstart = HAL_GetTick(); + uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); + uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == RESET) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + SMARTCARD_Receive_IT(hsmartcard); + /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */ + return; + } + } - /* Wait until flag is set */ - if(Status == RESET) + /* If some errors occur */ + cr3its = READ_REG(hsmartcard->Instance->CR3); + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) ) { - while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET) + /* SMARTCARD parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - return HAL_TIMEOUT; - } - } + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; } - } - else - { - while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) != RESET) + + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; + } + + /* Call SMARTCARD Error Call back function if need be --------------------------*/ + if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + SMARTCARD_Receive_IT(hsmartcard); + } - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET) + || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + SMARTCARD_EndRxTransfer(hsmartcard); - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel */ + if(hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); + } + } + /* other error type to be considered as blocking : + - Frame error in Transmission + */ + else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + SMARTCARD_EndTxTransfer(hsmartcard); - return HAL_TIMEOUT; + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel */ + if(hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); } } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + } } + return; + + } /* End if some error occurs */ + + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ + if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET)) + { + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + __HAL_UNLOCK(hsmartcard); + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information + * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); + return; + } + + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + SMARTCARD_Transmit_IT(hsmartcard); + return; + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; } - return HAL_OK; } /** - * @brief DMA SMARTCARD transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { - SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsmartcard->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. + */ } /** - * @brief DMA SMARTCARD receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { - SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsmartcard->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); - HAL_SMARTCARD_RxCpltCallback(hsmartcard); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. + */ } /** - * @brief DMA SMARTCARD communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { - SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsmartcard->RxXferCount = 0; - hsmartcard->TxXferCount = 0; - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; - HAL_SMARTCARD_ErrorCallback(hsmartcard); + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. + */ } /** - * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ -static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) { - uint32_t tmpreg = 0x00000000; - SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Receive Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + handle and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMARTCARD handle state. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Return SMARTCARD handle state */ + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = hsmartcard->gState; + temp2 = hsmartcard->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the SMARTCARD handle error code. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle Error Code +*/ +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +{ + return hsmartcard->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ + +/** + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpreg = 0x00000000U; + SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); @@ -1235,19 +1694,10 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. - Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - tmpreg |= USART_CR1_RE; - } tmpreg |= (uint32_t) hsmartcard->Init.WordLength; MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Stop bits are forced to 1.5 (STOP = 11) */ tmpreg = hsmartcard->Init.StopBits; /* Synchronous mode is activated by default */ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; @@ -1271,7 +1721,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); @@ -1284,19 +1734,19 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate); + hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_UNDEFINED: default: @@ -1309,9 +1759,9 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** - * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Configure the SMARTCARD associated USART peripheral advanced features. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) @@ -1371,23 +1821,28 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) } /** - * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Check the SMARTCARD Idle State. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) { + uint32_t tickstart = 0U; /* Initialize the SMARTCARD ErrorCode */ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Check if the Transmitter is enabled */ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { + /* Timeout occurred */ return HAL_TIMEOUT; } } @@ -1396,13 +1851,14 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { + /* Timeout occurred */ return HAL_TIMEOUT; } } - /* Initialize the SMARTCARD state*/ + /* Initialize the SMARTCARD states */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1413,18 +1869,428 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar } /** - * @} + * @brief Handle SMARTCARD Communication Timeout. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param Flag Specifies the SMARTCARD flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration. + * @retval HAL status */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + /** - * @} + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; +} + /** - * @} + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; +} + + +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + hsmartcard->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + + /* Stop SMARTCARD DMA Tx request if ongoing */ + if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) ) + { + hsmartcard->TxXferCount = 0U; + SMARTCARD_EndTxTransfer(hsmartcard); + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) ) + { + hsmartcard->RxXferCount = 0U; + SMARTCARD_EndRxTransfer(hsmartcard); + } + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; + HAL_SMARTCARD_ErrorCallback(hsmartcard); +} + +/** + * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + hsmartcard->TxXferCount = 0U; + + HAL_SMARTCARD_ErrorCallback(hsmartcard); +} + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); + + hsmartcard->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hsmartcard->hdmarx != NULL) + { + if(hsmartcard->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +} + + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent); + + hsmartcard->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hsmartcard->hdmatx != NULL) + { + if(hsmartcard->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +} + + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent); + + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None */ +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent); + + hsmartcard->RxXferCount = 0U; + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +} + +/** + * @brief Send an amount of data in non-blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + if(hsmartcard->TxXferCount == 0U) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + return HAL_OK; + } + else + { + hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU); + hsmartcard->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ + if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + { + /* Disable the Peripheral first to update modes */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + } + + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + HAL_SMARTCARD_TxCpltCallback(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + + if(--hsmartcard->RxXferCount == 0U) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + + return HAL_BUSY; + } +} + +/** + * @} + */ #endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard_ex.c index 06ebbcc601d20df590903c8422ed2cdf688b621f..89e930d949674f1fd0f33787f9a0162d11d41e3c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smartcard_ex.c @@ -2,14 +2,13 @@ ****************************************************************************** * @file stm32f3xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SMARTCARD HAL module driver. - * * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. - * + Initialization and de-initialization function - * + Peripheral Control function + * + Initialization and de-initialization functions + * + Peripheral Control functions * * @verbatim @@ -59,8 +58,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" -#ifdef HAL_SMARTCARD_MODULE_ENABLED - /** @addtogroup STM32F3xx_HAL_Driver * @{ */ @@ -69,6 +66,7 @@ * @brief SMARTCARD Extension HAL module driver * @{ */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -77,7 +75,7 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions * @{ */ @@ -134,20 +132,27 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Process Locked */ - __HAL_LOCK(hsmartcard); + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - /* Set the USART RTOEN bit */ - hsmartcard->Instance->CR2 |= USART_CR2_RTOEN; + /* Set the USART RTOEN bit */ + SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - return HAL_OK; + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** @@ -159,20 +164,27 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Process Locked */ - __HAL_LOCK(hsmartcard); + if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - /* Clear the USART RTOEN bit */ - hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN); + /* Clear the USART RTOEN bit */ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); - return HAL_OK; + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** @@ -183,6 +195,8 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + /** * @} */ @@ -191,6 +205,4 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smbus.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smbus.c index ab87a3eb80a8597a9c1821244db30dee02775611..fae7044d276ec0c62e5ef2ac18ee30af37e00c7c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smbus.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_smbus.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_smbus.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SMBUS HAL module driver. * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, @@ -41,7 +41,7 @@ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() - (#) For SMBUS IO operations, only one mode of operations is available within this driver : + (#) For SMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== @@ -141,18 +141,18 @@ /* Private typedef -----------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup SMBUS_Private_Define SMBUS Private Constants - * @{ - */ -#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */ -#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /*!< 10 s */ -#define HAL_TIMEOUT_BUSY ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_DIR ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_RXNE ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_STOPF ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_TC ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_TCR ((uint32_t)25) /*!< 25 ms */ -#define HAL_TIMEOUT_TXIS ((uint32_t)25) /*!< 25 ms */ -#define MAX_NBYTE_SIZE 255 + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */ +#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE 255U /** * @} */ @@ -170,6 +170,8 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -273,16 +275,16 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hsmbus->Init.OwnAddress1 != 0) + if(hsmbus->Init.OwnAddress1 != 0U) { if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) - { - hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); - } + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); + } else /* SMBUS_ADDRESSINGMODE_10BIT */ - { - hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); - } + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); + } } /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ @@ -297,7 +299,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8)); + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ @@ -357,11 +359,11 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) /** * @brief Initialize the SMBUS MSP. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -373,11 +375,11 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) /** * @brief DeInitialize the SMBUS MSP. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -488,13 +490,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } @@ -578,13 +584,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } @@ -641,7 +651,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -682,7 +692,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -704,10 +714,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Prepare transfer parameters */ hsmbus->pBuffPtr = pData; - hsmbus->XferSize = Size; hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + if(Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; @@ -720,12 +732,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) { - SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -773,7 +785,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -799,18 +811,21 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ hsmbus->XferCount = Size; hsmbus->XferOptions = XferOptions; + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + /* Set NBYTE to receive */ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { - SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } else { - SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); } /* Clear ADDR flag after prepare the transfer parameters */ @@ -922,9 +937,9 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; - __IO uint32_t SMBUS_Trials = 0; + __IO uint32_t SMBUS_Trials = 0U; if(hsmbus->State == HAL_SMBUS_STATE_READY) { @@ -951,7 +966,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1043,7 +1058,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - uint32_t tmpisrvalue = 0; + uint32_t tmpisrvalue = 0U; /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ @@ -1179,13 +1194,13 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback() could be implemented in the user file + the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file */ } @@ -1201,7 +1216,7 @@ __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback() could be implemented in the user file + the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file */ } @@ -1210,13 +1225,13 @@ __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback() could be implemented in the user file + the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file */ } @@ -1232,7 +1247,7 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) UNUSED(hsmbus); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback() could be implemented in the user file + the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file */ } @@ -1267,7 +1282,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file */ } @@ -1278,7 +1293,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval None */ - __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -1300,7 +1315,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1310,7 +1325,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) /** * @brief Return the SMBUS handle state. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. + * the configuration information for the specified SMBUS. * @retval HAL state */ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) @@ -1320,10 +1335,10 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief Return the SMBUS error code. +* @brief Return the SMBUS error code. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @retval SMBUS Error Code +* @retval SMBUS Error Code */ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) { @@ -1339,7 +1354,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1373,7 +1388,6 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { @@ -1403,6 +1417,19 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { + /* Store Last receive data if any */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + + if((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); @@ -1437,7 +1464,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) + if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); @@ -1459,7 +1486,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) + else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) @@ -1493,7 +1520,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0) + if(hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ if(hsmbus->pBuffPtr == NULL) @@ -1548,8 +1575,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) */ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { - uint8_t TransferDirection = 0; - uint16_t SlaveAddrCode = 0; + uint8_t TransferDirection = 0U; + uint16_t SlaveAddrCode = 0U; /* Process Locked */ __HAL_LOCK(hsmbus); @@ -1560,7 +1587,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0) + if(hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1617,15 +1644,15 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1) + if(hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0) + else if(hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); @@ -1643,7 +1670,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -1651,17 +1678,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) + if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) { if(hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) @@ -1677,9 +1704,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0) + if(hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); @@ -1687,7 +1714,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize--; } - if(hsmbus->XferCount == 0) + if(hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1708,6 +1735,19 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { + /* Store Last receive data if any */ + if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; + + if((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + /* Disable RX and TX Interrupts */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); @@ -1726,7 +1766,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear ADDR flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); - hsmbus->XferOptions = 0; + hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1752,7 +1792,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) */ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; + uint32_t tmpisr = 0U; if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { @@ -1794,7 +1834,7 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t */ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) { - uint32_t tmpisr = 0; + uint32_t tmpisr = 0U; if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) { @@ -1880,7 +1920,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; hsmbus->State= HAL_SMBUS_STATE_READY; @@ -1900,7 +1940,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; hsmbus->State= HAL_SMBUS_STATE_READY; @@ -1938,7 +1978,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -1952,12 +1992,51 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ + tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ (uint32_t)Mode | (uint32_t)Request); /* update CR2 register */ hsmbus->Instance->CR2 = tmpreg; } + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } +} /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi.c index efe4b7c077c12ce1f7d9c685886d097a0f6f2006..21f4f4a29b7656d7d768850179361479588a59f9 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -31,12 +31,12 @@ (+++) Configure the SPIx interrupt priority (+++) Enable the NVIC SPI IRQ handle (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel + (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -52,13 +52,79 @@ (#) The CRC feature is not managed when the DMA circular mode is enabled (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks - - @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() - (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() - (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI + modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the + maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on + the APBx peripheral clock frequency (fPCLK) used by the SPI instance. @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + ****************************************************************************** * @attention * @@ -89,40 +155,6 @@ ****************************************************************************** */ -/* - Additional Table: - - Using the HAL it is not possible to reach all supported SPI frequency with the differents - the following table resume the max SPI frequency reached with data size 8bits/16bits, - according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : - +-----------------------------------------------------------------------------------------+ - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |--------------------|--------------------|--------------------| - | | | Master | Slave | Master | Slave | Master | Slave | - |=========================================================================================| - | T | Polling | Fcpu/4 | Fcpu/8 | NA | NA | NA | NA | - | X |----------------|----------|---------|----------|---------|----------|---------| - | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA | - | R |----------------|----------|---------|----------|---------|----------|---------| - | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/4 | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | - | |----------------|----------|---------|----------|---------|----------|---------| - | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/2 | Fcpu/16 | Fcpu/2 | Fcpu/16 | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/8 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 | - | |----------------|----------|---------|----------|---------|----------|---------| - | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 | - +-----------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16 - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling - -*/ - /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" @@ -141,7 +173,7 @@ /** @defgroup SPI_Private_Constants SPI Private Constants * @{ */ -#define SPI_DEFAULT_TIMEOUT 50 +#define SPI_DEFAULT_TIMEOUT 100U /** * @} */ @@ -159,31 +191,39 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPI_Exported_Functions SPI Exported Functions * @{ */ @@ -235,7 +275,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) uint32_t frxth; /* Check the SPI handle allocation */ - if(hspi == NULL) + if (hspi == NULL) { return HAL_ERROR; } @@ -245,18 +285,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_MODE(hspi->Init.Mode)); assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ - if(hspi->State == HAL_SPI_STATE_RESET) + if (hspi->State == HAL_SPI_STATE_RESET) { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; @@ -271,7 +321,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Align by default the rs fifo threshold on the data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { frxth = SPI_RXFIFO_THRESHOLD_HF; } @@ -281,17 +331,17 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } /* CRC calculation is valid only for 16Bit and 8 Bit */ - if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } /* Align the CRC Length on the data size */ - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) { /* CRC Length aligned on the data size : value set by default */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; } @@ -301,35 +351,46 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } } - /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state, CRC Length */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); - - if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); +#if (USE_SPI_CRC != 0U) + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - hspi->Instance->CR1|= SPI_CR1_CRCL; + hspi->Instance->CR1 |= SPI_CR1_CRCL; } +#endif /* USE_SPI_CRC */ - /* Configure : NSS management */ - /* Configure : Rx Fifo Threshold */ - hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | - hspi->Init.DataSize ) | frxth; + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | + hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); - /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ - hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State= HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; return HAL_OK; } /** - * @brief DeInitialize the SPI peripheral. + * @brief De-Initialize the SPI peripheral. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status @@ -337,13 +398,14 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == NULL) + if (hspi == NULL) { return HAL_ERROR; } - /* Check the parameters */ + /* Check SPI Instance parameter */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + hspi->State = HAL_SPI_STATE_BUSY; /* Disable the SPI Peripheral Clock */ @@ -355,6 +417,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(hspi); return HAL_OK; @@ -371,13 +434,13 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SPI_MspInit should be implemented in the user file */ } /** - * @brief DeInitialize the SPI MSP. + * @brief De-Initialize the SPI MSP. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None @@ -440,21 +503,25 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); + uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - if((pData == NULL ) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; @@ -463,49 +530,61 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount--; + } /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0) + while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ - if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount--; } else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -516,28 +595,43 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ else { - while (hspi->TxXferCount > 0) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); + hspi->TxXferCount--; + } + } + while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ - if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - if(hspi->TxXferCount > 1) + if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); + *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); hspi->TxXferCount--; } } else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -545,26 +639,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } } } - +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; } @@ -587,52 +682,63 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg; - uint32_t tickstart = HAL_GetTick(); +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the TransmitReceive process */ - /* Process Locked */ - return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - if((pData == NULL ) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; + hspi->pRxBuffPtr = (uint8_t *)pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); /* this is done to handle the CRCNEXT before the latest data */ hspi->RxXferCount--; } +#endif /* USE_SPI_CRC */ /* Set the Rx Fido threshold */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -643,35 +749,37 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - /* Configure communication direction 1Line and enabled SPI if needed */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { /* Transfer loop */ - while(hspi->RxXferCount > 0) + while (hspi->RxXferCount > 0U) { /* Check the RXNE flag */ - if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { /* read the received data */ - (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; + (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; + pData += sizeof(uint8_t); hspi->RxXferCount--; } else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -682,19 +790,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 else { /* Transfer loop */ - while(hspi->RxXferCount > 0) + while (hspi->RxXferCount > 0U) { /* Check the RXNE flag */ - if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); + *((uint16_t *)pData) = hspi->Instance->DR; + pData += sizeof(uint16_t); hspi->RxXferCount--; } else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -703,14 +811,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } } +#if (USE_SPI_CRC != 0U) /* Handle the CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* freeze the CRC before the latest data */ - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); /* Read the latest data */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ errorcode = HAL_TIMEOUT; @@ -718,26 +827,26 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Receive last data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)pData) = hspi->Instance->DR; } /* Receive last data in 8 Bit mode */ else { - *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; } - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { - /* Flag Error*/ - hspi->ErrorCode = HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + /* Read CRC to Flush DR and RXNE flag */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; /* To avoid GCC warning */ @@ -749,12 +858,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* To avoid GCC warning */ UNUSED(tmpreg); - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode = HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } @@ -764,21 +873,24 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } } } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } +#endif /* USE_SPI_CRC */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; } @@ -799,46 +911,72 @@ error : * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) { -__IO uint16_t tmpreg; - uint32_t tickstart = HAL_GetTick(); + uint32_t tmp = 0U, tmp1 = 0U; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if (!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; } - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pRxData; + hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = pTxData; + hspi->pTxBuffPtr = (uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Set the Rx Fido threshold */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -850,44 +988,56 @@ __IO uint16_t tmpreg; } /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit and Receive data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } - hspi->Instance->CR1|= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } /* Check RXNE flag */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) { - *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); + *((uint16_t *)pRxData) = hspi->Instance->DR; + pRxData += sizeof(uint16_t); hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) + if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) { errorcode = HAL_TIMEOUT; goto error; @@ -897,44 +1047,62 @@ __IO uint16_t tmpreg; /* Transmit and Receive data in 8 Bit mode */ else { - while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); + hspi->TxXferCount--; + } + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* check TXE flag */ - if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) + if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - if(hspi->TxXferCount > 1) + if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); hspi->TxXferCount--; } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) + if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); } - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ - if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) + if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) { - if(hspi->RxXferCount > 1) + if (hspi->RxXferCount > 1U) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount <= 1) + *((uint16_t *)pRxData) = hspi->Instance->DR; + pRxData += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) { /* set fiforxthresold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -942,11 +1110,13 @@ __IO uint16_t tmpreg; } else { - (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; + (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR; hspi->RxXferCount--; } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) + if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)) { errorcode = HAL_TIMEOUT; goto error; @@ -954,19 +1124,20 @@ __IO uint16_t tmpreg; } } +#if (USE_SPI_CRC != 0U) /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } - - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + /* Read CRC */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; /* To avoid GCC warning */ @@ -978,12 +1149,12 @@ __IO uint16_t tmpreg; /* To avoid GCC warning */ UNUSED(tmpreg); - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); errorcode = HAL_TIMEOUT; goto error; } @@ -995,22 +1166,23 @@ __IO uint16_t tmpreg; } /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); errorcode = HAL_ERROR; } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; } @@ -1032,36 +1204,40 @@ error : HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } - if(hspi->State != HAL_SPI_STATE_READY) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - /* prepare the transfer */ + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; - hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; /* Set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { hspi->TxISR = SPI_TxISR_16BIT; } @@ -1071,23 +1247,25 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); @@ -1110,84 +1288,87 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - if((pData == NULL) || (Size == 0)) + + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } - /* Configure communication */ + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; + hspi->pRxBuffPtr = (uint8_t *)pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this we call the TransmitReceive process */ - return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); - } - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - else - { - hspi->CRCSize = 0; - } + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; - hspi->TxISR = NULL; - /* check the data size to adapt Rx threshold and the set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } SPI_RESET_CRC(hspi); } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); @@ -1210,75 +1391,84 @@ error : */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process locked */ __HAL_LOCK(hspi); - if(!((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if (!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; } - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } - hspi->CRCSize = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1; - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2; - } - } - - if(hspi->State != HAL_SPI_STATE_BUSY_RX) + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } + /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pTxData; + hspi->pTxBuffPtr = (uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; - hspi->pRxBuffPtr = pRxData; + hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; /* Set the function for IT treatment */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; } else { - hspi->RxISR = SPI_2linesRxISR_8BIT; - hspi->TxISR = SPI_2linesTxISR_8BIT; + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } SPI_RESET_CRC(hspi); } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ - /* check if packing mode is enabled and if there is more than 2 data to receive */ - if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) + /* Check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* Set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* Set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1286,7 +1476,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); @@ -1309,43 +1499,55 @@ error : HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; + + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ /* Set the SPI TxDMA Half transfer complete callback */ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; @@ -1356,33 +1558,39 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - /* packing mode is enabled only if the DMA setting is HALWORD */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + /* Packing mode is enabled only if the DMA setting is HALWORD */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Check the even/odd of the data size + crc if enabled */ - if((hspi->TxXferCount & 0x1) == 0) + if ((hspi->TxXferCount & 0x1U) == 0U) { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; } } - /* Enable the Tx DMA channel */ + /* Enable the Tx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); @@ -1394,6 +1602,7 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer @@ -1405,69 +1614,99 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { HAL_StatusTypeDef errorcode = HAL_OK; + /* check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; + hspi->pRxBuffPtr = (uint8_t *)pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the TransmitReceive process */ - return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); - } + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } +#if (USE_SPI_CRC != 0U) /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ - /* packing mode management is enabled by the DMA settings */ - if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) +#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx) + /* Packing mode management is enabled by the DMA settings */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { /* Restriction the DMA data received is not allowed in this mode */ errorcode = HAL_ERROR; goto error; } +#endif CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* set fiforxthresold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } } /* Set the SPI RxDMA Half transfer complete callback */ @@ -1479,19 +1718,25 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; - /* Enable the Rx DMA channel */ + /* Enable the Rx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + error: /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1508,33 +1753,44 @@ error: * @param Size: amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { + uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; + + /* check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process locked */ __HAL_LOCK(hspi); - if(!((hspi->State == HAL_SPI_STATE_READY) || - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + if (!((tmp == HAL_SPI_STATE_READY) || + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; } - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; goto error; } - /* check if the transmit Receive function is not called by a receive master */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } + /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = (uint8_t *)pTxData; hspi->TxXferSize = Size; @@ -1543,99 +1799,119 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->RxXferSize = Size; hspi->RxXferCount = Size; - /* Reset CRC Calculation + increase the rxsize */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } +#endif /* USE_SPI_CRC */ + + +#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx) + /* packing mode management is enabled by the DMA settings */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + goto error; + } +#endif /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - /* the packing mode management is enabled by the DMA settings according the spi data size */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + /* The packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - if((hspi->TxXferSize & 0x1) == 0x0) + if ((hspi->TxXferSize & 0x1U) == 0x0U) { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = hspi->TxXferCount >> 1; + hspi->TxXferCount = hspi->TxXferCount >> 1U; } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; } } - if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - if((hspi->RxXferCount & 0x1) == 0x0 ) + if ((hspi->RxXferCount & 0x1U) == 0x0U) { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1; + hspi->RxXferCount = hspi->RxXferCount >> 1U; } else { SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; } } } - /* Set the SPI Rx DMA transfer complete callback if the transfer request is a - reception request (RXNE) */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) { /* Set the SPI Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; } else { - /* Set the SPI Rx DMA Half transfer complete callback */ + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; } /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - /* Enable the Rx DMA channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; - /* Enable the Tx DMA channel */ + /* Enable the Tx DMA Stream/Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); @@ -1647,72 +1923,423 @@ error : } /** - * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +*/ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { - /* Process Locked */ - __HAL_LOCK(hspi); + HAL_StatusTypeDef errorcode; + __IO uint32_t count, resetcount; - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } - return HAL_OK; -} + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } -/** - * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* Enable the SPI DMA Tx & Rx requests */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } - return HAL_OK; -} + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); -/** - * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() - */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } - /* Abort the SPI DMA tx channel */ - if(hspi->hdmatx != NULL) + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) { - HAL_DMA_Abort(hspi->hdmatx); + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; } - /* Abort the SPI DMA rx channel */ - if(hspi->hdmarx != NULL) + else { - HAL_DMA_Abort(hspi->hdmarx); + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; } - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count, resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; return HAL_OK; } @@ -1729,54 +2356,86 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) uint32_t itflag = hspi->Instance->SR; /* SPI in mode Receiver ----------------------------------------------------*/ - if(((itflag & SPI_FLAG_OVR) == RESET) && - ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) + if (((itflag & SPI_FLAG_OVR) == RESET) && + ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } - /* SPI in mode Transmitter ---------------------------------------------------*/ - if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) + /* SPI in mode Transmitter -------------------------------------------------*/ + if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } - /* SPI in Error Treatment ---------------------------------------------------*/ - if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) + /* SPI in Error Treatment --------------------------------------------------*/ + if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) { - /* SPI Overrun error interrupt occurred -------------------------------------*/ - if((itflag & SPI_FLAG_OVR) != RESET) + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((itflag & SPI_FLAG_OVR) != RESET) { - if(hspi->State != HAL_SPI_STATE_BUSY_TX) + if (hspi->State != HAL_SPI_STATE_BUSY_TX) { - hspi->ErrorCode |= HAL_SPI_ERROR_OVR; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); __HAL_SPI_CLEAR_OVRFLAG(hspi); } else { + __HAL_SPI_CLEAR_OVRFLAG(hspi); return; } } - /* SPI Mode Fault error interrupt occurred -------------------------------------*/ - if((itflag & SPI_FLAG_MODF) != RESET) + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_MODF; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); __HAL_SPI_CLEAR_MODFFLAG(hspi); } - /* SPI Frame error interrupt occurred ----------------------------------------*/ - if((itflag & SPI_FLAG_FRE) != RESET) + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_FRE; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); __HAL_SPI_CLEAR_FREFLAG(hspi); } - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmarx); + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmatx); + } + } + else + { + /* Call user error callback */ + HAL_SPI_ErrorCallback(hspi); + } + } return; } } @@ -1883,7 +2542,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); @@ -1896,6 +2555,21 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ } +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -1935,6 +2609,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) */ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { + /* Return SPI ErrorCode */ return hspi->ErrorCode; } @@ -1942,13 +2617,12 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @} */ - /** * @} */ /** @addtogroup SPI_Private_Functions - * @brief Private functions + * @brief Private functions * @{ */ @@ -1960,29 +2634,37 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); - if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Clear overrun flag in 2 Lines communication mode because received data is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - hspi->TxXferCount = 0; + hspi->TxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); return; @@ -1999,22 +2681,33 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { - __IO uint16_t tmpreg; + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); +#if (USE_SPI_CRC != 0U) /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + /* Read CRC */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { tmpreg = hspi->Instance->DR; /* To avoid GCC warning */ @@ -2026,12 +2719,12 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* To avoid GCC warning */ UNUSED(tmpreg); - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; /* To avoid GCC warning */ @@ -2039,27 +2732,30 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } } +#endif /* USE_SPI_CRC */ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - hspi->RxXferCount = 0; + hspi->RxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } +#endif /* USE_SPI_CRC */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); return; @@ -2070,65 +2766,81 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t tickstart = 0U; +#if (USE_SPI_CRC != 0U) + __IO int16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { - __IO int16_t tmpreg; + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } + /* Read CRC to Flush DR and RXNE flag */ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; /* To avoid GCC warning */ UNUSED(tmpreg); } else { - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { /* Error on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } + /* Read CRC to Flush DR and RXNE flag */ tmpreg = hspi->Instance->DR; /* To avoid GCC warning */ UNUSED(tmpreg); } } +#endif /* USE_SPI_CRC */ /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Disable Rx/Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; hspi->State = HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } +#endif /* USE_SPI_CRC */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); return; @@ -2139,13 +2851,13 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_TxHalfCpltCallback(hspi); } @@ -2158,42 +2870,182 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_RxHalfCpltCallback(hspi); } /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; HAL_SPI_TxRxHalfCpltCallback(hspi); } /** * @brief DMA SPI communication error callback. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->ErrorCode|= HAL_SPI_ERROR_DMA; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); +} + /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2203,12 +3055,12 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in packing mode */ - if(hspi->RxXferCount > 1) + if (hspi->RxXferCount > 1U) { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2; - if(hspi->RxXferCount == 1) + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) { /* set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); @@ -2222,25 +3074,28 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* check end of the reception */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_2linesRxISR_8BITCRC; return; } +#endif /* USE_SPI_CRC */ - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2249,24 +3104,29 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ UNUSED(tmpreg); hspi->CRCSize--; /* check end of the reception */ - if(hspi->CRCSize == 0) + if (hspi->CRCSize == 0U) { - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#endif /* USE_SPI_CRC */ /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. @@ -2277,11 +3137,11 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in packing Bit mode */ - if(hspi->TxXferCount >= 2) + if (hspi->TxXferCount >= 2U) { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2; + hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else @@ -2291,18 +3151,23 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* check the end of the transmission */ - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + /* Set CRC Next Bit to send CRC */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); return; } +#endif /* USE_SPI_CRC */ + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } @@ -2318,28 +3183,31 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_2linesRxISR_16BITCRC; return; } +#endif /* USE_SPI_CRC */ /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2349,7 +3217,11 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ - __IO uint16_t tmpreg = hspi->Instance->DR; + __IO uint16_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); @@ -2358,6 +3230,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) SPI_CloseRxTx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. @@ -2373,24 +3246,30 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->TxXferCount--; /* Enable CRC Transmission */ - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + /* Set CRC Next Bit to send CRC */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); return; } +#endif /* USE_SPI_CRC */ + /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { SPI_CloseRxTx_ISR(hspi); } } } +#if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2399,17 +3278,22 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ UNUSED(tmpreg); hspi->CRCSize--; - if(hspi->CRCSize == 0) + if (hspi->CRCSize == 0U) { SPI_CloseRx_ISR(hspi); } } +#endif /* USE_SPI_CRC */ /** * @brief Manage the receive 8-bit in Interrupt context. @@ -2422,23 +3306,28 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_8BITCRC; return; } +#endif /* USE_SPI_CRC */ SPI_CloseRx_ISR(hspi); } } +#if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -2447,9 +3336,11 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg; + __IO uint16_t tmpreg = 0U; + /* Read data register to flush CRC */ tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); @@ -2458,6 +3349,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) SPI_CloseRx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** * @brief Manage the 16-bit receive in Interrupt context. @@ -2471,19 +3363,23 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ - if(hspi->RxXferCount == 0) + if (hspi->RxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_16BITCRC; return; } +#endif /* USE_SPI_CRC */ SPI_CloseRx_ISR(hspi); } } @@ -2499,13 +3395,15 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ SPI_CloseTx_ISR(hspi); } } @@ -2523,13 +3421,15 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - if(hspi->TxXferCount == 0) + if (hspi->TxXferCount == 0U) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ SPI_CloseTx_ISR(hspi); } } @@ -2537,21 +3437,21 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle SPI Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag : SPI flag to check - * @param State : flag state to check - * @param Timeout : Timeout duration + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param State: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = HAL_GetTick(); - - while((hspi->Instance->SR & Flag) != State) + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2560,19 +3460,20 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } - hspi->State= HAL_SPI_STATE_READY; + hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -2588,29 +3489,30 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle SPI FIFO Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo : Fifo to check - * @param State : Fifo state to check - * @param Timeout : Timeout duration + * the configuration information for SPI module. + * @param Fifo: Fifo to check + * @param State: Fifo state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) { __IO uint8_t tmpreg; - uint32_t tickstart = HAL_GetTick(); - while((hspi->Instance->SR & Fifo) != State) + while ((hspi->Instance->SR & Fifo) != State) { - if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); /* To avoid GCC warning */ UNUSED(tmpreg); } - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2619,14 +3521,15 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } @@ -2648,30 +3551,33 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, * @brief Handle the check of the RX transaction complete. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout : Timeout duration - * @retval None. + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status */ -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } /* Control the BSY flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Empty the FRLVL fifo */ - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } } @@ -2679,22 +3585,24 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t } /** - * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout : Timeout duration + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi: SPI handle + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status */ -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { /* Control if the TX fifo is empty */ - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } /* Control the BSY flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } return HAL_OK; @@ -2708,28 +3616,35 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->State = HAL_SPI_STATE_READY; - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); HAL_SPI_ErrorCallback(hspi); } else { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - if(hspi->State == HAL_SPI_STATE_BUSY_RX) + if (hspi->State == HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_READY; HAL_SPI_RxCpltCallback(hspi); @@ -2745,7 +3660,9 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) } +#endif /* USE_SPI_CRC */ } /** @@ -2756,34 +3673,38 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Check the end of the transaction */ - if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) - { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; - } - hspi->State = HAL_SPI_STATE_READY; + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + hspi->State = HAL_SPI_STATE_READY; - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_RxCpltCallback(hspi); } else { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - HAL_SPI_RxCpltCallback(hspi); - } - else - { - HAL_SPI_ErrorCallback(hspi); - } + HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ } /** @@ -2794,23 +3715,28 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { + uint32_t tickstart = 0U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Disable TXE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); /* Check the end of the transaction */ - if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } hspi->State = HAL_SPI_STATE_READY; - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); } @@ -2820,6 +3746,93 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) } } +/** + * @brief Handle abort a Rx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Check TXEIE is disabled */ + do + { + if (count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi_ex.c index 944b9964060d280cf22251784b9bcd8fa37da7f6..aee4f9e5b1257c96d3cfa637802523a61d9d5a85 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended SPI HAL module driver. * This file provides firmware functions to manage the following * SPI peripheral extended functionalities : @@ -72,8 +72,8 @@ */ /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -98,13 +98,13 @@ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) { __IO uint32_t tmpreg; - uint8_t count = 0; - while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + uint8_t count = 0U; + while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) { count++; tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ - if(count == SPI_FIFO_SIZE) + if (count == SPI_FIFO_SIZE) { return HAL_TIMEOUT; } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sram.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sram.c index e690a53b7419fdf0831c179310db9708538ba4f5..14bc2300dc944be12fc4cf7a189607f4d92e04f9 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sram.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_sram.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -295,7 +295,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint8_t *)psramaddress; pDstBuffer++; @@ -337,7 +337,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint8_t *)psramaddress = *pSrcBuffer; pSrcBuffer++; @@ -373,7 +373,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint16_t *)psramaddress; pDstBuffer++; @@ -415,7 +415,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint16_t *)psramaddress = *pSrcBuffer; pSrcBuffer++; @@ -449,7 +449,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint32_t *)pAddress; pDstBuffer++; @@ -489,7 +489,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint32_t *)pAddress = *pSrcBuffer; pSrcBuffer++; diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim.c index 0108063edf545b424cb51a9db3b202ff38a02884..fb996617504cee6a2781b7638d6149cf047030f2 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -211,6 +211,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -394,7 +395,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -488,6 +489,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -787,7 +789,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -994,6 +996,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1296,7 +1299,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1503,6 +1506,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1778,7 +1782,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1979,6 +1983,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -2240,9 +2245,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Check the TIM handle allocation */ if(htim == NULL) @@ -2252,6 +2257,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2294,18 +2302,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2482,7 +2490,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ + /* Enable the capture compare Interrupts 1 and/or 2U */ switch (Channel) { case TIM_CHANNEL_1: @@ -2535,14 +2543,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - /* Disable the capture compare Interrupts 1 */ + /* Disable the capture compare Interrupts 1U */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if(Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - /* Disable the capture compare Interrupts 2 */ + /* Disable the capture compare Interrupts 2U */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else @@ -2550,7 +2558,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - /* Disable the capture compare Interrupts 1 and 2 */ + /* Disable the capture compare Interrupts 1 and 2U */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } @@ -2589,7 +2597,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch } else if((htim->State == HAL_TIM_STATE_READY)) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) { return HAL_ERROR; } @@ -2706,14 +2714,14 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - /* Disable the capture compare DMA Request 1 */ + /* Disable the capture compare DMA Request 1U */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } else if(Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - /* Disable the capture compare DMA Request 2 */ + /* Disable the capture compare DMA Request 2U */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } else @@ -2721,7 +2729,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - /* Disable the capture compare DMA Request 1 and 2 */ + /* Disable the capture compare DMA Request 1 and 2U */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } @@ -2769,7 +2777,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2791,7 +2799,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2812,7 +2820,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2833,7 +2841,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -3030,7 +3038,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { @@ -3062,7 +3070,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; @@ -3125,7 +3133,7 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_ /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; } break; @@ -3155,7 +3163,7 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_ /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; } break; @@ -3336,7 +3344,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U ) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3356,7 +3364,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC1: @@ -3368,7 +3376,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3380,7 +3388,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3392,7 +3400,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3404,7 +3412,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_COM: @@ -3416,7 +3424,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3428,7 +3436,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3559,7 +3567,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U ) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3579,7 +3587,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC1: @@ -3591,7 +3599,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3603,7 +3611,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3615,7 +3623,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3627,7 +3635,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_COM: @@ -3639,7 +3647,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3651,7 +3659,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3817,12 +3825,12 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 1 */ + /* Enable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; } else { - /* Disable the Ocref clear feature for Channel 1 */ + /* Disable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; } } @@ -3832,12 +3840,12 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 2 */ + /* Enable the Ocref clear feature for Channel 2U */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; } else { - /* Disable the Ocref clear feature for Channel 2 */ + /* Disable the Ocref clear feature for Channel 2U */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; } } @@ -3847,12 +3855,12 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 3 */ + /* Enable the Ocref clear feature for Channel 3U */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; } else { - /* Disable the Ocref clear feature for Channel 3 */ + /* Disable the Ocref clear feature for Channel 3U */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; } } @@ -3862,12 +3870,12 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 4 */ + /* Enable the Ocref clear feature for Channel 4U */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; } else { - /* Disable the Ocref clear feature for Channel 4 */ + /* Disable the Ocref clear feature for Channel 4U */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; } } @@ -3892,7 +3900,7 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Process Locked */ __HAL_LOCK(htim); @@ -3966,7 +3974,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_TI1: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ @@ -3996,7 +4004,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo break; case TIM_CLOCKSOURCE_TI1ED: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ @@ -4011,7 +4019,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo break; case TIM_CLOCKSOURCE_ITR0: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); @@ -4019,7 +4027,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo break; case TIM_CLOCKSOURCE_ITR1: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); @@ -4027,7 +4035,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo break; case TIM_CLOCKSOURCE_ITR2: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); @@ -4035,7 +4043,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo break; case TIM_CLOCKSOURCE_ITR3: { - /* Check whether or not the timer instance supports external clock mode 1 */ + /* Check whether or not the timer instance supports external clock mode 1U */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); @@ -4066,7 +4074,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0U; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); @@ -4171,7 +4179,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; __HAL_LOCK(htim); @@ -4546,7 +4554,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ @@ -4564,6 +4572,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= (uint32_t)Structure->ClockDivision; } + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ @@ -4591,9 +4602,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) */ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -4665,9 +4676,9 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4685,12 +4696,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); + tmpccer |= (OC_Config->OCPolarity << 4U); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { @@ -4699,7 +4710,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); + tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; @@ -4711,13 +4722,17 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - /* Reset the Output Compare and Output Compare N IDLE State */ + /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; +#if defined(STM32F373xC) || defined(STM32F378xx) +#else + /* Reset the Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2N; +#endif /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); + tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); + tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ @@ -4741,9 +4756,9 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4765,7 +4780,7 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); + tmpccer |= (OC_Config->OCPolarity << 8U); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { @@ -4774,7 +4789,7 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); + tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } @@ -4785,13 +4800,16 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +#if defined(STM32F373xC) || defined(STM32F378xx) +#else /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; +#endif /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); + tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); + tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ @@ -4815,9 +4833,9 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -4835,21 +4853,24 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); + tmpccer |= (OC_Config->OCPolarity << 12U); if(IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +#if defined(STM32F373xC) || defined(STM32F378xx) +#else /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; +#endif /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); + tmpcr2 |= (OC_Config->OCIdleState << 6U); } /* Write to TIMx CR2 */ @@ -4868,9 +4889,9 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -4919,7 +4940,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; @@ -5012,8 +5033,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -5033,7 +5054,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5058,8 +5079,8 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; @@ -5068,7 +5089,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5102,8 +5123,8 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5112,15 +5133,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); + tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5141,8 +5162,8 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5151,11 +5172,11 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5185,8 +5206,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -5199,11 +5220,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5233,8 +5254,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5243,15 +5264,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); + tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5275,7 +5296,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; @@ -5306,7 +5327,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; tmpsmcr = TIMx->SMCR; @@ -5314,7 +5335,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; @@ -5335,7 +5356,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, */ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim_ex.c index fd5cfb071dd7c64932d5daed6921adfa4e4ee5e3..b9adbab3d1b1d6fe982d73e1816cd4cab077d6e9 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -119,8 +119,8 @@ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) +#define BDTR_BKF_SHIFT (16U) +#define BDTR_BK2F_SHIFT (20U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ @@ -199,6 +199,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -249,7 +250,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ + register to 101U */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; @@ -347,7 +348,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance)); - /* Disable the Input Capture channels 1, 2 and 3 + /* Disable the Input Capture channels 1U, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -424,7 +425,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -442,7 +443,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - /* Enable the DMA channel for Capture 1*/ + /* Enable the DMA channel for Capture 1U*/ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); /* Enable the capture compare 1 Interrupt */ @@ -645,7 +646,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -729,7 +730,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1061,7 +1062,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1145,7 +1146,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U ) && (Length > 0U)) { return HAL_ERROR; } @@ -1800,7 +1801,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; } break; @@ -1834,7 +1835,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; } break; @@ -1868,7 +1869,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; } break; @@ -1912,7 +1913,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) { /* Check the parameters */ @@ -2005,7 +2006,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) { - uint32_t tmpbdtr = 0; + uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -2022,48 +2023,29 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - /* Clear the BDTR bits */ - tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | - TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | - TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF | - TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P); - - /* Set the BDTR bits */ - tmpbdtr |= sBreakDeadTimeConfig->DeadTime; - tmpbdtr |= sBreakDeadTimeConfig->LockLevel; - tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; - tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; - tmpbdtr |= sBreakDeadTimeConfig->BreakState; - tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; - tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; - tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); - tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT); - tmpbdtr |= sBreakDeadTimeConfig->Break2State; - tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity; - } - else - { - /* Clear the BDTR bits */ - tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI | - TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | - TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF); - - /* Set the BDTR bits */ - tmpbdtr |= sBreakDeadTimeConfig->DeadTime; - tmpbdtr |= sBreakDeadTimeConfig->LockLevel; - tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode; - tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode; - tmpbdtr |= sBreakDeadTimeConfig->BreakState; - tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity; - tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput; - tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT); + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } /* Set TIMx_BDTR */ @@ -2090,6 +2072,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { + uint32_t tmpbdtr = 0U; + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); @@ -2107,14 +2091,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | - sBreakDeadTimeConfig->OffStateIDLEMode | - sBreakDeadTimeConfig->LockLevel | - sBreakDeadTimeConfig->DeadTime | - sBreakDeadTimeConfig->BreakState | - sBreakDeadTimeConfig->BreakPolarity | - sBreakDeadTimeConfig->AutomaticOutput; + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; htim->State = HAL_TIM_STATE_READY; @@ -2125,7 +2114,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ - defined(STM32F303xC) || defined(STM32F358xx) + defined(STM32F303xC) || defined(STM32F358xx) || \ + defined(STM32F334x8) #if defined(STM32F303xE) || defined(STM32F398xx) /** * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities. @@ -2165,7 +2155,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3 * @retval HAL status */ -#else /* STM32F303xC || STM32F358xx */ +#elif defined(STM32F303xC) || defined(STM32F358xx) /** * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities. * @param htim: TIM handle. @@ -2195,6 +2185,28 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 * @retval HAL status */ +#else /* STM32F334x8 */ +/** + * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities. + * @param htim: TIM handle. + * @param Remap1: specifies the first TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock + * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 + * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO + * @param Remap2: specifies the second TIMremapping source (if any). + * This parameter can be one of the following values: + * @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 + * @retval HAL status + */ #endif /* STM32F303xE || STM32F398xx || */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2) { @@ -2215,17 +2227,17 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1 return HAL_OK; } #endif /* STM32F303xE || STM32F398xx || */ - /* STM32F303xC || STM32F358xx || */ + /* STM32F303xC || STM32F358xx || STM32F334x8 */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F303x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ defined(STM32F373xC) || defined(STM32F378xx) #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ - defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F303x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Configures the TIM1 and TIM16 Remapping input capabilities. @@ -2362,7 +2374,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); @@ -2424,12 +2436,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 1 */ + /* Enable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; } else { - /* Disable the Ocref clear feature for Channel 1 */ + /* Disable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; } } @@ -2438,12 +2450,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 2 */ + /* Enable the Ocref clear feature for Channel 2U */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; } else { - /* Disable the Ocref clear feature for Channel 2 */ + /* Disable the Ocref clear feature for Channel 2U */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; } } @@ -2452,12 +2464,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 3 */ + /* Enable the Ocref clear feature for Channel 3U */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; } else { - /* Disable the Ocref clear feature for Channel 3 */ + /* Disable the Ocref clear feature for Channel 3U */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; } } @@ -2466,12 +2478,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 4 */ + /* Enable the Ocref clear feature for Channel 4U */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; } else { - /* Disable the Ocref clear feature for Channel 4 */ + /* Disable the Ocref clear feature for Channel 4U */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; } } @@ -2480,12 +2492,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 1 */ + /* Enable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; } else { - /* Disable the Ocref clear feature for Channel 1 */ + /* Disable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; } } @@ -2494,12 +2506,12 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, { if(sClearInputConfig->ClearInputState != RESET) { - /* Enable the Ocref clear feature for Channel 1 */ + /* Enable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; } else { - /* Disable the Ocref clear feature for Channel 1 */ + /* Disable the Ocref clear feature for Channel 1U */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; } } @@ -2636,7 +2648,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) */ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp = TIM_CCER_CC1NE << Channel; @@ -2660,9 +2672,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; @@ -2682,14 +2694,14 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); + tmpccer |= (OC_Config->OCPolarity << 16U); if(IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); + tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -2713,9 +2725,9 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; @@ -2730,19 +2742,19 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); + tmpccer |= (OC_Config->OCPolarity << 20U); if(IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); + tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_alarm_template.c new file mode 100644 index 0000000000000000000000000000000000000000..0ab565df4130b43ad9ab57f3267486353a1fdd7a --- /dev/null +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_alarm_template.c @@ -0,0 +1,314 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_timebase_rtc_alarm_template.c + * @version V1.4.0 + * @date 16-December-2016 + * @brief HAL time base based on the hardware RTC_ALARM Template. + * + * This file override the native HAL time base functions (defined as weak) + * to use the RTC ALARM for time base generation: + * + Intializes the RTC peripheral to increment the seconds registers each 1ms + * + The alarm is configured to assert an interrupt when the RTC reaches 1ms + * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 + * + HSE (default), LSE or LSI can be selected as RTC clock source + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32f3xx_hal_timebase_rtc_alarm.c' + (#) Add this file and the RTC HAL drivers to your project and uncomment + HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h + + [..] + (@) HAL RTC alarm and HAL RTC wakeup drivers can�t be used with low power modes: + The wake up capability of the RTC may be intrusive in case of prior low power mode + configuration requiring different wake up sources. + Application/Example behavior is no more guaranteed + (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples + requiring low power modes + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Uncomment the line below to select the appropriate RTC Clock source for your application: + + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. + + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing + precision. + + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing + precision. + */ +#define RTC_CLOCK_SOURCE_HSE +/* #define RTC_CLOCK_SOURCE_LSE */ +/* #define RTC_CLOCK_SOURCE_LSI */ + +#ifdef RTC_CLOCK_SOURCE_HSE + #define RTC_ASYNCH_PREDIV 49U + #define RTC_SYNCH_PREDIV 4U +#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ + #define RTC_ASYNCH_PREDIV 0U + #define RTC_SYNCH_PREDIV 31U +#endif /* RTC_CLOCK_SOURCE_HSE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_HandleTypeDef hRTC_Handle; +/* Private function prototypes -----------------------------------------------*/ +void RTC_Alarm_IRQHandler(void); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the RTC_ALARMA as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) +{ + __IO uint32_t counter = 0U; + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + +#ifdef RTC_CLOCK_SOURCE_LSE + /* Configue LSE as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configue LSI as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configue HSE as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) + { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) + { + /* Enable RTC Clock */ + __HAL_RCC_RTC_ENABLE(); + /* The time base should be 1ms + Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK + HSE/32 as RTC clock and HSE 8MHz + Time base = ((49U + 1U) * (4U + 1U)) / 250kHz + = 1ms + LSE as RTC clock + Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz + = ~1ms + LSI as RTC clock + Time base = ((31U + 1U) * (0U + 1U)) / 32KHz + = 1ms + */ + hRTC_Handle.Instance = RTC; + hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; + hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; + hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; + hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + HAL_RTC_Init(&hRTC_Handle); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); + + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); + + counter = 0U; + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET) + { + if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ + { + return HAL_ERROR; + } + } + + hRTC_Handle.Instance->ALRMAR = 0x01U; + + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); + + /* Check if the Initialization mode is set */ + if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK; + counter = 0U; + while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ + { + return HAL_ERROR; + } + } + } + hRTC_Handle.Instance->DR = 0U; + hRTC_Handle.Instance->TR = 0U; + + hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); + + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U); + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + return HAL_OK; + } + } + return HAL_ERROR; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling RTC ALARM interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Disable RTC ALARM update Interrupt */ + __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling RTC ALARM interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Enable RTC ALARM Update interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief ALARM A Event Callback in non blocking mode + * @note This function is called when RTC_ALARM interrupt took place, inside + * RTC_Alarm_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc : RTC handle + * @retval None + */ +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + __IO uint32_t counter = 0U; + + HAL_IncTick(); + + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the Initialization mode */ + hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ + { + break; + } + } + + hrtc->Instance->DR = 0U; + hrtc->Instance->TR = 0U; + + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief This function handles RTC ALARM interrupt request. + * @param None + * @retval None + */ +void RTC_Alarm_IRQHandler(void) +{ + HAL_RTC_AlarmIRQHandler(&hRTC_Handle); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_wakeup_template.c new file mode 100644 index 0000000000000000000000000000000000000000..265a069e7ac27f9510230262578affdca0155f63 --- /dev/null +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_rtc_wakeup_template.c @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_timebase_rtc_wakeup_template.c + * @version V1.4.0 + * @date 16-December-2016 + * @brief HAL time base based on the hardware RTC_WAKEUP Template. + * + * This file overrides the native HAL time base functions (defined as weak) + * to use the RTC WAKEUP for the time base generation: + * + Intializes the RTC peripheral and configures the wakeup timer to be + * incremented each 1ms + * + The wakeup feature is configured to assert an interrupt each 1ms + * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback + * + HSE (default), LSE or LSI can be selected as RTC clock source + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32f3xx_hal_timebase_rtc_wakeup.c' + (#) Add this file and the RTC HAL drivers to your project and uncomment + HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h + + [..] + (@) HAL RTC alarm and HAL RTC wakeup drivers can�t be used with low power modes: + The wake up capability of the RTC may be intrusive in case of prior low power mode + configuration requiring different wake up sources. + Application/Example behavior is no more guaranteed + (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples + requiring low power modes + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Uncomment the line below to select the appropriate RTC Clock source for your application: + + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. + + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing + precision. + + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing + precision. + */ +#define RTC_CLOCK_SOURCE_HSE +/* #define RTC_CLOCK_SOURCE_LSE */ +/* #define RTC_CLOCK_SOURCE_LSI */ + +#ifdef RTC_CLOCK_SOURCE_HSE + #define RTC_ASYNCH_PREDIV 49U + #define RTC_SYNCH_PREDIV 4U +#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ + #define RTC_ASYNCH_PREDIV 0U + #define RTC_SYNCH_PREDIV 31U +#endif /* RTC_CLOCK_SOURCE_HSE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +RTC_HandleTypeDef hRTC_Handle; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_WKUP_IRQHandler(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the RTC_WKUP as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK + = 1ms + * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1) + = 1 ms + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) +{ + __IO uint32_t counter = 0U; + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + +#ifdef RTC_CLOCK_SOURCE_LSE + /* Configue LSE as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configue LSI as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configue HSE as RTC clock soucre */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) + { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) + { + /* Enable RTC Clock */ + __HAL_RCC_RTC_ENABLE(); + /* The time base should be 1ms + Time base = ((RTC_ASYNCH_PREDIV + 1U) * (RTC_SYNCH_PREDIV + 1U)) / RTC_CLOCK + HSE/32 as RTC clock and HSE 8MHz + Time base = ((49U + 1U) * (4U + 1U)) / 250kHz + = 1ms + LSE as RTC clock + Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz + = ~1ms + LSI as RTC clock + Time base = ((31U + 1U) * (0U + 1U)) / 32Khz + = 1ms + */ + hRTC_Handle.Instance = RTC; + hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; + hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; + hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; + hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + HAL_RTC_Init(&hRTC_Handle); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + + /* Disable the Wake-up Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT); + + /* Wait till RTC WUTWF flag is set */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET) + { + if(counter++ == (SystemCoreClock /48U)) + { + return HAL_ERROR; + } + } + + /* Clear PWR wake up Flag */ + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + + /* Clear RTC Wake Up timer Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); + + /* Configure the Wake-up Timer counter */ + hRTC_Handle.Instance->WUTR = 0U; + + /* Clear the Wake-up Timer clock source bits in CR register */ + hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS; + + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT); + + /* Enable the Wake-up Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); + + HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U); + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + return HAL_OK; + } + } + return HAL_ERROR; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling RTC_WKUP interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Disable WAKE UP TIMER Interrupt */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling RTC_WKUP interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Enable WAKE UP TIMER interrupt */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Wake Up Timer Event Callback in non blocking mode + * @note This function is called when RTC_WKUP interrupt took place, inside + * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc : RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + HAL_IncTick(); +} + +/** + * @brief This function handles WAKE UP TIMER interrupt request. + * @param None + * @retval None + */ +void RTC_WKUP_IRQHandler(void) +{ + HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_tim_template.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_tim_template.c new file mode 100644 index 0000000000000000000000000000000000000000..7b1dfcb62c6f714b67eee8241867e4c42fd063a1 --- /dev/null +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_timebase_tim_template.c @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_timebase_tim_template.c + * @version V1.4.0 + * @date 16-December-2016 + * @brief HAL time base based on the hardware TIM Template. + * + * This file override the native HAL time base functions (defined as weak) + * the TIM time base: + * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms + * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_TimeBase_TIM + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef TimHandle; +/* Private function prototypes -----------------------------------------------*/ +void TIM6_DAC_IRQHandler(void); +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + + /*Configure the TIM6 IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2U*HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + TimHandle.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + Period = [(TIM6CLK/1000U) - 1]. to have a (1U/1000U) s time base. + + Prescaler = (uwTimclock/1000000U - 1U) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + TimHandle.Init.Period = (1000000U / 1000U) - 1U; + TimHandle.Init.Prescaler = uwPrescalerValue; + TimHandle.Init.ClockDivision = 0U; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + return HAL_TIM_Base_Start_IT(&TimHandle); + } + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + HAL_IncTick(); +} + +/** + * @brief This function handles TIM interrupt request. + * @param None + * @retval None + */ +void TIM6_DAC_IRQHandler(void) +{ + HAL_TIM_IRQHandler(&TimHandle); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tsc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tsc.c index cfd482abbe4dbbeac36a6f0c6979d64fee9ec5d7..e0b7d601a963d7778d0e0a609c070a4d1234c4f9 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tsc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_tsc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and De-initialization @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) /* Set all functions */ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | htsc->Init.CTPulseLowLength | - (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | + (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) | htsc->Init.SpreadSpectrumPrescaler | htsc->Init.PulseGeneratorPrescaler | htsc->Init.MaxCountValue | @@ -844,14 +844,14 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc) */ static uint32_t TSC_extract_groups(uint32_t iomask) { - uint32_t groups = 0; + uint32_t groups = 0U; uint32_t idx; - for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++) + for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++) { - if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET) + if ((iomask & (0x0FU << (idx * 4U))) != RESET) { - groups |= ((uint32_t)1 << idx); + groups |= (1U << idx); } } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart.c index 4cee119d18427807e3fa66925d744d4c86f40835..1455f175a142eccc754b97e6e0ae000214639650 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -64,11 +64,12 @@ by calling the HAL_RS485Ex_Init() API. [..] - (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_UART_MspInit() API. - Three operation modes are available within this driver : + [..] + [..] Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -176,7 +177,6 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */ #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ /** @@ -186,14 +186,24 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions +/** @addtogroup UART_Private_Functions * @{ */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @} */ @@ -330,8 +340,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); @@ -385,11 +395,11 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_HDSEL; + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); @@ -405,8 +415,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) * @param huart: UART handle. * @param BreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) @@ -461,16 +471,16 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - huart->Instance->CR2 |= USART_CR2_LINEN; + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -485,8 +495,8 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe * @param Address: UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod: specifies the UART wakeup method. * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark * @note If the user resorts to idle line detection wake up, the Address parameter * is useless and ignored by the initialization function. * @note If the user resorts to address mark wake up, the address length detection @@ -535,8 +545,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { @@ -576,16 +586,16 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -598,7 +608,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: UART handle. * @retval None */ - __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -613,7 +623,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @param huart: UART handle. * @retval None */ - __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -638,10 +648,10 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) and Half duplex data transfers. (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) No-Blocking mode: The communication is performed using Interrupts + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts or DMA, These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when @@ -651,28 +661,51 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) No-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) No-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -691,12 +724,13 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t* tmp; + uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -707,27 +741,30 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + while(huart->TxXferCount > 0U) { huart->TxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pData += 2U; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); } } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -758,11 +795,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { uint16_t* tmp; uint16_t uhMask; + uint32_t tickstart = 0U; /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -773,6 +811,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + huart->RxXferSize = Size; huart->RxXferCount = Size; @@ -781,10 +822,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui uhMask = huart->Mask; /* as long as data have to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { huart->RxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -792,7 +833,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { tmp = (uint16_t*) pData ; *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2; + pData +=2U; } else { @@ -826,7 +867,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -845,7 +886,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -867,7 +908,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -885,17 +926,14 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - /* Process Unlocked */ __HAL_UNLOCK(huart); - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART Parity Error and Data Register not empty Interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); return HAL_OK; } @@ -917,15 +955,13 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check if UART instance supports continuous communication using DMA */ assert_param(IS_UART_DMA_INSTANCE(huart->Instance)); /* Check that a Tx process is not already ongoing */ if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -949,20 +985,22 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + /* Enable the UART transmit DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); + HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAT; - /* Process Unlocked */ __HAL_UNLOCK(huart); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else @@ -985,15 +1023,13 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t *tmp; - /* Check if UART instance supports continuous communication using DMA */ assert_param(IS_UART_DMA_INSTANCE(huart->Instance)); /* Check that a Rx process is not already ongoing */ if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } @@ -1016,16 +1052,24 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); + HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 |= USART_CR3_DMAR; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -1045,15 +1089,21 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - if(huart->gState == HAL_UART_STATE_BUSY_TX) + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) { /* Disable the UART DMA Tx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable the UART DMA Rx request */ - huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* Process Unlocked */ @@ -1075,15 +1125,19 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - huart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - /* Clear the Overrun flag before resumming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Enable the UART DMA Rx request */ - huart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* Process Unlocked */ @@ -1101,109 +1155,611 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { /* The Lock is not implemented on this API to allow the user application to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback() / HAL_UART_RxHalfCpltCallback (): - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is - generated if the DMA transfer interruption occurs at the middle or at the end of the stream - and the corresponding call back is executed. - */ + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ - /* Disable the UART Tx/Rx DMA requests */ - huart->Instance->CR3 &= ~USART_CR3_DMAT; - huart->Instance->CR3 &= ~USART_CR3_DMAR; + /* Stop UART DMA Tx request if ongoing */ + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - /* Abort the UART DMA tx channel */ - if(huart->hdmatx != NULL) + /* Abort the UART DMA Tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) { - HAL_DMA_Abort(huart->hdmatx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + + UART_EndRxTransfer(huart); } - /* Abort the UART DMA rx channel */ - if(huart->hdmarx != NULL) + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - HAL_DMA_Abort(huart->hdmarx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmatx); + } } - huart->gState = HAL_UART_STATE_READY; + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmarx); + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + /* Reset Handle ErrorCode to No Error */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + return HAL_OK; } /** - * @brief Handle UART interrupt request. - * @param huart: UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { - /* UART parity error interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmatx); + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmarx); + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; - huart->ErrorCode |= HAL_UART_ERROR_PE; + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } } - /* UART frame error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + /* Disable the UART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->ErrorCode |= HAL_UART_ERROR_FE; + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } } - /* UART noise error interrupt occurred --------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - huart->ErrorCode |= HAL_UART_ERROR_NE; + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } } - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - huart->ErrorCode |= HAL_UART_ERROR_ORE; + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); } - /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - HAL_UARTEx_WakeupCallback(huart); + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart: UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } } - /* UART in mode Receiver ---------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) + /* If some errors occur */ + cr3its = READ_REG(huart->Instance->CR3); + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) { - UART_Receive_IT(huart); + /* UART parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_UART_ErrorCallback(huart); + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) + { + __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); + /* Set the UART state ready to be able to start again the process */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + HAL_UARTEx_WakeupCallback(huart); + return; } /* UART in mode Transmitter ------------------------------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { UART_Transmit_IT(huart); + return; } /* UART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); + return; } - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* Set the UART state ready to be able to start again the Tx/Rx process */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - HAL_UART_ErrorCallback(huart); - } } /** @@ -1211,7 +1767,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) * @param huart: UART handle. * @retval None */ - __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -1226,7 +1782,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) * @param huart: UART handle. * @retval None */ - __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -1271,7 +1827,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) * @param huart: UART handle. * @retval None */ - __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); @@ -1281,6 +1837,51 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) */ } +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -1318,7 +1919,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - huart->Instance->CR1 |= USART_CR1_MME; + SET_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -1339,7 +1940,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - huart->Instance->CR1 &= ~(USART_CR1_MME); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -1430,6 +2031,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) return HAL_OK; } + + /** * @} */ @@ -1458,7 +2061,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1= 0x00, temp2 = 0x00; + uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = huart->gState; temp2 = huart->RxState; @@ -1470,7 +2073,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code -*/ + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -1494,10 +2097,10 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; + uint32_t tmpreg = 0x00000000U; UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; HAL_StatusTypeDef ret = HAL_OK; /* Check the parameters */ @@ -1564,8 +2167,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) break; } - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); huart->Instance->BRR = brrtemp; } else @@ -1609,55 +2212,55 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); } /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); } /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); } /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); } /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); } /* if required, configure auto Baud rate detection scheme */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); /* set auto Baudrate detection parameters if detection is enabled */ - if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); @@ -1665,7 +2268,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) } /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); @@ -1674,19 +2277,24 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /** * @brief Check the UART Idle State. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { + uint32_t tickstart = 0U; + /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Check if the Transmitter is enabled */ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout Occured */ return HAL_TIMEOUT; @@ -1696,7 +2304,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { /* Timeout Occured */ return HAL_TIMEOUT; @@ -1704,8 +2312,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1713,95 +2321,93 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_OK; } - /** * @brief Handle UART Communication Timeout. - * @param huart: UART handle. - * @param Flag: specifies the UART flag to check. - * @param Status: the Flag status (SET or RESET). - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { - while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(huart); + return HAL_TIMEOUT; } } } - else - { - while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + return HAL_OK; +} - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; } + /** * @brief DMA UART transmit process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -1813,33 +2419,37 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART transmit process half complete callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); HAL_UART_TxHalfCpltCallback(huart); } /** * @brief DMA UART receive process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -1850,37 +2460,194 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process half complete callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); HAL_UART_RxHalfCpltCallback(huart); } /** * @brief DMA UART communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + + /* Stop UART DMA Tx request if ongoing */ + if ( (huart->gState == HAL_UART_STATE_BUSY_TX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) + &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(huart->hdmarx != NULL) + { + if(huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(huart->hdmatx != NULL) + { + if(huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +} + /** * @brief Send an amount of data in interrupt mode. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) @@ -1890,14 +2657,13 @@ HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - - if(huart->TxXferCount == 0) + if(huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); return HAL_OK; } @@ -1906,14 +2672,13 @@ HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + huart->pTxBuffPtr += 2U; } else { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU); } - huart->TxXferCount--; return HAL_OK; @@ -1925,17 +2690,16 @@ HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) } } - /** * @brief Wrap up transmission in non-blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -1945,43 +2709,41 @@ HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) return HAL_OK; } - /** * @brief Receive an amount of data in interrupt mode. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint16_t uhMask = huart->Mask; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; /* Check that a Rx process is ongoing */ if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - huart->pRxBuffPtr +=2; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr +=2U; } else { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); } - if(--huart->RxXferCount == 0) + if(--huart->RxXferCount == 0U) { - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -2003,10 +2765,10 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } /** - * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: UART handle - * @param WakeUpSelection: UART wake up from stop mode parameters - * @retval HAL status + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart: UART handle. + * @param WakeUpSelection: UART wake up from stop mode parameters. + * @retval None */ void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { @@ -2019,7 +2781,6 @@ void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef Wak MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } - /** * @} */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart_ex.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart_ex.c index 0549c4bbfb77ecfcb2b99d95dccb2bdccf9fef67..0bc2d7264b956868d428d48e7f87011cfebfa91e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart_ex.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_uart_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Extended UART HAL module driver. * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). @@ -156,8 +156,8 @@ * @param huart: UART handle. * @param Polarity: select the driver enable polarity. * This parameter can be one of the following values: - * @arg UART_DE_POLARITY_HIGH: DE signal is active high - * @arg UART_DE_POLARITY_LOW: DE signal is active low + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low * @param AssertionTime: Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time @@ -171,7 +171,7 @@ */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { - uint32_t temp = 0x0; + uint32_t temp = 0x0U; /* Check the UART handle allocation */ if(huart == NULL) @@ -258,17 +258,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /** - * @brief UART wakeup from Stop mode callback - * @param huart: UART handle + * @brief UART wakeup from Stop mode callback. + * @param huart: UART handle. * @retval None */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file + the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @verbatim =============================================================================== - ##### Peripheral Control function ##### + ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides extended functions allowing to control the UART. @@ -301,14 +301,15 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @param huart: UART handle. * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. * This parameter can be one of the following values: - * @arg UART_WAKEUP_ON_ADDRESS - * @arg UART_WAKEUP_ON_STARTBIT - * @arg UART_WAKEUP_ON_READDATA_NONEMPTY + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = 0U; /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); @@ -334,8 +335,11 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } @@ -414,8 +418,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. * @param huart: UART handle. * @param AddressLength: this parameter can be one of the following values: - * @arg UART_ADDRESS_DETECT_4B: 4-bit long address - * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_usart.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_usart.c index 0215b212cf1ea75ceea2db3c4a6d86e92db858c4..2d50e48df2d9ded84c1f74bfd4d377ed26844828 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_usart.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_usart.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter @@ -47,7 +47,7 @@ flow control and Mode (Receiver/Transmitter) in the husart handle Init structure. (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_USART_MspInit(&husart) API. (#) Three operation modes are available within this driver : @@ -107,6 +107,10 @@ [..] (@) You can refer to the USART HAL driver header file for more useful macros + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. @endverbatim ****************************************************************************** @@ -158,10 +162,8 @@ /** @defgroup USART_Private_Constants USART Private Constants * @{ */ -#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ -#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ -#define USART_TXDMA_TIMEOUTVALUE 22000 -#define USART_TIMEOUT_VALUE 22000 +#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ @@ -173,15 +175,19 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup USART_Private_Functions USART Private Functions +/** @addtogroup USART_Private_Functions * @{ */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); @@ -264,9 +270,9 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); */ /** - * @brief Initializes the USART mode according to the specified + * @brief Initialize the USART mode according to the specified * parameters in the USART_InitTypeDef and initialize the associated handle. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) @@ -315,12 +321,12 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /** * @brief DeInitialize the USART peripheral. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ + /* Check the USART handle allocation */ if(husart == NULL) { return HAL_ERROR; @@ -331,9 +337,9 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - husart->Instance->CR1 = 0x0; - husart->Instance->CR2 = 0x0; - husart->Instance->CR3 = 0x0; + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); @@ -352,7 +358,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart: USART handle. * @retval None */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -367,7 +373,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @param husart: USART handle. * @retval None */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -382,7 +388,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions + * @brief USART Transmit and Receive functions * @verbatim =============================================================================== @@ -408,18 +414,18 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode APIs are : - (++) HAL_USART_Transmit()in simplex mode + (++) HAL_USART_Transmit() in simplex mode (++) HAL_USART_Receive() in full duplex receive only (++) HAL_USART_TransmitReceive() in full duplex mode (#) No-Blocking mode APIs with Interrupt are : - (++) HAL_USART_Transmit_IT()in simplex mode + (++) HAL_USART_Transmit_IT() in simplex mode (++) HAL_USART_Receive_IT() in full duplex receive only (++) HAL_USART_TransmitReceive_IT()in full duplex mode (++) HAL_USART_IRQHandler() (#) No-Blocking mode APIs with DMA are : - (++) HAL_USART_Transmit_DMA()in simplex mode + (++) HAL_USART_Transmit_DMA() in simplex mode (++) HAL_USART_Receive_DMA() in full duplex receive only (++) HAL_USART_TransmitReceive_DMA() in full duplex mode (++) HAL_USART_DMAPause() @@ -434,25 +440,44 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) (++) HAL_USART_ErrorCallback() (++) HAL_USART_TxRxCpltCallback() + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + @endverbatim * @{ */ /** * @brief Simplex send an amount of data in blocking mode. - * @param husart: USART handle. - * @param pTxData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @param husart USART handle. + * @param pTxData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp=0U; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -463,34 +488,38 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + husart->TxXferSize = Size; husart->TxXferCount = Size; /* Check the remaining data to be sent */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pTxData += 2; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + pTxData += 2U; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU); } } - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } + /* At end of Tx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; /* Process Unlocked */ @@ -507,29 +536,34 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @param husart: USART handle. - * @param pRxData: Pointer to data buffer. - * @param Size: Amount of data to be received. - * @param Timeout: Timeout duration. + * @param husart USART handle. + * @param pRxData Pointer to data buffer. + * @param Size Amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp=0U; uint16_t uhMask; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + husart->RxXferSize = Size; husart->RxXferCount = Size; @@ -538,7 +572,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat uhMask = husart->Mask; /* as long as data have to be received */ - while(husart->RxXferCount > 0) + while(husart->RxXferCount > 0U) { husart->RxXferCount--; @@ -546,14 +580,14 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * clock for the slave to send data. * Whatever the frame length (7, 8 or 9-bit long), the same dummy value * can be written for all the cases. */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU); /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -562,7 +596,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2U; } else { @@ -570,6 +604,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat } } + /* At end of Rx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; /* Process Unlocked */ @@ -585,30 +620,35 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @param husart: USART handle. - * @param pTxData: pointer to TX data buffer. - * @param pRxData: pointer to RX data buffer. - * @param Size: amount of data to be sent (same amount to be received). - * @param Timeout: Timeout duration. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer. + * @param pRxData pointer to RX data buffer. + * @param Size amount of data to be sent (same amount to be received). + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp=0U; uint16_t uhMask; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + husart->RxXferSize = Size; husart->TxXferSize = Size; husart->TxXferCount = Size; @@ -619,13 +659,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t uhMask = husart->Mask; /* Check the remain data to be sent */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; husart->RxXferCount--; /* Wait until TC flag is set to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -633,7 +673,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pTxData; husart->Instance->TDR = (*tmp & uhMask); - pTxData += 2; + pTxData += 2U; } else { @@ -641,7 +681,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t } /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -650,7 +690,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2U; } else { @@ -658,6 +698,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t } } + /* At end of TxRx process, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; /* Process Unlocked */ @@ -673,16 +714,16 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. - * @param husart: USART handle. - * @param pTxData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param husart USART handle. + * @param pTxData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -718,21 +759,22 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Receive an amount of data in blocking mode. + * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @param husart: USART handle. - * @param pRxData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param husart USART handle. + * @param pRxData pointer to data buffer. + * @param Size amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -745,27 +787,23 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - - /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - /* Process Unlocked */ __HAL_UNLOCK(husart); + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Send dummy byte in order to generate the clock for the Slave to send the next data */ if(husart->Init.WordLength == USART_WORDLENGTH_9B) { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF); + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU); } else { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU); } return HAL_OK; @@ -778,10 +816,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @param husart: USART handle. - * @param pTxData: pointer to TX data buffer. - * @param pRxData: pointer to RX data buffer. - * @param Size: amount of data to be sent (same amount to be received). + * @param husart USART handle. + * @param pTxData pointer to TX data buffer. + * @param pRxData pointer to RX data buffer. + * @param Size amount of data to be sent (same amount to be received). * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -789,10 +827,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -809,20 +848,17 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - - /* Enable the USART Parity Error Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_PE); + /* Process Unlocked */ + __HAL_UNLOCK(husart); /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -830,29 +866,29 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { return HAL_BUSY; } - } /** * @brief Send an amount of data in DMA mode. - * @param husart: USART handle. - * @param pTxData: pointer to data buffer. - * @param Size: amount of data to be sent. - * @note This function starts a DMA transfer in interrrupt mode meaning that + * @param husart USART handle. + * @param pTxData pointer to data buffer. + * @param Size amount of data to be sent. + * @note This function starts a DMA transfer in interrupt mode meaning that * DMA half transfer complete, DMA transfer complete and DMA transfer * error interrupts are enabled * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { - uint32_t *tmp=0; + uint32_t *tmp=0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -879,13 +915,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /* Clear the TC flag in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; - /* Process Unlocked */ __HAL_UNLOCK(husart); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else @@ -896,13 +932,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Receive an amount of data in DMA mode. - * @param husart: USART handle. - * @param pRxData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param husart USART handle. + * @param pRxData pointer to data buffer. + * @param Size amount of data to be received. * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * the parity bit (MSB position). * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note This function starts a DMA transfer in interrrupt mode meaning that + * @note This function starts a DMA transfer in interrupt mode meaning that * DMA half transfer complete, DMA transfer complete and DMA transfer * error interrupts are enabled * @retval HAL status @@ -911,9 +947,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR { uint32_t *tmp; + /* Check that a Rx process is not already ongoing */ if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -945,19 +982,28 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Enable the USART transmit DMA channel: the transmit channel is used in order to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ - tmp = (uint32_t*)&pRxData; + /* Set the USART DMA Tx Complete and Error callback to Null */ + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -969,12 +1015,12 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param husart: USART handle. - * @param pTxData: pointer to TX data buffer. - * @param pRxData: pointer to RX data buffer. - * @param Size: amount of data to be received/sent. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer. + * @param pRxData pointer to RX data buffer. + * @param Size amount of data to be received/sent. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note This function starts a 2 DMA transfers in interrrupt mode meaning that + * @note This function starts a 2 DMA transfers in interrupt mode meaning that * DMA half transfer complete, DMA transfer complete and DMA transfer * error interrupts are enabled * @retval HAL status @@ -985,10 +1031,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + /* Process Locked */ __HAL_LOCK(husart); @@ -1026,19 +1073,25 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Clear the TC flag in the ICR register */ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 |= USART_CR3_DMAT; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1050,7 +1103,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /** * @brief Pause the DMA Transfer. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) @@ -1058,22 +1111,29 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /* Process Locked */ __HAL_LOCK(husart); - if(husart->State == HAL_USART_STATE_BUSY_TX) + if( (husart->State == HAL_USART_STATE_BUSY_TX) && + (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))) { /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - } - else if(husart->State == HAL_USART_STATE_BUSY_RX) - { - /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) + else if( (husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) { - /* Disable the USART DMA Tx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT); - /* Disable the USART DMA Rx request */ - husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the USART DMA Tx request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the USART DMA Rx request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } } /* Process Unlocked */ @@ -1084,7 +1144,7 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /** * @brief Resume the DMA Transfer. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) @@ -1095,26 +1155,23 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - else if(husart->State == HAL_USART_STATE_BUSY_RX) + else if( (husart->State == HAL_USART_STATE_BUSY_RX) || + (husart->State == HAL_USART_STATE_BUSY_TX_RX) ) { - /* Clear the Overrun flag before resumming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); - /* Enable the USART DMA Rx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; - } - else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART DMA Rx request before the DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAR; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Enable the USART DMA Tx request */ - husart->Instance->CR3 |= USART_CR3_DMAT; + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); } /* Process Unlocked */ @@ -1125,7 +1182,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /** * @brief Stop the DMA Transfer. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) @@ -1139,8 +1196,8 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ /* Disable the USART Tx/Rx DMA requests */ - husart->Instance->CR3 &= ~USART_CR3_DMAT; - husart->Instance->CR3 &= ~USART_CR3_DMAR; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA tx channel */ if(husart->hdmatx != NULL) @@ -1153,76 +1210,355 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) HAL_DMA_Abort(husart->hdmarx); } + USART_EndTransfer(husart); husart->State = HAL_USART_STATE_READY; return HAL_OK; } /** - * @brief Handle USART interrupt request. - * @param husart: USART handle. - * @retval None - */ -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* USART parity error interrupt occurred ------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - husart->ErrorCode |= HAL_USART_ERROR_PE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(husart->hdmatx); + } } - /* USART frame error interrupt occurred -------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - husart->ErrorCode |= HAL_USART_ERROR_FE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(husart->hdmarx); + } } - /* USART noise error interrupt occurred -------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(husart->hdmatx != NULL) { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - husart->ErrorCode |= HAL_USART_ERROR_NE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } } - - /* USART Over-Run interrupt occurred ----------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) + /* DMA Rx Handle is valid */ + if(husart->hdmarx != NULL) { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - husart->ErrorCode |= HAL_USART_ERROR_ORE; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } } - /* Call USART Error Call back function if need be --------------------------*/ - if(husart->ErrorCode != HAL_USART_ERROR_NONE) + /* Disable the USART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { - HAL_USART_ErrorCallback(husart); + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } } - /* USART in mode Receiver --------------------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET)) + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { - if(husart->State == HAL_USART_STATE_BUSY_RX) + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(husart->hdmarx != NULL) { - USART_Receive_IT(husart); + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } } - else + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == RESET) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) { - USART_TransmitReceive_IT(husart); + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + return; } } - /* USART in mode Transmitter -----------------------------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET)) + /* If some errors occur */ + cr3its = READ_REG(husart->Instance->CR3); + if( (errorflags != RESET) + && ( ((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if(((isrflags & USART_ISR_ORE) != RESET) && + (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* Call USART Error Call back function if need be --------------------------*/ + if(husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || + (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + + /* Abort the USART DMA Tx channel */ + if(husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_USART_ErrorCallback(husart); + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { if(husart->State == HAL_USART_STATE_BUSY_TX) { @@ -1232,12 +1568,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { USART_TransmitReceive_IT(husart); } + return; } /* USART in mode Transmitter (transmission end) -----------------------------*/ - if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) + if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); + return; } } @@ -1259,10 +1597,10 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callback. - * @param husart: USART handle + * @param husart: USART handle. * @retval None */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); @@ -1304,7 +1642,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: USART handle + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1332,6 +1670,21 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) */ } +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -1395,222 +1748,41 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) @endverbatim * @{ */ - /** - * @brief Configure the USART peripheral. - * @param husart: USART handle. - * @retval HAL status + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None */ -static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +static void USART_EndTransfer(USART_HandleTypeDef *husart) { - uint32_t tmpreg = 0x0; - USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; + /* Disable TXEIE and TCIE interrupts */ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Check the parameters */ - assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); - assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); - assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); - assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); - assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); - assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); - assert_param(IS_USART_PARITY(husart->Init.Parity)); - assert_param(IS_USART_MODE(husart->Init.Mode)); + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity and Mode: - * set the M bits according to husart->Init.WordLength value - * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ - tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; - MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: - * set CPOL bit according to husart->Init.CLKPolarity value - * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value - * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = (uint32_t)(USART_CLOCK_ENABLE); - tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); - tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); - MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* no CR3 register configuration */ - - /*-------------------------- USART BRR Configuration -----------------------*/ - /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ - USART_GETCLOCKSOURCE(husart, clocksource); - switch (clocksource) - { - case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); - husart->Instance->BRR = brrtemp; - - return ret; -} - -/** - * @brief Check the USART Idle State. - * @param husart: USART handle. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) -{ - /* Initialize the USART ErrorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Check if the Transmitter is enabled */ - if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout Occured */ - return HAL_TIMEOUT; - } - } - - /* REACK bit in ISR is checked only when available (not to be checked on all instances). - Bit is defined only for USART instances supporting WakeUp from Stop Mode feature. - */ - if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance)) - { - /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - } - - /* Initialize the USART state*/ - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - - -/** - * @brief Handle USART Communication Timeout. - * @param husart: USART handle. - * @param Flag: specifies the USART flag to check. - * @param Status: the Flag status (SET or RESET). - * @param Timeout: timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - husart->State= HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - - -/** - * @brief DMA USART transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - husart->TxXferCount = 0; + husart->TxXferCount = 0U; if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ - husart->Instance->CR3 &= ~(USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); @@ -1626,39 +1798,42 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) } } - /** * @brief DMA USART transmit process half complete callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); HAL_USART_TxHalfCpltCallback(husart); } /** * @brief DMA USART receive process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); /* DMA Normal mode */ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { - husart->RxXferCount = 0; + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit in USART CR3 register */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* similarly, disable the DMA TX transfer that was started to provide the clock to the slave device */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); if(husart->State == HAL_USART_STATE_BUSY_RX) { @@ -1689,12 +1864,12 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART receive process half complete callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); HAL_USART_RxHalfCpltCallback(husart); } @@ -1706,32 +1881,302 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void USART_DMAError(DMA_HandleTypeDef *hdma) { - USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); - husart->RxXferCount = 0; - husart->TxXferCount = 0; husart->ErrorCode |= HAL_USART_ERROR_DMA; husart->State= HAL_USART_STATE_READY; HAL_USART_ErrorCallback(husart); } +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + + HAL_USART_ErrorCallback(husart); +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(husart->hdmarx != NULL) + { + if(husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(husart->hdmatx != NULL) + { + if(husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); +} + + +/** + * @brief Handle USART Communication Timeout. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief Configure the USART peripheral. + * @param husart: USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg = 0x0U; + USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp = 0x0000U; + uint16_t usartdiv = 0x0000U; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* no CR3 register configuration */ + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart: USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart = 0U; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout Occured */ + return HAL_TIMEOUT; + } + } + + /* REACK bit in ISR is checked only when available (not to be checked on all instances). + Bit is defined only for USART instances supporting WakeUp from Stop Mode feature. + */ + if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance)) + { + /* Check if the Receiver is enabled */ + if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + } + + /* Initialize the USART state*/ + husart->State= HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + + /** * @brief Simplex send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Transmit_IT(). * @note The USART errors are not managed to avoid the overrun error. - * @param husart: USART handle. + * @param husart USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; + uint16_t* tmp=0U; + /* Check that a Tx process is ongoing */ if(husart->State == HAL_USART_STATE_BUSY_TX) { - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); @@ -1746,12 +2191,12 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - husart->pTxBuffPtr += 2; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); + husart->pTxBuffPtr += 2U; } else { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU); } husart->TxXferCount--; @@ -1768,7 +2213,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) /** * @brief Wraps up transmission in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart Pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1780,6 +2225,7 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + /* Tx process is ended, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; HAL_USART_TxCpltCallback(husart); @@ -1792,12 +2238,12 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) * @brief Simplex receive an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Receive_IT(). - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; + uint16_t* tmp=0U; uint16_t uhMask = husart->Mask; if(husart->State == HAL_USART_STATE_BUSY_RX) @@ -1807,7 +2253,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { @@ -1815,18 +2261,17 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) } /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU); - if(--husart->RxXferCount == 0) + if(--husart->RxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - - /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); @@ -1851,13 +2296,13 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; + uint16_t* tmp=0U; uint16_t uhMask = husart->Mask; if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { - if(husart->TxXferCount != 0x00) + if(husart->TxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) { @@ -1865,7 +2310,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & uhMask); - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; } else { @@ -1874,14 +2319,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) husart->TxXferCount--; /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); } } } - if(husart->RxXferCount != 0x00) + if(husart->RxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) { @@ -1889,7 +2334,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { @@ -1900,16 +2345,15 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } /* Check the latest data received */ - if(husart->RxXferCount == 0) + if(husart->RxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - - /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + /* Rx process is completed, restore husart->State to Ready */ husart->State = HAL_USART_STATE_READY; HAL_USART_TxRxCpltCallback(husart); diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_wwdg.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_wwdg.c index 699dc3a7fe4da6173f8f1fb8959389a71d03ca23..e93125c8efcd05067adf7d99bcb6b2f440009754 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_wwdg.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_wwdg.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -15,9 +15,9 @@ ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (T[6;0] downcounter) + time period, unless the program refreshes the counter (T[6U;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). + value rolls over from 0x40 to 0x3FU). (+) An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This @@ -31,20 +31,20 @@ (+) The WWDG downcounter input clock is derived from the APB clock divided by a programmable prescaler. - (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler) - (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock) - where T[5;0] are the lowest 6 bits of downcounter. + (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock) + where T[5U;0] are the lowest 6 bits of downcounter. (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock) - (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock) + (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock) + (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock) (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms (+) The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is - generated. When the downcounter reaches the value 0x40, an EWI interrupt + generated. When the downcounter reaches the value 0x40U, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_adc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_adc.c index c82735b130f2bcfbce287c8d3474945cba194230..9c66d1c452aba82cf1a611750c112c732d4667cb 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_adc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_adc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief ADC LL module driver ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_comp.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_comp.c index 51b02c4e6f0c2ecef7e5817efc650944ef8bc4e4..26e5f330b4b37a08b451a78f2b4ac62426523fe3 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_comp.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_comp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_comp.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief COMP LL module driver ****************************************************************************** * @attention @@ -55,7 +55,7 @@ /* (comparator output blanking, ...) (refer to reference manual). */ /* - STM32F37x: */ /* COMP IP with 2 instances */ -/* This file contains the drivers of these ADC IP, located in 2 area */ +/* This file contains the drivers of these COMP IP, located in 2 area */ /* delimited by compilation switches. */ #if defined(COMP_V1_3_0_0) @@ -131,7 +131,7 @@ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) #endif -#if defined(STM32F301x8) || defined(STM32F318xx) +#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -139,9 +139,12 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ ) -#else +#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ @@ -151,6 +154,31 @@ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \ + ) +#elif defined(STM32F302xC) || defined(STM32F302xE) +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ + ) +#else /* STM32F301x8 || STM32F318xx || STM32F302x8 */ +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ ) #endif @@ -179,7 +207,7 @@ (((__COMP_INSTANCE__) == COMP2) \ ? ( \ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC4_COMP2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \ ) \ @@ -213,7 +241,7 @@ ? ( \ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC4_COMP2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \ @@ -250,7 +278,7 @@ ? ( \ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC4_COMP1_2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \ @@ -293,7 +321,7 @@ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC4_COMP1_2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \ ) \ : \ @@ -370,7 +398,7 @@ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC4_COMP1_2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \ || (((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_OCCLR_COMP2) \ && ((__COMP_INSTANCE__) == COMP2) ) \ @@ -782,6 +810,10 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \ ) #define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ @@ -791,6 +823,9 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \ ) +/* Note: Output redirection is specific to COMP instances but is checked */ +/* with literals of instance COMP2 (no differentiation possible since */ +/* literals of COMP1 and COMP2 share the same values range). */ #define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__) \ ( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \ @@ -798,8 +833,8 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4) \ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1) \ - || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \ + || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2) \ ) #define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_crc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_crc.c index fc7096bf072418d3629a4e373511eb2b2489b83c..46bb177f2fa86cad5edbecaafd6f69c1adca465d 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_crc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_crc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief CRC LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dac.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dac.c index e46d6f61d77ef5e4ce9053598a28c2b610d0a8ff..ff31f9412c3e5b8a30e1c2b205fdac2577bcb72f 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dac.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_dac.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief DAC LL module driver ****************************************************************************** * @attention @@ -40,7 +40,7 @@ #include "stm32f3xx_ll_dac.h" #include "stm32f3xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) @@ -232,7 +232,6 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2); } #endif - return SUCCESS; } diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dma.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dma.c index 3c9be74e99599d4183bc1fab91cc6b4428c3730a..ce9305fc8a17637db9cd79bcb495a105df83cf1b 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dma.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_dma.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief DMA LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_exti.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_exti.c index 21ba49c060fae0277999eb1d429e1082955d1975..86ccfdbb014597996fcb83744b0a1958fd2ab127 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_exti.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_exti.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_exti.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief EXTI LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_fmc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_fmc.c index 3c9911505cd3c0e523f92dfe2258ca1fbda83817..6be0d111782bcf891adacfa6fc293a8f8e20fd54 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_fmc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_fmc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_gpio.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_gpio.c index f828205475298ed235bb65cd6b591aa04cf7d599..977e4e94db3ee4e3c4266879c5a66aec1e007a71 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_gpio.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_gpio.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief GPIO LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_hrtim.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_hrtim.c index 9f89f716c6a5876f3347f7c2ff5f5070dc22c694..881c12392bcd326480149c99c9f58be0667442cf 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_hrtim.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_hrtim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_hrtim.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief HRTIM LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_i2c.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_i2c.c index 17a6b5ad42521d987e1eeda5ec9f29637a0be026..0c65fd835c110a274ba238135cceec37a578442c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_i2c.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_i2c.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief I2C LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_opamp.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_opamp.c index 3af784c1e86548b33e33b803cbb468c7720d30d6..270dd526b58b1db675aee4209a90992c00298496 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_opamp.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_opamp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_opamp.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief OPAMP LL module driver ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_pwr.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_pwr.c index 0ef7534b5de037f567614c5d04bfc3444e0bca99..109091baeac4ab144357b93445090cc983b3239c 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_pwr.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_pwr.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rcc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rcc.c index d85ead325e61d9c6c5c58ac463bd1031dd157f69..4aea844944afc10f0b6319ab965a4d8fc43938ca 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rcc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_rcc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -61,9 +61,9 @@ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) const uint16_t aADCPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}; -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ /** * @} */ @@ -133,9 +133,9 @@ const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, #endif /* RCC_CFGR2_ADC1PRES */ #endif /* RCC_CFGR_ADCPRE */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) #define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE)) -#endif /* RCC_CFGR_SDADCPRE */ +#endif /* RCC_CFGR_SDPRE */ #if defined(CEC) #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) @@ -615,7 +615,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) return i2c_frequency; } -#if defined(RCC_CFGR_I2SSRC) +#if defined(RCC_CFGR_I2SSRC) /** * @brief Return I2Sx clock frequency * @param I2SxSource This parameter can be one of the following values: @@ -644,8 +644,7 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) return i2s_frequency; } -#endif /*RCC_CFGR_I2SSRC*/ - +#endif /* RCC_CFGR_I2SSRC */ #if defined(USB) /** * @brief Return USBx clock frequency @@ -730,7 +729,7 @@ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) } #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ -#if defined(RCC_CFGR_SDADCPRE) +#if defined(RCC_CFGR_SDPRE) /** * @brief Return SDADCx clock frequency * @param SDADCxSource This parameter can be one of the following values: @@ -754,7 +753,7 @@ uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource) return sdadc_frequency; } -#endif /*RCC_CFGR_SDADCPRE */ +#endif /*RCC_CFGR_SDPRE */ #if defined(CEC) /** diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rtc.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rtc.c index 6541f8eddb2a09bd6eb900524b824a8c659cd9fa..6b4ad4ffe560af3cfd332b3b2bae6a058478a710 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rtc.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_rtc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief RTC LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_spi.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_spi.c index e078bd1c1adade6404f252f6a704648b689249d7..d6effcb62480cdb1e79efe70622d007b0fb41ccd 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_spi.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_spi.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief SPI LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_tim.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_tim.c index d0bd6351149e153694110e5391468ed8f9d9a698..9b330bc246444b85bfdb415b9820122b4722c24f 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_tim.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_tim.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief TIM LL module driver. ****************************************************************************** * @attention @@ -144,6 +144,70 @@ #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) +#if defined(TIM_BDTR_BKF) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) +#endif /* TIM_BDTR_BKF */ +#if defined(TIM_BDTR_BK2E) + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) +#endif /* TIM_BDTR_BK2E */ + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -704,6 +768,100 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType } #endif /* TIM_CR2_MMS2 */ +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; +#if defined(TIM_BDTR_BKF) + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; +#endif /* TIM_BDTR_BKF */ +#if defined(TIM_BDTR_BK2E) + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +#endif /* TIM_BDTR_BK2E */ +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); +#if defined(TIM_BDTR_BKF) + if (IS_TIM_ADVANCED_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + } +#endif /* TIM_BDTR_BKF */ +#if defined(TIM_BDTR_BK2E) + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + } +#endif /* TIM_BDTR_BK2E */ + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} /** * @} */ @@ -855,8 +1013,11 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); +#if defined(STM32F373xC) || defined(STM32F378xx) +#else /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); +#endif } /* Write to TIMx CR2 */ @@ -931,11 +1092,14 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni /* Set the complementary output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); +#if defined(STM32F373xC) || defined(STM32F378xx) +#else /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); +#endif } /* Write to TIMx CR2 */ @@ -1004,8 +1168,11 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); +#if defined(STM32F373xC) || defined(STM32F378xx) +#else /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); +#endif } /* Write to TIMx CR2 */ diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_usart.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_usart.c index 82a0d30ff9e6064d3d441cf4bd57b2e07399db07..8c9f982ce7eaa5398c3c7205a3f6c1b6676d39ec 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_usart.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_usart.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief USART LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_utils.c b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_utils.c index 02f5e5a1900f1abcdd918da87dace61af3611456..f4f934836985ed170b7a42c3241b7f7f97a0199e 100644 --- a/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_utils.c +++ b/stm32cube/stm32f3xx/drivers/src/stm32f3xx_ll_utils.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_ll_utils.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief UTILS LL module driver. ****************************************************************************** * @attention diff --git a/stm32cube/stm32f3xx/soc/stm32f301x8.h b/stm32cube/stm32f3xx/soc/stm32f301x8.h index eda579730a3ffd6be3f4cccff96d9dff6c53678c..bca87b69576420e9fa1d2c00d8ef636c216bcbd6 100644 --- a/stm32cube/stm32f3xx/soc/stm32f301x8.h +++ b/stm32cube/stm32f3xx/soc/stm32f301x8.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f301x8.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral�s registers hardware * ****************************************************************************** * @attention @@ -2831,18 +2831,12 @@ typedef struct #define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) -#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR19_Pos (19U) #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR20_Pos (20U) #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR_MR21_Pos (21U) -#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ -#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ #define EXTI_IMR_MR22_Pos (22U) #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ @@ -2855,24 +2849,12 @@ typedef struct #define EXTI_IMR_MR25_Pos (25U) #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR_MR26_Pos (26U) -#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */ -#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */ #define EXTI_IMR_MR27_Pos (27U) #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ -#define EXTI_IMR_MR28_Pos (28U) -#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */ -#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR_MR29_Pos (29U) -#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */ -#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */ #define EXTI_IMR_MR30_Pos (30U) #define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */ #define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */ -#define EXTI_IMR_MR31_Pos (31U) -#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */ -#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -2893,20 +2875,32 @@ typedef struct #define EXTI_IMR_IM15 EXTI_IMR_MR15 #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 +#if defined(EXTI_IMR_MR18) #define EXTI_IMR_IM18 EXTI_IMR_MR18 +#endif #define EXTI_IMR_IM19 EXTI_IMR_MR19 #define EXTI_IMR_IM20 EXTI_IMR_MR20 +#if defined(EXTI_IMR_MR21) #define EXTI_IMR_IM21 EXTI_IMR_MR21 +#endif #define EXTI_IMR_IM22 EXTI_IMR_MR22 #define EXTI_IMR_IM23 EXTI_IMR_MR23 #define EXTI_IMR_IM24 EXTI_IMR_MR24 #define EXTI_IMR_IM25 EXTI_IMR_MR25 +#if defined(EXTI_IMR_MR26) #define EXTI_IMR_IM26 EXTI_IMR_MR26 +#endif #define EXTI_IMR_IM27 EXTI_IMR_MR27 +#if defined(EXTI_IMR_MR28) #define EXTI_IMR_IM28 EXTI_IMR_MR28 +#endif +#if defined(EXTI_IMR_MR29) #define EXTI_IMR_IM29 EXTI_IMR_MR29 +#endif #define EXTI_IMR_IM30 EXTI_IMR_MR30 +#if defined(EXTI_IMR_MR31) #define EXTI_IMR_IM31 EXTI_IMR_MR31 +#endif #define EXTI_IMR_IM_Pos (0U) #define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */ @@ -2967,18 +2961,12 @@ typedef struct #define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) -#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ #define EXTI_EMR_MR19_Pos (19U) #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ #define EXTI_EMR_MR20_Pos (20U) #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ -#define EXTI_EMR_MR21_Pos (21U) -#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ -#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ #define EXTI_EMR_MR22_Pos (22U) #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ @@ -2991,24 +2979,12 @@ typedef struct #define EXTI_EMR_MR25_Pos (25U) #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ -#define EXTI_EMR_MR26_Pos (26U) -#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */ -#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */ #define EXTI_EMR_MR27_Pos (27U) #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ -#define EXTI_EMR_MR28_Pos (28U) -#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */ -#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */ -#define EXTI_EMR_MR29_Pos (29U) -#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */ -#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */ #define EXTI_EMR_MR30_Pos (30U) #define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */ #define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */ -#define EXTI_EMR_MR31_Pos (31U) -#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */ -#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -3029,20 +3005,32 @@ typedef struct #define EXTI_EMR_EM15 EXTI_EMR_MR15 #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 +#if defined(EXTI_EMR_MR18) #define EXTI_EMR_EM18 EXTI_EMR_MR18 +#endif #define EXTI_EMR_EM19 EXTI_EMR_MR19 #define EXTI_EMR_EM20 EXTI_EMR_MR20 +#if defined(EXTI_EMR_MR21) #define EXTI_EMR_EM21 EXTI_EMR_MR21 +#endif #define EXTI_EMR_EM22 EXTI_EMR_MR22 #define EXTI_EMR_EM23 EXTI_EMR_MR23 #define EXTI_EMR_EM24 EXTI_EMR_MR24 #define EXTI_EMR_EM25 EXTI_EMR_MR25 +#if defined(EXTI_EMR_MR26) #define EXTI_EMR_EM26 EXTI_EMR_MR26 +#endif #define EXTI_EMR_EM27 EXTI_EMR_MR27 +#if defined(EXTI_EMR_MR28) #define EXTI_EMR_EM28 EXTI_EMR_MR28 +#endif +#if defined(EXTI_EMR_MR29) #define EXTI_EMR_EM29 EXTI_EMR_MR29 +#endif #define EXTI_EMR_EM30 EXTI_EMR_MR30 +#if defined(EXTI_EMR_MR31) #define EXTI_EMR_EM31 EXTI_EMR_MR31 +#endif /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) @@ -3099,30 +3087,18 @@ typedef struct #define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) -#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR19_Pos (19U) #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR20_Pos (20U) #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21_Pos (21U) -#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ -#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ #define EXTI_RTSR_TR22_Pos (22U) #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ -#define EXTI_RTSR_TR29_Pos (29U) -#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */ -#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */ #define EXTI_RTSR_TR30_Pos (30U) #define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */ #define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */ -#define EXTI_RTSR_TR31_Pos (31U) -#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */ -#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -3143,14 +3119,40 @@ typedef struct #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#if defined(EXTI_RTSR_TR18) #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 +#endif #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 +#if defined(EXTI_RTSR_TR21) #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 +#endif #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 +#if defined(EXTI_RTSR_TR23) +#define EXTI_RTSR_RT23 EXTI_RTSR_TR23 +#endif +#if defined(EXTI_RTSR_TR24) +#define EXTI_RTSR_RT24 EXTI_RTSR_TR24 +#endif +#if defined(EXTI_RTSR_TR25) +#define EXTI_RTSR_RT25 EXTI_RTSR_TR25 +#endif +#if defined(EXTI_RTSR_TR26) +#define EXTI_RTSR_RT26 EXTI_RTSR_TR26 +#endif +#if defined(EXTI_RTSR_TR27) +#define EXTI_RTSR_RT27 EXTI_RTSR_TR27 +#endif +#if defined(EXTI_RTSR_TR28) +#define EXTI_RTSR_RT28 EXTI_RTSR_TR28 +#endif +#if defined(EXTI_RTSR_TR29) #define EXTI_RTSR_RT29 EXTI_RTSR_TR29 +#endif #define EXTI_RTSR_RT30 EXTI_RTSR_TR30 +#if defined(EXTI_RTSR_TR31) #define EXTI_RTSR_RT31 EXTI_RTSR_TR31 +#endif /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) @@ -3207,30 +3209,18 @@ typedef struct #define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) -#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR19_Pos (19U) #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR20_Pos (20U) #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21_Pos (21U) -#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ -#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ #define EXTI_FTSR_TR22_Pos (22U) #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ -#define EXTI_FTSR_TR29_Pos (29U) -#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */ -#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */ #define EXTI_FTSR_TR30_Pos (30U) #define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */ #define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */ -#define EXTI_FTSR_TR31_Pos (31U) -#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */ -#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -3251,14 +3241,40 @@ typedef struct #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 -#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 -#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 -#define EXTI_FTSR_FT20 EXTI_FTSR_TR20 -#define EXTI_FTSR_FT21 EXTI_FTSR_TR21 -#define EXTI_FTSR_FT22 EXTI_FTSR_TR22 -#define EXTI_FTSR_FT29 EXTI_FTSR_TR29 -#define EXTI_FTSR_FT30 EXTI_FTSR_TR30 -#define EXTI_FTSR_FT31 EXTI_FTSR_TR31 +#if defined(EXTI_FTSR_TR18) +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 +#endif +#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 +#define EXTI_FTSR_FT20 EXTI_FTSR_TR20 +#if defined(EXTI_FTSR_TR21) +#define EXTI_FTSR_FT21 EXTI_FTSR_TR21 +#endif +#define EXTI_FTSR_FT22 EXTI_FTSR_TR22 +#if defined(EXTI_FTSR_TR23) +#define EXTI_FTSR_FT23 EXTI_FTSR_TR23 +#endif +#if defined(EXTI_FTSR_TR24) +#define EXTI_FTSR_FT24 EXTI_FTSR_TR24 +#endif +#if defined(EXTI_FTSR_TR25) +#define EXTI_FTSR_FT25 EXTI_FTSR_TR25 +#endif +#if defined(EXTI_FTSR_TR26) +#define EXTI_FTSR_FT26 EXTI_FTSR_TR26 +#endif +#if defined(EXTI_FTSR_TR27) +#define EXTI_FTSR_FT27 EXTI_FTSR_TR27 +#endif +#if defined(EXTI_FTSR_TR28) +#define EXTI_FTSR_FT28 EXTI_FTSR_TR28 +#endif +#if defined(EXTI_FTSR_TR29) +#define EXTI_FTSR_FT29 EXTI_FTSR_TR29 +#endif +#define EXTI_FTSR_FT30 EXTI_FTSR_TR30 +#if defined(EXTI_FTSR_TR31) +#define EXTI_FTSR_FT31 EXTI_FTSR_TR31 +#endif /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) @@ -3315,30 +3331,18 @@ typedef struct #define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) -#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ -#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER19_Pos (19U) #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER20_Pos (20U) #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21_Pos (21U) -#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ -#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ #define EXTI_SWIER_SWIER22_Pos (22U) #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ -#define EXTI_SWIER_SWIER29_Pos (29U) -#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */ -#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */ #define EXTI_SWIER_SWIER30_Pos (30U) #define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */ #define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */ -#define EXTI_SWIER_SWIER31_Pos (31U) -#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */ -#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -3359,14 +3363,40 @@ typedef struct #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 -#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 -#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 -#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 -#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 -#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 -#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29 -#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30 -#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 +#if defined(EXTI_SWIER_SWIER18) +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 +#endif +#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 +#if defined(EXTI_SWIER_SWIER21) +#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 +#endif +#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 +#if defined(EXTI_SWIER_SWIER23) +#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 +#endif +#if defined(EXTI_SWIER_SWIER24) +#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24 +#endif +#if defined(EXTI_SWIER_SWIER25) +#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25 +#endif +#if defined(EXTI_SWIER_SWIER26) +#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26 +#endif +#if defined(EXTI_SWIER_SWIER27) +#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27 +#endif +#if defined(EXTI_SWIER_SWIER28) +#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28 +#endif +#if defined(EXTI_SWIER_SWIER29) +#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29 +#endif +#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30 +#if defined(EXTI_SWIER_SWIER31) +#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31 +#endif /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) @@ -3423,30 +3453,18 @@ typedef struct #define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) -#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ -#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ #define EXTI_PR_PR19_Pos (19U) #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ #define EXTI_PR_PR20_Pos (20U) #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ -#define EXTI_PR_PR21_Pos (21U) -#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ -#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ #define EXTI_PR_PR22_Pos (22U) #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ -#define EXTI_PR_PR29_Pos (29U) -#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */ -#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */ #define EXTI_PR_PR30_Pos (30U) #define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */ #define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */ -#define EXTI_PR_PR31_Pos (31U) -#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */ -#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -3456,6 +3474,7 @@ typedef struct #define EXTI_PR_PIF4 EXTI_PR_PR4 #define EXTI_PR_PIF5 EXTI_PR_PR5 #define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF6 EXTI_PR_PR6 #define EXTI_PR_PIF7 EXTI_PR_PR7 #define EXTI_PR_PIF8 EXTI_PR_PR8 #define EXTI_PR_PIF9 EXTI_PR_PR9 @@ -3467,14 +3486,40 @@ typedef struct #define EXTI_PR_PIF15 EXTI_PR_PR15 #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 -#define EXTI_PR_PIF18 EXTI_PR_PR18 -#define EXTI_PR_PIF19 EXTI_PR_PR19 -#define EXTI_PR_PIF20 EXTI_PR_PR20 -#define EXTI_PR_PIF21 EXTI_PR_PR21 -#define EXTI_PR_PIF22 EXTI_PR_PR22 -#define EXTI_PR_PIF29 EXTI_PR_PR29 -#define EXTI_PR_PIF30 EXTI_PR_PR30 -#define EXTI_PR_PIF31 EXTI_PR_PR31 +#if defined(EXTI_PR_PR18) +#define EXTI_PR_PIF18 EXTI_PR_PR18 +#endif +#define EXTI_PR_PIF19 EXTI_PR_PR19 +#define EXTI_PR_PIF20 EXTI_PR_PR20 +#if defined(EXTI_PR_PR21) +#define EXTI_PR_PIF21 EXTI_PR_PR21 +#endif +#define EXTI_PR_PIF22 EXTI_PR_PR22 +#if defined(EXTI_PR_PR23) +#define EXTI_PR_PIF23 EXTI_PR_PR23 +#endif +#if defined(EXTI_PR_PR24) +#define EXTI_PR_PIF24 EXTI_PR_PR24 +#endif +#if defined(EXTI_PR_PR25) +#define EXTI_PR_PIF25 EXTI_PR_PR25 +#endif +#if defined(EXTI_PR_PR26) +#define EXTI_PR_PIF26 EXTI_PR_PR26 +#endif +#if defined(EXTI_PR_PR27) +#define EXTI_PR_PIF27 EXTI_PR_PR27 +#endif +#if defined(EXTI_PR_PR28) +#define EXTI_PR_PIF28 EXTI_PR_PR28 +#endif +#if defined(EXTI_PR_PR29) +#define EXTI_PR_PIF29 EXTI_PR_PR29 +#endif +#define EXTI_PR_PIF30 EXTI_PR_PR30 +#if defined(EXTI_PR_PR31) +#define EXTI_PR_PIF31 EXTI_PR_PR31 +#endif #define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */ @@ -3482,21 +3527,19 @@ typedef struct #define EXTI_IMR2_MR32_Pos (0U) #define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */ #define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */ -#define EXTI_IMR2_MR33_Pos (1U) -#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */ -#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */ -#define EXTI_IMR2_MR34_Pos (2U) -#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */ -#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */ -#define EXTI_IMR2_MR35_Pos (3U) -#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */ -#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */ /* References Defines */ -#define EXTI_IMR2_IM32 EXTI_IMR2_MR32 -#define EXTI_IMR2_IM33 EXTI_IMR2_MR33 -#define EXTI_IMR2_IM34 EXTI_IMR2_MR34 -#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 + +#define EXTI_IMR2_IM32 EXTI_IMR2_MR32 +#if defined(EXTI_IMR2_MR33) +#define EXTI_IMR2_IM33 EXTI_IMR2_MR33 +#endif +#if defined(EXTI_IMR2_MR34) +#define EXTI_IMR2_IM34 EXTI_IMR2_MR34 +#endif +#if defined(EXTI_IMR2_MR35) +#define EXTI_IMR2_IM35 EXTI_IMR2_MR35 +#endif #define EXTI_IMR2_IM_Pos (0U) #define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */ @@ -3506,69 +3549,87 @@ typedef struct #define EXTI_EMR2_MR32_Pos (0U) #define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */ #define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */ -#define EXTI_EMR2_MR33_Pos (1U) -#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */ -#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */ -#define EXTI_EMR2_MR34_Pos (2U) -#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */ -#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */ -#define EXTI_EMR2_MR35_Pos (3U) -#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */ -#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */ /* References Defines */ -#define EXTI_EMR2_EM32 EXTI_EMR2_MR32 -#define EXTI_EMR2_EM33 EXTI_EMR2_MR33 -#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 -#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 +#define EXTI_EMR2_EM32 EXTI_EMR2_MR32 +#if defined(EXTI_EMR2_MR33) +#define EXTI_EMR2_EM33 EXTI_EMR2_MR33 +#endif +#if defined(EXTI_EMR2_MR34) +#define EXTI_EMR2_EM34 EXTI_EMR2_MR34 +#endif +#if defined(EXTI_EMR2_MR35) +#define EXTI_EMR2_EM35 EXTI_EMR2_MR35 +#endif /****************** Bit definition for EXTI_RTSR2 register ********************/ #define EXTI_RTSR2_TR32_Pos (0U) #define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */ -#define EXTI_RTSR2_TR33_Pos (1U) -#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */ -#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */ /* References Defines */ -#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32 -#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33 +#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32 +#if defined(EXTI_RTSR2_TR33) +#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33 +#endif +#if defined(EXTI_RTSR2_TR34) +#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34 +#endif +#if defined(EXTI_RTSR2_TR35) +#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35 +#endif /****************** Bit definition for EXTI_FTSR2 register ******************/ #define EXTI_FTSR2_TR32_Pos (0U) #define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */ #define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */ -#define EXTI_FTSR2_TR33_Pos (1U) -#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */ -#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */ /* References Defines */ -#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32 -#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33 +#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32 +#if defined(EXTI_FTSR2_TR33) +#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33 +#endif +#if defined(EXTI_FTSR2_TR34) +#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34 +#endif +#if defined(EXTI_FTSR2_TR35) +#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35 +#endif /****************** Bit definition for EXTI_SWIER2 register *****************/ #define EXTI_SWIER2_SWIER32_Pos (0U) #define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */ #define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */ -#define EXTI_SWIER2_SWIER33_Pos (1U) -#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */ -#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */ /* References Defines */ -#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32 -#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33 +#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32 +#if defined(EXTI_SWIER2_SWIER33) +#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33 +#endif +#if defined(EXTI_SWIER2_SWIER34) +#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34 +#endif +#if defined(EXTI_SWIER2_SWIER35) +#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35 +#endif /******************* Bit definition for EXTI_PR2 register *******************/ #define EXTI_PR2_PR32_Pos (0U) #define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */ #define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */ -#define EXTI_PR2_PR33_Pos (1U) -#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */ -#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */ /* References Defines */ -#define EXTI_PR2_PIF32 EXTI_PR2_PR32 -#define EXTI_PR2_PIF33 EXTI_PR2_PR33 +#define EXTI_PR2_PIF32 EXTI_PR2_PR32 +#if defined(EXTI_PR2_PR33) +#define EXTI_PR2_PIF33 EXTI_PR2_PR33 +#endif +#if defined(EXTI_PR2_PR34) +#define EXTI_PR2_PIF34 EXTI_PR2_PR34 +#endif +#if defined(EXTI_PR2_PR35) +#define EXTI_PR2_PIF35 EXTI_PR2_PR35 +#endif + /******************************************************************************/ /* */ @@ -6513,6 +6574,7 @@ typedef struct #define TIM_CR2_OIS4_Pos (14U) #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!